RESISTIVE RANDOM ACCESS MEMORY AND METHOD FOR PREPARING THE SAME

Abstract

The present disclosure discloses a resistive random access memory, and the resistive random access memory includes a lower electrode layer, a ferroelectric material layer, and an upper electrode layer arranged in sequence from bottom to top, wherein the ferroelectric material layer includes a doped HfO.sub.2 ferroelectric thin film.

Claims

1. A resistive random access memory, comprising, a lower electrode layer, a ferroelectric material layer, and an upper electrode layer arranged in sequence from bottom to top, wherein the ferroelectric material layer comprises a doped HfO.sub.2 ferroelectric thin film.

2. The resistive random access memory according to claim 1, wherein the ferroelectric material layer comprises a HfO.sub.2 ferroelectric thin film doped with at least one element of Zr, Al, Si, and La.

3. The resistive random access memory according to claim 2, wherein a mole percentage of a doping element is 0.1 to 50 mol %.

4. The resistive random access memory according to claim 1, wherein the lower electrode layer comprises one or more of elementary substances W, Al, Ti, Ta, Ni, and Hf, and conductive metal compounds TiN and TaN.

5. The resistive random access memory according to claim 1, wherein the upper electrode layer comprises one or more of elementary substances W, Al, Cu, Ru, Ti, and Ta, and conductive metal compounds TiN, TaN, IrO.sub.2, ITO, and IZO.

6. A method for preparing a resistive random access memory, comprising: forming a lower electrode layer on the substrate; forming a ferroelectric material layer on the lower electrode layer, wherein the ferroelectric material layer comprises a doped HfO.sub.2 ferroelectric thin film; and forming an upper electrode layer on the ferroelectric material layer.

7. The method according to claim 6, wherein the ferroelectric material layer comprises a HfO.sub.2 ferroelectric thin film doped with at least one element of Zr, Al, Si, and La.

8. The method according to claim 6, wherein a doping method comprises an atomic layer deposition (ALD) method or a co-sputtered method.

9. The method according to claim 6, wherein after the ferroelectric material layer is formed on the lower electrode layer, an annealing treatment is performed, an annealing temperature is 400 to 1000° C., and an annealing time is 30 to 300 s.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Through following description of the present disclosure with reference to the accompanying drawings, other purposes and advantages of the present disclosure will be apparent and may help a comprehensive understanding of the present disclosure.

[0016] FIG. 1 shows a schematic structural diagram of a resistive random access memory according to an exemplary embodiment of the present disclosure.

[0017] FIG. 2 shows a flowchart of a method for preparing the resistive random access memory of FIG. 1.

[0018] FIG. 3 shows a current-voltage characteristic curve diagram of the resistive random access memory of FIG. 1 in a DC scan mode.

DETAILED DESCRIPTION OF EMBODIMENTS

[0019] In order to make the objectives, technical solutions, and advantages of the present disclosure clearer, the following further describes the present disclosure in detail with reference to specific embodiments and drawings. It should be noted that, in the drawings or description of the specification, similar or identical parts use the same drawing numbers. The implementations not shown or described in the drawings are those known to those of ordinary skill in the art. In addition, although the present disclosure may provide an example of a parameter containing a specific value, it should be understood that the parameter does not need to be exactly equal to the corresponding value, but may be approximated to the corresponding value within an acceptable error tolerance or design constraint. The directional terms mentioned in the embodiments, such as “upper”, “lower”, “front”, “rear”, “left”, “right”, etc., are only directions with reference to the drawings. Therefore, the directional terms used are used to illustrate and not to limit the protection scope of the present disclosure.

[0020] FIG. 1 shows a schematic structural diagram of a resistive random access memory according to an exemplary embodiment of the present disclosure. As shown in FIG. 1, the resistive random access memory includes a lower electrode layer 101, a ferroelectric material layer 201, and an upper electrode layer 301 arranged in sequence from bottom to top, where the ferroelectric material layer 201 includes a doped HfO.sub.2 ferroelectric thin film. In the resistive random access memory according to the embodiment of the present disclosure, by applying the doped HfO.sub.2 ferroelectric thin film to a structure of a metal-insulating layer-metal (MIM) resistive memory, a memory having characteristics of high speed and high endurance of the ferroelectric memory and a characteristic of easy integration of the resistive random access memory may be obtained. As the doped HfO.sub.2 ferroelectric thin film has a polycrystalline structure, it may be better compatible with a substrate, ensuring a stability of a device structure. The resistive random access memory of the present disclosure does not require additional transistors, which may greatly reduce an area of a device, and may be more conducive to three-dimensional integration. Moreover, non-destructive reading is used, no additional write-back operation is required, and the reading efficiency is improved. In addition, the HfO.sub.2 ferroelectric thin film may still maintain good ferroelectric properties at a small thickness, which may greatly increase a current density and further improve a scalability of the memory.

[0021] The lower electrode layer 101 may include one or more of elementary substances W, Al, Ti, Ta, Ni, Hf, and conductive metal compounds TiN and TaN, and may be prepared by one of an electron beam evaporation, a chemical vapor deposition, a pulsed laser deposition, an atomic layer deposition, and a sputtering method. In an embodiment of the present disclosure, a thickness and a shape of the lower electrode layer 101 are not limited.

[0022] The upper electrode layer 301 may include one or more of elementary substances W, Al, Cu, Ru, Ti, Ta, and conductive metal compounds TiN, TaN, IrO.sub.2, ITO, IZO, and may be prepared by one of an electron beam evaporation, a chemical vapor deposition, a pulsed laser deposition, an atomic layer deposition, and a sputtering method. In an embodiment of the present disclosure, a thickness and a shape of the upper electrode layer 301 are not limited.

[0023] The ferroelectric material layer 201 formed between the lower electrode layer 101 and the upper electrode layer 301 may specifically include a HfO.sub.2 ferroelectric thin film doped with at least one element of Zr, Al, Si, and La. The binary oxide HfO.sub.2 has a high dielectric constant, a wide band gap, and a good compatibility with CMOS processes. The HfO.sub.2 thin film has a good ferroelectricity after being doped, and forms a metal-insulating layer-metal (MIM) structure with the lower electrode layer 101 and the upper electrode layer 301. This kind of structure based on ferroelectric material has a characteristic of a diode with adjustable direction. The diode current is modulated by an electric domain flipping (ferroelectric diode phenomenon for short) to realize a function of the resistive random access memory, and due to a mechanism of ferroelectric flipping, a theoretical speed may reach ns level and may be used for memory applications. Furthermore, compared with traditional ferroelectric thin films, the polycrystalline structure of the doped HfO.sub.2 ferroelectric thin film reduces requirements on the substrate. In addition, by virtue of a mature technology combined with silicon base, the reliability and stability of the device may also be guaranteed. In addition, the HfO.sub.2 ferroelectric thin film may still maintain good ferroelectric properties even when a thickness of the HfO.sub.2 ferroelectric thin film is small (10 nm). In comparison, a thickness of a traditional ferroelectric material is generally about 200 nm. As a result, the resistive random access memory of the present disclosure may greatly reduce a thickness of a device, which is conducive to a miniaturization of the memory. In addition, the thickness of the traditional ferroelectric material limits a current density of the memory, which may generally only be maintained at about 20 mA/cm.sup.2. However, in order for the amplifier in a memory readout circuit to effectively read the current, the current density of the device needs to be as high as possible. The resistive random access memory of the present disclosure may maintain the current density at a relatively high level (200 A/cm.sup.2), making the reading of the memory readout circuit more accurate.

[0024] In an embodiment of the present disclosure, a mole percentage of doping elements in the HfO.sub.2 ferroelectric thin film may be 0.1 to 50 mol %, and a doping method may include an atomic layer deposition (ALD) method or a co-sputtered method.

[0025] FIG. 2 shows a flowchart of a method for preparing the resistive random access memory of FIG. 1. As shown in FIG. 2, the method for preparing the resistive random access memory may include the following steps:

[0026] S1, forming a lower electrode layer 101 on a substrate;

[0027] S2, forming a ferroelectric material layer 201 on the lower electrode layer 101, where the ferroelectric material layer 201 may include a doped HfO.sub.2 ferroelectric thin film, specifically, the ferroelectric material layer 201 may include a HfO.sub.2 ferroelectric thin film doped with at least one element of Zr, Al, Si, and La;

[0028] S3, forming an upper electrode layer 301 on the ferroelectric material layer 201.

[0029] Further, after the ferroelectric material layer 201 is formed on the lower electrode layer 101, an annealing treatment is performed, an annealing temperature is in 400 to 1000° C., and an annealing time is in 30 to 300 s.

[0030] FIG. 3 shows a current-voltage characteristic curve of the resistive random access memory of FIG. 1 in a DC scan mode, where a dotted line represents a curve after scanning with a scan voltage of 6V, and a solid line represents a curve after scanning with a scan voltage of −6V. As shown in FIG. 6, when the scan voltage is applied from 0 to 6V, the device exhibits a forward turn-on diode characteristic; when the bias scan voltage is applied from 0 to −6V, the device exhibits a reverse turn-on diode characteristic. Under a reading voltage of 2V, the current density may reach 200 A/cm.sup.2.

[0031] The description is given below based on specific embodiments.

Embodiment 1

[0032] A resistive random access memory based on the Hf.sub.0.5Zr.sub.0.5O.sub.2 ferroelectric layer is prepared, and a process for preparing the same is as follows.

[0033] Step 1: a sputtering method is used to form a TiN lower electrode layer, and process conditions are: a power of 25 W to 500 W; a pressure of 0.1 Pa to 100 Pa; an Ar gas flow rate of 0.5 sccm to 100 sccm; and a thickness of the prepared TiN lower electrode layer is 10 nm to 500 nm.

[0034] Step 2: ALD is used to cyclically grow HfO.sub.2 and ZrO.sub.2 on the TiN lower electrode layer to obtain the Hf.sub.0.5Zr.sub.0.5O.sub.2 ferroelectric layer, and process conditions are: a power of 25 W to 500 W; a pressure of 0.1 Pa to 100 Pa; a gas flow rate of 60 sccm; a temperature of 250° C. to 300° C.; a rate of about 0.07 nm/cycle; and after a cycle of HfO.sub.2 is grown, a cycle of ZrO.sub.2 is grown immediately, the two circles are repeated in this way, so that the two materials are mixed and deposited at a molar ratio of 1:1.

[0035] Step 3: an annealing treatment is performed, an annealing temperature is 400° C., and an annealing time is 30 s.

[0036] Step 4: a sputtering method is used to form a TiN upper electrode layer on the Hf.sub.0.5Zr.sub.0.5O.sub.2 ferroelectric layer, and process conditions are: a power of 25 W to 500 W; a pressure of 0.1 Pa to 100 Pa; an Ar gas flow rate of 0.5 sccm to 100 sccm; and a thickness of the prepared TiN upper electrode layer is 10 nm to 500 nm.

[0037] Thus, the resistive random access memory of Embodiment 1 is completed.

[0038] Although the present disclosure has been described with reference to the accompanying drawings, the embodiments disclosed in the accompanying drawings are intended to exemplify the implementation of the present disclosure and should not be understood as a limitation of the present disclosure.

[0039] Those of ordinary skill in the art will understand that changes may be made to these embodiments without departing from the principle and spirit of the general idea of the present disclosure, and the scope of the present disclosure is defined by the claims and their equivalents.