PROCESS FOR PRODUCING ADJACENT CHIPS COMPRISING LED WIRES AND DEVICE OBTAINED BY THE PROCESS

Abstract

A process for producing at least two adjacent regions, each comprising an array of light-emitting wires connected together in a given region by a transparent conductive layer, comprises: producing, on a substrate, a plurality of individual zones for growing wires extending over an area greater than the cumulative area of the two chips; growing wires in the individual growth zones; removing wires from at least one zone forming an initial free area to define the arrays of wires, the initial free area comprising individual growth zones level with the removed wires; and depositing a transparent conductive layer on each array of wires to electrically connect the wires of a given array of wires, each conductive layer being separated from the conductive layer of the neighbouring region by a free area. A device obtained using the process of the invention is also provided.

Claims

1. A process for producing at least two adjacent chips each comprising an array of light-emitting wires connected together in a given chip by a transparent conductive layer, comprising the following steps: producing, on a substrate, a plurality of individual zones for growing wires extending over an area greater than the cumulative area of said two chips; growing wires (NT.sub.i) in the individual growth zones; removing wires from at least one zone forming an initial free area so as to define said arrays of wires, said initial free area comprising individual growth zones level with the removed wires, which zones are called imprints; and depositing a transparent conductive layer on each array of wires so as to electrically connect the wires of a given array of wires, each conductive layer being separated from the conductive layer of the neighbouring chip by a free area.

2. The process for producing at least two adjacent chips according to claim 1, in which the individual growth zones are apertures (zci.sub.a, zci) defined in a mask located on the surface of said substrate.

3. The process for producing at least two adjacent chips according to claim 1, in which the substrate comprises a nucleation layer on which said mask is located.

4. The process for producing at least two adjacent chips according to claim 1, in which the individual growth zones are nucleation pads (zci.sub.b).

5. The process for producing at least two adjacent chips according to claim 1, in which the transparent conductive layers are deposited so as to partially cover the individual growth zones from which light-emitting wires have been removed.

6. The process for producing at least two adjacent chips according to claim 1, comprising producing electrical pads making it possible to connect electrically said chips, said pads being placed on said corresponding conductive layers.

7. The process for producing at least two adjacent chips according to claim 1, in which the wire removal comprises the following steps: producing a protective mask containing apertures level with an array of wires located on an initial free area of the substrate, said mask encapsulating at least a first array of wires and a second array of wires separated by said initial free area; and removing the wires in said initial free area.

8. The process for manufacturing at least two adjacent chips according to claim 1, in which the wires are removed by a direct etching operation through said protective mask.

9. The process for manufacturing at least two adjacent chips according to claim 8, in which the wires are removed by a direct chemical etching operation through said protective mask, or by a direct dry etching operation through said protective mask, with an RIE or ICP plasma.

10. The process for manufacturing at least two adjacent chips according to claim 1, in which the wires are removed by a mechanical action causing said wires to break.

11. The process for manufacturing a functional support according to claim 10, in which the mechanical action is delivered by ultrasound, or by a high-pressure jet of fluid, or in the presence of a solid tool.

12. The process for manufacturing at least two adjacent chips according to claim 4, in which if the wires are grown from a nucleation layer, the wire removal step is carried out by attacking said nucleation layer chemically.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0072] The invention will be better understood and other advantages will become apparent on reading the following description, which is given by way of nonlimiting example, and by virtue of the appended figures, in which:

[0073] FIG. 1 illustrates a first example LED comprising wires according to the prior art;

[0074] FIG. 2 illustrates a second example LED comprising wires according to the prior art;

[0075] FIG. 3 illustrates a view of an array of wires separated by zones of non-growth in which defects are present in a prior-art configuration;

[0076] FIGS. 4a and 4b illustrate a first example of individual growth zones produced in a growth mask and the growth of wires over a complete area;

[0077] FIGS. 5a and 5b illustrate a second example of individual growth zones produced from nucleation pads and the growth of wires on said pads;

[0078] FIGS. 6a, 6b and 6c illustrate the various steps of the process for producing adjacent chips according to the invention in the case where a growth mask deposited on a nucleation layer is used; and

[0079] FIGS. 7a to 7j illustrate all the steps of an example process for producing two adjacent chips of LED wires according to the invention, and comprising a mechanical operation for removing a subset of wires.

DETAILED DESCRIPTION

[0080] Generally, it is proposed in the present invention to provide a device comprising a set of chips each of which comprises an array of LED wires and which can be produced under uniform growth conditions.

[0081] To do this, the process of the invention comprises a first step of producing individual LED-wire growth zones over an extensive area of a substrate, then the generalized growth of LED wires, followed by localized removal of a subset of LED wires.

[0082] The individual wire growth zones may be produced using various processes known in the art.

[0083] FIG. 4a shows a first variant in which a growth mask 200, comprising apertures corresponding to said individual growth zones zc.sub.ia, is produced on a substrate 100 in a surface zone of width d.sub.SNT. In this way, it is, as is known, possible to grow locally LED wires NT.sub.i from these individual growth zones as illustrated in FIG. 4b, the entire surface SNT of the substrate thus being covered with an array of wires NT.sub.i.

[0084] According to another variant of the invention, the individual growth zones may be produced from nucleation pads zc.sub.ib fabricated on the surface of the substrate 100, as shown in FIG. 5a. FIG. 5b illustrates growth of the wires NT.sub.i from these nucleation pads zc.sub.ib, this growth occurring over the entire surface SNT of the substrate. The area of the substrate 100 located between the nucleation pads zc.sub.ib is advantageously made dielectric by oxidation or nitridation, as described in patent application US 2012/0001303, so as to prevent wires from growing on the surface of the substrate.

[0085] According to the process of the present invention, individual LED chips are defined subsequently.

[0086] For this purpose, FIGS. 6a, 6b and 6c illustrate all of the steps for the case of individual growth zones z.sub.ci produced through a mask 200 deposited on the surface of a nucleation layer 102 on the surface of a substrate 100 comprising a contact layer 101 on its back side. The wires shown are typically wires comprising a wire core 300 and a shell 301. The wires NT.sub.i are thus grown over all of the surface SNT, as shown in FIG. 6a.

[0087] Next, wires are locally and selectively removed at least from between two arrays of wires NT.sub.i1 and NT.sub.2i, leaving an initial free area SL.sub.0 of width d.sub.SL0, as illustrated in FIG. 6b. The wires NT.sub.i1 are located on the surface of growth zones zc.sub.i1, the wires NT.sub.2i are located on the surface of growth zones zc.sub.i2, and the growth zones exempt from wires are imprints zc.sub.i0.

[0088] Next, a dedicated transparent electrode is produced on each array of LED wires, so as to connect said LED wires together within a given LED chip. As shown in FIG. 6c, an electrode layer C.sub.NT1i connects the array of wires NT.sub.i1 and an electrode layer C.sub.NT2i connects the array of wires NT.sub.2i. The two electrode layers are separated from each other by a free area SL that is smaller than the initial free area SL0 so as to make space to position contact pads (not shown), i.e.:

d.sub.SL<d.sub.SL0.

[0089] Thus, FIG. 6c shows the production of two adjacent LED chips that are separate from each other: [0090] a first chip P1 extending over an area of illustrated width d.sub.SP1 comprising an array of LED wires NT.sub.i1 covered by a common electrode layer C.sub.NT1i, and [0091] a second chip P2 extending over an area of illustrated width d.sub.SP2 comprising an array of LED wires NT.sub.2i covered by a common electrode layer C.sub.NT2i; where [0092] each chip comprises individual growth zones with LED wires and growth zones zc.sub.i0 exempt from LED wires that then correspond to imprints left after removal of LED wires from this initial free area.

[0093] Typically, the width da of the free area between two adjacent chips may be comprised between 10 and 200 μm.

[0094] The width of the wireless area, i.e. the initial free area, corresponds to the sum of the following widths, the minimum size of which may be about: [0095] 5 μm for the transparent conductive electrode layer C.sub.NT1i projecting over the substrate for the chip P1; [0096] 10 μm width of free area; and [0097] 5 μm for the transparent conductive electrode layer C.sub.NT2i projecting over the substrate for the chip P2.

[0098] Typically, the width of the part of the transparent electrode layer that extends over the growth zones zc.sub.i0 may be comprised between 5 μm and 50 μm around the corresponding array of wires. The width of the part of the same transparent electrode layer dedicated to connection to the metal pad may be comprised between 50 μm and 200 μm.

[0099] The periodicity of the wires and therefore of the individual growth zones may be comprised between 1 μm and 10 μm.

[0100] Various means may be used in the present invention to remove a localized array of wires.

[0101] Notably, this removal may be carried out with means commonly used in microelectronics after zones in which it is desired to preserve the wires have been protected using a hard mask or a resist mask depending on the processes chosen.

[0102] First Means for Removing an Array of Wires Using a Chemical Etching Process:

[0103] After an array of wires has been coated in a protective mask in order to be preserved, a direct etching operation can be carried out for example using a hot potassium hydroxide KOH solution, in this case a mask resistant to this solution, and therefore a hard mask, possibly made of SiO.sub.2 or SiN, inter alia, is chosen.

[0104] Second Means for Removing an Array of Wires Using a Dry Etching Process:

[0105] After an array of wires has been coated in a protective mask, possibly made of a resist, in order to be preserved, a dry etching operation can be carried out. Advantageously, plasma reactors allowing high etch rates to be obtained may be used.

[0106] For this purpose, two types of RF sources, classed into two reactor categories, namely capacitively coupled (CCP) reactors and inductively coupled (ICP) reactors, and a chlorine-based gas, for example of SiCl.sub.4 and Cl.sub.2 chemistry or a mixture of Cl.sub.2 and Ar, may notably be used

[0107] Third Means for Removing an Array of Wires Using a Chemical Etching Process and a Nucleation Layer:

[0108] For example, for the growth of GaN-based wires on a silicon substrate, a TiN nucleation layer will be used.

[0109] After the wires intended to be preserved have been coated in a protective mask, selective chemical attack of the nucleation layer may be carried out with a solution, possibly a H.sub.2O.sub.2/NH.sub.4OH/H.sub.2O-based solution.

[0110] Fourth Means for Removing an Array of Wires Using a Mechanical Action to Break the Nanowires

[0111] After the wires intended to be preserved have been coated in a protective mask, the carrier is placed in a medium subjected, for example, to ultrasound that will deliver a vibrational mechanical action and therefore break the uncoated, and therefore unprotected, wires.

[0112] The mechanical action may also be applied using a high-pressure jet of water or another fluid (inert gas, CO.sub.2, etc.).

[0113] The mechanical action may even be applied using a solid tool, optionally a cutting or abrasive tool, to deform the wire beyond its breaking point or to wear the wire away.

[0114] Example Embodiment of a Process of the Invention in the Context of Fabrication of a Set of GaN-Wire-Based Chips

[0115] FIGS. 7a to 7j schematically illustrate all of the various steps performed to obtain a device of the invention for a two-chip configuration.

[0116] Step 1 Illustrated in FIG. 7a:

[0117] Wires are produced in a known way in a core/shell configuration such as illustrated in FIG. 2.

[0118] More precisely, on the surface of a substrate 100, covered with a nucleation layer 102, wires NT.sub.i are grown through apertures in a dielectric mask 200, the core of the nanowires 300 is typically made of n-doped GaN and intrinsically undoped GaN, the shell 301 being made of p-doped GaN. The apertures produced in the mask correspond to the individual growth zones zci of the wires. The substrate comprises a lower contact layer 101 on its back side.

[0119] Step 2 Illustrated in FIG. 7b:

[0120] Next, a protective photoresist 400 is deposited over all of the wires NT.sub.i.

[0121] Step 3 Illustrated in FIG. 7c:

[0122] A conventional photolithography operation is used to remove the resist 400 level with the wires that are intended to be removed, in order to leave, on either side of these wires that are intended to be removed, an array of resist-coated wires NT.sub.i1 and an array of resist-coated wires NT.sub.2i.

[0123] Step 4 Illustrated in FIG. 7d:

[0124] The substrate locally covered with resist level with the two arrays of wires NT.sub.i1 and NT.sub.2i, is subjected to the action of ultrasound capable of causing the wires to break in the surface plane of the mask 200.

[0125] In this way, the two arrays of preserved wires NT.sub.i1 and NT.sub.i2 are obtained above individual growth zones zc.sub.i1 and individual growth zones zc.sub.i2, respectively, because they are protected by the protective resist layer, while leaving individual growth zones zc.sub.i0 exposed results in wires not protected by the resist breaking, these locally removed wires leaving corresponding imprints.

[0126] After removal of the wires, these individual growth zones zc.sub.i0 consist of the constituent material of the wires in the illustrated example.

[0127] In this way, an initial free area of width d.sub.SL0 is left between two arrays of wires intended to belong to a first chip and a second chip, respectively, said area containing said imprints.

[0128] Step 5 Illustrated in FIG. 7e:

[0129] Next, all of the protective resist is removed, exposing the two arrays of wires NT.sub.i1 and NT.sub.2i.

[0130] Step 6 Illustrated in FIG. 7f:

[0131] An etch mask intended for the p-type upper contact is then produced using a photoresist 600, which may be identical to the resist 400, after a dielectric layer 500 has been deposited.

[0132] Step 7 Illustrated in FIG. 7g:

[0133] A partial etch of the dielectric layer 500 is then carried out through the masking layer 600.

[0134] Step 8 Illustrated in FIG. 7h:

[0135] The resist layer 600 is then removed leaving the partially etched dielectric layer 500 exposed.

[0136] Step 9 Illustrated in FIG. 7i:

[0137] Next, a transparent conductive control layer 700, possibly and typically made of ITO (indium tin oxide) is deposited, allowing light emitted under the action of an electrical command to be transmitted.

[0138] Step 10 Illustrated in FIG. 7j:

[0139] Lastly, metal contacts 800 are deposited and etched between the wires, the two contacts not necessarily being located in the initial free area.

[0140] In summary, the following various advantages of the process for producing two adjacent chips based on LED wires implemented in the present invention, using uniform growth of wires over an area larger than the cumulative areas of the LED chips, then removal of a subset of wires in order to form an intermediate zone exempt from wires, and thus define adjacent chips, will be recalled: [0141] edge effects are avoided during epitaxy of the wires, thereby obtaining a very high wire growth uniformity on the wafer scale; [0142] parasitic growth of crystals, for example GaN crystals, between the technologically useful patterns is avoided; [0143] a single process can be used for different epitaxial growth techniques, rather than multiple technique-dependent processes being required, thus enabling better control of the processes; [0144] a single design with respect to pre-epitaxy technologies can be used, making organizing the logistics of fabrication easier; and [0145] personalization of the chips at the substrate level is delayed.