Low noise amplifier circuit

Abstract

An amplifier for converting a single-ended input signal to a differential output signal. The amplifier comprises a first transistor, a second transistor, a third transistor and a fourth transistor. The first transistor, configured in common-source or common-emitter mode, receives the single-ended input signal and generates a first part of the differential output signal. The second transistor, also configured in common-source or common-emitter mode, generates a second part of the differential output signal. The third and fourth transistors are capacitively cross-coupled. The amplifier further comprises inductive degeneration such that a source or emitter of the first transistor is connected to a first inductor and a source or emitter of the second transistor is connected to a second inductor.

Claims

1. A low noise amplifier for converting a single-ended input signal to a differential output signal, the amplifier comprising: a first transistor, configured in common-source or common-emitter mode, to receive the single-ended input signal and generate a first part of the differential output signal; a second transistor, configured in common-source or common-emitter mode, to generate a second part of the differential output signal; and a third transistor and a fourth transistor, and wherein the third transistor and forth transistor are cross-coupled and connected to the first and second transistors such that: a drain or collector of the first transistor is coupled to a gate or base of the fourth transistor via a first capacitor; a drain or collector of the second transistor is coupled to a gate or base of the third transistor via a second capacitor; the drain or collector of the first transistor is connected to a source or emitter of the third transistor, the drain or collector of the second transistor is connected to a source or emitter of the fourth transistor; the drain or collector of the first transistor is coupled to a gate or base of the second transistor directly or via a third capacitor; a source or emitter of the first transistor is connected to a first inductor and a source or emitter of the second transistor is connected to a second inductor; and a load impedance coupled to a drain or collector of the third transistor and a drain or collector of the fourth transistor is configured to convert the differential output signal into a differential output voltage; wherein a parasitic ground impedance couples the first inductor and the second inductor of the low noise amplifier to a ground.

2. The low noise amplifier of claim 1, wherein the parasitic ground impedance equals zero Ohms (0Ω).

3. A wireless communication device comprising one or more amplifiers wherein each amplifier of the one or more amplifiers is a low noise amplifier for converting a single-ended input signal to a differential output signal, the amplifier comprising: a first transistor configured in common-source or common-emitter mode, to receive the single-ended input signal and generate a first part of the differential output signal; a second transistor configured in common-source or common-emitter mode, to generate a second part of the differential output signal; and a third transistor and a fourth transistor, and wherein the third transistor and forth transistor are cross-coupled and connected to the first and second transistors such that: a drain or collector of the first transistor is coupled to a gate or base of the fourth transistor via a first capacitor; a drain or collector of the second transistor is coupled to a gate or base of the third transistor via a second capacitor; the drain or collector of the first transistor is connected to a source or emitter of the third transistor, the drain or collector of the second transistor is connected to a source or emitter of the fourth transistor; the drain or collector of the first transistor is coupled to a gate or base of the second transistor directly or via a third capacitor; a source or emitter of the first transistor is connected to a first inductor and a source or emitter of the second transistor is connected to a second inductor; and a load impedance coupled to a drain or collector of the third transistor and a drain or collector of the fourth transistor is configured to convert the differential output signal into a differential output voltage; wherein a parasitic ground impedance couples the first inductor and the second inductor of the low noise amplifier to a ground.

4. A receiver for operating at multiple frequency bands, the receiver comprising: one or more radio-frequency filters configured to receive a single-ended input signal and to generate a single-ended output signal; one or more amplifiers configured to convert a single-ended input signal, being the single-ended output signal generated from the radio-frequency filter, to a differential output signal, wherein each amplifier of the one or more amplifiers is a low noise amplifier for converting a single-ended input signal to a differential output signal, the amplifier comprising: a first transistor configured in common-source or common-emitter mode, to receive the single-ended input signal and generate a first part of the differential output signal; a second transistor configured in common-source or common-emitter mode, to generate a second part of the differential output signal; and a third transistor and a fourth transistor, and wherein the third transistor and forth transistor are cross-coupled and connected to the first and second transistors such that: a drain or collector of the first transistor is coupled to a gate or base of the fourth transistor via a first capacitor; a drain or collector of the second transistor is coupled to a gate or base of the third transistor via a second capacitor; the drain or collector of the first transistor is connected to a source or emitter of the third transistor, the drain or collector of the second transistor is connected to a source or emitter of the fourth transistor; the drain or collector of the first transistor is coupled to a gate or base of the second transistor directly or via a third capacitor; a source or emitter of the first transistor is connected to a first inductor and a source or emitter of the second transistor is connected to a second inductor; and a load impedance coupled to a drain or collector of the third transistor and a drain or collector of the fourth transistor is configured to convert the differential output signal into a differential output voltage; wherein a parasitic ground impedance couples the first inductor and the second inductor of the low noise amplifier to a ground; wherein input impedances of the one or more amplifiers are configured to match output impedances of the one or more radio frequency filters at operating frequencies respectively.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Examples of embodiments herein are described in more detail with reference to attached drawings in which:

(2) FIG. 1 is a schematic diagram illustrating a single-ended-to-differential amplifier with capacitive cross-coupled transistor pair according to prior art.

(3) FIG. 2 is a schematic diagram illustrating a direct conversion receiver with a single-ended-to-differential LNA according to prior art.

(4) FIG. 3 is a schematic diagram illustrating a single-ended-to-differential amplifier according to embodiments herein.

(5) FIG. 4 is a schematic diagram illustrating an analysis model for the single-ended-to-differential amplifier shown in FIG. 3.

(6) FIG. 5 is a block diagram illustrating a wireless communication device in which embodiments herein may be implemented.

(7) FIG. 6 is a flowchart depicting a method in a receiver according to embodiments herein.

DETAILED DESCRIPTION

(8) Nowadays most receivers in wireless communication devices are based on direct conversion or zero Intermediate Frequency (zero-IF) architectures, because these receiver topologies allow a very high level of integration and low cost. Zero-IF receivers also permit efficient integration of multimode, multiband receivers.

(9) A simplified block diagram of a direct conversion receiver 200 with a single-ended-to-differential LNA 210 is shown in FIG. 2. An antenna 220 feeds a received RF analog signal to a RF filter 230 that performs pre-selection of received RF bands and passes on a selected RF analog signal. The LNA 210 amplifies the selected RF analog signal and drives down-conversion mixers 240, mixers for short, which down-convert the amplified RF analog signal.

(10) The down-converted analog signal is filtered and amplified in low-pass filters and gain stages of Analog Baseband (ABB) 250 and then converted to a digital signal in Analog-to-Digital Converters (ADC) 260. As shown in FIG. 2, the selected RF signal at the LNA 210 input is single-ended but the remaining signal processing before the ADC 260 is carried out with differential signals.

(11) The mixers 240 utilized in an integrated direct conversion receiver are practically always based either on single- or double-balanced circuit topologies. If a mixer operates with a differential Local Oscillator (LO) signal and a single-ended RF signal, it is called single-balanced. However, if a mixer accommodates both differential RF and LO signals, it is called double-balanced.

(12) Double-balanced mixers generate less even-order distortion and provide better port-to-port isolation than their single-balanced counterparts. In addition, single-balanced topologies are more susceptible to noise in the LO signal. For these reasons, double-balanced mixer topologies are preferred and the LNA 210 needs to provide differential drive signals for the double-balanced mixer, as shown in FIG. 2. Embodiments herein is to provide LNA circuits that improve the performance of the receiver 200.

(13) According to embodiments herein, a single-ended-to differential amplifier 300 for converting a single-ended input signal to a differential output signal is shown in FIG. 3. FIG. 3 is a simplified schematic, where all biasing details are omitted. The amplifier 300 may be used as the LNA 210 in the receiver in FIG. 2.

(14) As shown in FIG. 3, the amplifier 300 comprises a first transistor 301, M.sub.1, a second transistor 302, M.sub.2, a third transistor 303, M.sub.3 and a fourth transistor 304, M.sub.4. Although transistors shown in FIG. 3 are Metal-Oxide-Semiconductor (MOS) transistors with terminal names of gate, drain and source, it is also possible to use other types of transistor, for example, Bipolar Junction Transistors (BJT) with corresponding terminal names of base, collector and emitter.

(15) The first transistor 301, configured in common-source or common-emitter mode, receives the single-ended input signal and generates a first part of the differential output signal, i.e. the output current i.sub.OUT+. The second transistor 302, also configured in common-source or common-emitter mode, generates a second part of the differential output signal, i.e. the output current i.sub.OUT−. The third and fourth transistors 303,304 are capacitively cross-coupled and connected to the first and second transistors 301,302.

(16) Further, as shown in FIG. 3, detailed connections of the first, second, third and fourth transistors 301,302,303,304 are: a drain or collector of the first transistor 301 is coupled to a gate or base of the fourth transistor 304 via a first capacitor 311, C.sub.1; a drain or collector of the second transistor 302 is coupled to a gate or base of the third transistor 303 via a second capacitor 312, C.sub.2; further, the drain or collector of the first transistor 301 is coupled to a gate or base of the second transistor 302 via a third capacitor 313, C.sub.3; and furthermore the drain or collector of the first transistor 301 is connected to a source or emitter of the third transistor 303, the drain or collector of the second transistor 302 is connected to a source or emitter of the fourth transistor 304.

(17) According to some embodiments, the third capacitor C.sub.3 may be replaced with a short circuit. In that case the gate or base of the second transistor 302 is directly connected to the drain or collector of the first transistor 301.

(18) The amplifier 300 further comprises inductive degeneration such that a source or emitter of the first transistor 301 is connected to a first inductor 321, L.sub.S1, and a source or emitter of the second transistor 302 is connected to a second inductor 322, L.sub.S2.

(19) According to some embodiments, degeneration inductors 321 and 322, i.e. L.sub.S1 and L.sub.S2, may also be implemented with a single differential inductor. Then, the amplifier 300 comprises a differential degenerating inductance such that the source or emitter of the first transistor 301 is connected to a first terminal of the differential inductor and the source or emitter of the second transistor 302 is connected to a second terminal of the differential inductor. Depending on the differential inductor topology, a middle access terminal of the differential inductor may be connected to a ground.

(20) The amplifier 300 further comprises a matching circuit 330. The gate or base of the first transistor 301 is coupled to the single-ended input signal through the matching circuit 330. In FIG. 3, Z.sub.GND represents a parasitic ground impedance, ideally Z.sub.GND=0Ω. The matching circuit 330 is usually implemented with off-chip high-Quality (high-Q) passive components. Most often, one or two passive components are sufficient to match the amplifier input impedance at the frequency of interest to the impedance of an RF filter, e.g. 50Ω. The matching circuit 330 may comprise, for instance, starting from the gate of the first transistor 301, a series inductance and a parallel capacitance between the amplifier 300 input terminal, i.e. the terminal named V.sub.IN and the ground. In FIG. 3, the first, second and third capacitors 311,312,313, i.e. C.sub.1, C.sub.2, and C.sub.3 are assumed to act as short-circuits at the operation frequency of interest.

(21) At the frequency of interest, the input matching circuit 330 together with the first transistor 301, which is the inductively degenerated common-source transistor M.sub.1, matches the amplifier 300 input impedance to the characteristic impedance of the RF filter 230. The first transistor 301 also amplifies the input voltage V.sub.IN across the gate-source of the first transistor 301. In the following, the first transistor 301, M.sub.1, converts the amplified version of the input voltage V.sub.IN or its gate-source voltage V.sub.GS1 to a first part of the differential output current i.sub.OUT+. The second transistor 302, which is the common-source transistor M.sub.2, is responsible for converting its gate-source voltage V.sub.GS2 to a second part of, i.e. the complementary of the differential output current i.sub.OUT−. Moreover, thanks to the cross-coupled third and fourth transistors 303,304, i.e. M.sub.3 and M.sub.4, the output currents i.sub.OUT+ and i.sub.OUT− are well-balanced.

(22) As a summary, the amplifier 300 being a single-ended-to-differential amplifier, converts the input signal, the voltage v.sub.IN applied via the input matching network 330 to the gate or base of the first transistor 301, M.sub.1, to a differential output signal, i.e. the output current i.sub.OUT=i.sub.OUT+−i.sub.OUT−, where i.sub.OUT+=i.sub.OUT−, available at the drains or collectors of the cross-coupled third and fourth transistors 303, 304, M.sub.3 and M.sub.4. At the output of the amplifier 300, the differential output current may be converted to a differential output voltage v.sub.OUT=Z.sub.L*i.sub.OUT by a load impedance Z.sub.L if needed.

(23) Now, detailed operations of the single-ended-to-differential converting in the amplifier 300 are described. By inspection of the amplifier 300 in FIG. 3, the output currents can be written as
i.sub.OUT+=g.sub.m3(v.sub.2−v.sub.1)  (1)
i.sub.OUT−=g.sub.m4(v.sub.1−v.sub.2)  (2)

(24) Where, v.sub.1 and v.sub.2 are voltages at nodes 1 and 2, and g.sub.m3,g.sub.m4 are transconductances of the third transistor M.sub.3 and the fourth transistor M.sub.4 respectively. By choosing g.sub.m3=g.sub.m4
i.sub.OUT−=g.sub.m3(v.sub.1−v.sub.2)=−g.sub.m3(v.sub.2−v.sub.1)=−i.sub.OUT+  (3)

(25) Thus well-balanced output currents are obtained.

(26) At a frequency f.sub.0 of interest, an input impedance Z.sub.IN of the amplifier 300 is designed to match the characteristic RF pre-selection filter impedance R.sub.s, also called as a source resistance, usually R.sub.s=50Ω:
Z.sub.IN(ω.sub.0)=R.sub.s  (4)

(27) Where ω.sub.0=2πf.sub.0. In addition, at the operation frequency of f.sub.0, while impedance matched, i.e. the input impedance of the amplifier 300 is matched to the source resistance, or condition in Equation (4) is fulfilled, the magnitude of the differential output current can be approximated as
|i.sub.OUT (ω.sub.0)|=|i.sub.OUT+−i.sub.OUT−|=2|i.sub.OUT+|=2g.sub.m1|v.sub.GS1|=2g.sub.m1Qv.sub.IN  (5)

(28) where g.sub.m1 is the transconductance of the first transistor M.sub.1, v.sub.GS1 is the gate-source voltage of the first transistor M.sub.1, and Q is a quality factor, Q-factor, of the input matching circuit 330 and is expressed as

(29) $\begin{array}{cc}Q=.Math.\frac{v_{\mathrm{GS}1}\left({\omega }_0\right)}{v_{\mathrm{IN}}}.Math.=\frac{.Math.v_{\mathrm{GS}1}\left({\omega }_0\right).Math.}{v_{\mathrm{IN}}}& \left(6\right)\end{array}$

(30) Accordingly, the equivalent transconductance of the amplifier 300 is given as

(31) $\begin{array}{cc}{G}_m=\frac{.Math.i_{\mathrm{OUT}}\left({\omega }_0\right).Math.}{v_{\mathrm{IN}}}=2g_{m1}Q& \left(7\right)\end{array}$

(32) It can be seen that Equation (7) describes how the single-ended input voltage v.sub.IN is converted to a differential output current i.sub.OUT and the conversion gain in terms of transconductance is 2g.sub.m1Q.

(33) Also, when impedance matched at the frequency of interest, an input current magnitude of the amplifier 300 is expressed as

(34) $\begin{array}{cc}.Math.i_{\mathrm{IN}}\left({\omega }_0\right).Math.=\frac{v_{\mathrm{IN}}}{.Math.Z_{\mathrm{IN}}\left({\omega }_0\right).Math.}=\frac{v_{\mathrm{IN}}}{R_s}& \left(8\right)\end{array}$

(35) Thus, the amplifier 300 output current given by (5) is written as
|i.sub.OUT(ω.sub.0)|=2g.sub.m1Qv.sub.IN=2g.sub.m1QR.sub.s|i.sub.IN(ω.sub.0)|  (9)

(36) Thus, a current gain of the amplifier 300 at impedance match is given as

(37) $\begin{array}{cc}.Math.\frac{i_{\mathrm{OUT}}\left({\omega }_0\right)}{i_{\mathrm{IN}}\left({\omega }_0\right)}.Math.=2g_{m1}{\mathrm{QR}}_s& \left(10\right)\end{array}$

(38) In practice, 2g.sub.m1QR.sub.s»1 and thus
|i.sub.OUT (ω.sub.0)|»|i.sub.IN (ω.sub.0)|  (11)

(39) Using the approximation expressed in Equation (11) at impedance match, the Kirchhoff's current law for node 3 can be written as
v.sub.3Z.sub.GND.sup.−1≈i.sub.OUT++i.sub.OUT−  (12)

(40) Where, v.sub.3 is a voltage across the parasitic ground impedance Z.sub.GND. Since i.sub.OUT+=−i.sub.OUT−, thus
v.sub.3Z.sub.GND.sup.−1≈i.sub.OUT++i.sub.OUT−≈0  (13)
and therefore
v.sub.3≈0  (14)

(41) Thus, the voltage across the parasitic ground impedance Z.sub.GND is close to zero. In other words, practically no current flows through Z.sub.GND at the operation frequency f.sub.0. The residual RF current that flows thorough the parasitic ground impedance Z.sub.GND in the single-ended-to-differential amplifier 300 is due to the input current expressed in Equation (8). Compared to the current that flows via ground impedance in a truly single-ended inductively degenerated common-source amplifier, the parasitic ground RF current in the single-ended-to-differential amplifier 300 according to embodiments herein is a factor of 2g.sub.m1QR.sub.s smaller, i.e. the current gain expressed in Equation (10). As a result, in the single-ended-to-differential amplifier 300, the parasitic ground-impedance has only a minor effect, for example, on the equivalent transconductance, input matching and input impedance. This is beneficial, because inaccurately modeled Integrated Circuit (IC) package ground pins etc., will now have an ignorable effect on performance of the amplifier 300. As a result, the amplifier 300 according to embodiments herein may lower time-to-market due to an enhanced design cycle, as discussed above.

(42) In the amplifier 300 herein, noise and nonlinearity due to the second transistor M.sub.2 are cancelled at the output current. FIG. 4 shows an analyze model of the amplifier 300, the same reference numbers used in FIG. 3 are used in FIG. 4 for the same components. As shown in FIG. 4, the noise or weak nonlinearity due to the second transistor M.sub.2 is represented by a current source of i.sub.n2. Again, Z.sub.GND represents a parasitic ground impedance and Rs is source resistance, usually Rs=50Ω.

(43) To analyze the output current i.sub.OUT+ due to i.sub.n2, the amplifier 300 input is connected to ground via the source resistor Rs. Now, the output currents are given by
i.sub.OUT+=g.sub.m3(v.sub.2−v.sub.1)=g.sub.m1v.sub.GS1  (15)
i.sub.OUT−=i.sub.n2+g.sub.m2v.sub.GS2=g.sub.m4(v.sub.1−v.sub.2)  (16)

(44) Here, v.sub.1 and v.sub.2 are voltages at nodes 1 and 2, v.sub.GS1 and v.sub.GS2 are gate-source voltages of M.sub.1 and M.sub.2, and g.sub.mi is transconductance of transistor i, M.sub.i, where i=1, 2, 3, 4. Moreover, the Kirchhoff's current law for node 3 can be written as
v.sub.3Z.sub.GND.sup.−1=i.sub.OUT++i.sub.OUT−=g.sub.m3(v.sub.2−v.sub.1+v.sub.1−v.sub.2)=0  (17)

(45) where equations (15) and (16) have been used and g.sub.m3=g.sub.m4. Thus, again it is found that v.sub.3≈0 and thus i.sub.n2 causes no current flowing via ground impedance Z.sub.GND. Then also v.sub.GS1=0 and i.sub.OUT+=0, which implies that v.sub.1=v.sub.2, since
i.sub.OUT+=g.sub.m3(v.sub.2−v.sub.1)=0  (18)

(46) As a result, also i.sub.OUT−=0 according equation (16). Accordingly, the amplifier 300 output current shows no component due to noise or weak nonlinearity of the second transistor M.sub.2 in the auxiliary branch. This is a clear advantage of the single-ended-to-differential amplifier 300 according to embodiments herein.

(47) As discussed in the background, by employing a single-ended input LNA in a receiver of a wireless communication device, the number of package pins needed for the RFIC can be lowered and the PCB routing between the FEM and RFIC can be simplified. Accordingly, the PCB area and footprint can be reduced. As a result, lower cost and bills-of-material (BOM) can be achieved. The amplifier 300 according to embodiments herein has a single-ended input, therefore the amplifier 300 achieves above advantages.

(48) In addition, the amplifier 300 according to embodiments herein minimizes signal currents at frequencies of interest both at the ground node of the inductively degenerated transistors, such as the first and second transistors M.sub.1 and M.sub.2, and at supply node. Accordingly, the effect of the non-ideal ground and supply impedances on conversion gain, input impedance, noise figure of the amplifier 300 etc. are minimized. Consequently, use of the amplifier 300 can lower time-to-market due to the enhanced design cycle.

(49) The amplifier 300 according to embodiments herein converts the single-ended input signal to a differential output signal. The single-ended-to-differential conversion is performed in such a way, that it has minimal effect on the amplifier noise or linearity performance. This is due to the fact that the noise and nonlinearity due to the second or auxiliary branch of the amplifier 300 needed to generate the complementary output signal are cancelled at the differential output signal. Thus the amplifier 300 according to embodiments herein is suitable for using as an LNA in a receiver of a wireless communication device, as shown in FIG. 5, since its input impedance can be accurately matched to a characteristic impedance of an RF pre-selection filter. As shown in FIG. 5, the wireless communication device 500 comprises a Receiver 510, wherein the amplifier 300 may be implemented. The wireless communication device 500 further comprises a Transmitter 520, a Memory 530 and a Processing unit 540. Moreover, the amplifier 300 may be integrated on the same RFIC with rest of the Receiver 510 and it requires no expensive off-chip inductive balun circuits at the input of the amplifier 300 and no integrated balun circuits at the output of the amplifier 300.

(50) The amplifier 300 according to embodiments herein is also suited for multiband receivers, since the single-ended-to-differential conversion itself is wideband while the amplifier 300 input impedance can be configured to match the RF filter output impedance at frequencies of interest. According some embodiments, a multiband receiver for operating at multiple frequency bands may comprise one or more radio-frequency filters configured to receive a single-ended input signal and to generate a single-ended output signal. The multiband receiver may further comprise one or more amplifiers 300 according to embodiments herein for converting a single-ended input signal, being the single-ended output signal generated from the radio-frequency filter, to a differential output signal. Further, input impedances of the one or more amplifiers 300 are configured to match output impedances of the one or more radio frequency filters at operating frequencies respectively.

(51) Corresponding embodiments of a method in a receiver for operating at multiple frequency bands will now be described with reference to FIG. 6. As mentioned above, the receiver comprises one or more radio-frequency filters and one or more amplifiers 300. The method comprises following actions:

(52) Action 601

(53) The one or more radio-frequency filters receive a single-ended input signal.

(54) Action 602

(55) The one or more radio-frequency filters generate a single-ended output signal.

(56) Action 603

(57) The one or more amplifiers 300 receive the generated single-ended output signal.

(58) Action 604

(59) The one or more amplifiers 300 convert the received single-ended output signal to a differential output signal.

(60) Those skilled in the art will understand that although the amplifier 300 is described with N-channel Metal-Oxide-Semiconductor (NMOS) devices, the amplifier 300 may comprise any other types of devices or transistors, such as Bipolar Junction Transistors (BJT), P-channel MOS (PMOS) devices, Complementary MOS (CMOS) devices etc. When using the word “comprise” or “comprising” it shall be interpreted as non-limiting, i.e. meaning “consist at least of”.

(61) The embodiments herein are not limited to the above described preferred embodiments. Various alternatives, modifications and equivalents may be used. Therefore, the above embodiments should not be taken as limiting the scope of the invention, which is defined by the appending claims.