SILICON WAFER FOR AN ELECTRONIC COMPONENT AND METHOD FOR THE PRODUCTION THEREOF

Abstract

A silicon wafer for an electronic component, having an epitaxially grown silicon layer on a carrier substrate and the silicon layer is removed as a silicon wafer from the carrier substrate, in which at least one p-dopant and at least one n-dopant are introduced into the silicon layer during the epitaxial growth. The dopants are introduced into the silicon layer such that the silicon layer is formed having an electrically active p-doping and an electrically active n-doping, each greater than 1×10.sup.14 cm.sup.−3.

Claims

1. An epitaxially grown silicon wafer for producing an electronic component, the silicon wafer comprising: a p-type doping formed by at least one p-type dopant and an n-type doping formed by at least one n-type dopant, wherein the electrically active concentration of the p-type doping and of the n-type doping is in each case with a concentration in a range of 1×10.sup.14 cm.sup.−3 to 1×10.sup.16 cm.sup.−3.

2. The silicon wafer as claimed in claim 1, wherein the silicon wafer has an electrically active net doping, such that the silicon wafer has a sheet resistance of greater than 1 Ωcm or the silicon wafer has an electrically active net doping of at least 5×10.sup.14 cm.sup.−3, or both.

3. The silicon wafer as claimed in claim 1, wherein the silicon wafer has an electrically active net doping that is substantially constant in a thickness direction.

4. The silicon wafer as claimed in claim 1, wherein the silicon wafer has an electrically active net doping that has a stepped profile or a linear profile in a thickness direction.

5. The silicon wafer as claimed in claim 1, wherein the electrically active net doping has a non-exponential profile in the thickness direction.

6. The silicon wafer as claimed in claim 5, wherein the non-exponential profile is no profile in accordance with Scheil's law.

7. The silicon wafer as claimed in claim 1, wherein an electrically active density of the p-type doping and of the n-type doping is in each case greater than 5×10.sup.14 cm.sup.−3.

8. The silicon wafer as claimed in claim 1, wherein the silicon wafer is at least one of adapted for production of a photovoltaic solar cell, covers at least an area of 10×10 cm.sup.2, has a charge carrier lifetime of at least 300 μs, or has a thickness in the range of 30 μm to 300 μm.

Description

BRIEF DESCRIPTION OF THE DRAWING

[0039] Further preferred features and embodiments are explained below with reference to the figures of the exemplary embodiment.

[0040] In this case:

[0041] FIG. 1 shows one exemplary embodiment of a device for carrying out one exemplary embodiment of the method according to the invention.

[0042] FIG. 2 shows a comparison of the oxygen content in an epitaxially grown silicon wafer according to the present method in comparison with the prior known wafers.

[0043] FIG. 3 shows a comparison of the wafer resistivity distribution of an epitaxially grown silicon wafer according to the present method in comparison with the prion known wafers.

DETAILED DESCRIPTION

[0044] FIG. 1 shows a device for epitaxially producing a silicon layer. The device comprises a process chamber 3 for receiving a carrier substrate 1. The carrier substrate 1 can be moved into and out of the process chamber 3 by a conveying device 6 in the form of a conveyor belt. For this purpose, the process chamber 3 has locks.

[0045] The process chamber 3 is heatable by a heating device 5. Furthermore, a gas stream can be introduced into the process chamber 3 via a gas inlet 4. Gas can be discharged from the process chamber via a gas outlet.

[0046] The device illustrated in FIG. 1 and its operation can be implemented, in principle, in a manner known per se, in particular as described in WO 2012/084187 or DE 10 2015 118 042.

[0047] In one exemplary embodiment of a method according to the invention, a surface (top surface in FIG. 1) of the carrier substrate 1 is firstly porosified. The porosification of a carrier substrate is known per se and serves, in particular, to be able to detach the epitaxially grown silicon layer from the carrier substrate. The carrier substrate itself is likewise formed from silicon.

[0048] The carrier substrate that has been pretreated in this way is moved into the process chamber 3 by the conveying device 6, as far as the approximately central position as illustrated in FIG. 1. This is followed by epitaxially growing a silicon layer 2, wherein the process chamber 3 is heated by the heating device 5 and silicon-containing silane or chlorosilane gas and for example diborane gas containing boron as p-type dopant and phosphine gas containing phosphorus as n-type dopant are introduced via the gas inlet 4. Alternatively, a plurality of gas inlets can be provided, in particular one or more separate gas inlets for each gas.

[0049] The process of epitaxially growing the silicon layer 2 is carried out with process parameters that are substantially known per se. One essential difference is that the gases which contain the p-type dopant and the n-type dopant are supplied in such a high concentration that the silicon layer is formed in the present case with an electrically active p-type doping of 1×10.sup.14 cm.sup.−3 in the present case and with an electrically active n-type doping of 6×10.sup.14 cm.sup.−3 in the present case.

[0050] The silicon layer thus has an electrically active net doping of the n doping type of 5×10.sup.14 cm.sup.−3 and is thus formed as a high-resistance silicon layer with approximately 10 Ωcm.

[0051] Typical process parameters that can be used for this process are 1050° C. process temperature, a flow rate of 50 standard liters/minute hydrogen, 1 standard liter/minute chlorosilane, 0.002 standard liter/minute phosphine dissolved in hydrogen and 0.001 standard liter/minute diborane dissolved in hydrogen.

[0052] Afterward, the carrier substrate 1 with the silicon layer 2 is moved out of the process chamber 3 by the conveying device 6 and the silicon layer 2 is released from the carrier substrate 1. The detached silicon layer 2 thus corresponds to one exemplary embodiment of a silicon wafer according to the invention.

[0053] The carrier substrate has an approximately square surface having an edge length of 10 cm in the present case, such that the resulting silicon wafer also has approximately these dimensions. The resulting silicon wafer has a thickness of 100 μm in the present case.

[0054] In this exemplary embodiment, the concentration both of the n-type dopant and of the p-type dopant was kept constant during the epitaxial growth, such that the silicon layer 2 has an active net doping that is constant in the thickness direction (perpendicular to the front side of the silicon layer 2, said front side being at the top in FIG. 1).

[0055] Alternatively, in a further exemplary embodiment, the gas flow can be varied during the epitaxial growth, such that the silicon layer 2 has an electrically active net doping that has a stepped profile or a linear profile in the thickness direction. In this case, preferred profiles are a stepped or linear profile proceeding from an electrically active net doping of 1×10.sup.14 cm.sup.−3 at the surface of the silicon layer 2 facing the carrier substrate to an electrically active net doping of 1×10.sup.15 cm.sup.−3 at the side of the silicon layer 2 facing away from the carrier substrate 1 (the front side of the silicon layer 2).

[0056] In the case of a stepped profile, steps with a relative concentration change of 10-30%, proceeding from the lower doping level, are advantageous.

[0057] These three profiles mentioned above, of the constant, stepped or linear active net doping, have in common the fact that no exponential profile typical of ingot production methods is present, in particular no profile in accordance with Scheil's law.

[0058] FIG. 2 shows a comparison of the oxygen content of the epitaxially grown silicon wafer 2 according to the present method in comparison with the prior known wafers grown according to the Czochralski method. Here it can be seen that the oxygen content of the present epitaxially grown silicon wafer 2 has over 50 times less oxygen.

[0059] FIG. 3 shows a comparison of the wafer resistivity distribution of an epitaxially grown silicon wafer 2 according to the present method in comparison with the prior known wafers grown according to the Czochralski method. Based on the epitaxial growth, the resistivity distribution can be precisely controlled in comparison to the Czochralski method.