DESIGN AND PACKAGING METHOD FOR PCB BOARD TO AVOID PATCH ELEMENT TOMBSTONE AND PCB BOARD

Abstract

A design method and a packaging method for a PCB board to avoid patch element tombstone, and a PCB board are provided. The method includes: providing at least one patch element placement area on a PCB board, providing pads in each patch element placement area, where each pad group includes two pads, and the two pads are arranged side by side; establishing pad limit areas around the pads; and reflow soldering the patch element to the PCB board. With the above method, the tombstone phenomenon of the patch element can be effectively prevented, the design efficiency is improved, the workload of manual operation of the engineer is reduced, and an error rate is reduced.

Claims

1. A design method for a PCB board to avoid patch element tombstone, comprising: step a1, providing at least one patch element placement area on a PCB board, and providing pads in each of the at least one patch element placement area, wherein each pad group comprises two pads, and the two pads are arranged side by side; and step a2, establishing pad limiting areas around the pads.

2. The design method for the PCB board to avoid patch element tombstone according to claim 1, wherein step a2 comprises: establishing pad limiting areas around all the pads on the PCB board.

3. The design method for the PCB board to avoid patch element tombstone according to claim 1, wherein step a2 comprises: establishing pad limiting areas around a part of the pads on the PCB board; and printing the PCB board, wherein a pad limiting area pattern is printed on the pad limiting area.

4. A packaging method for a PCB board to avoid patch element tombstone, wherein one end of a patch element is made of copper sheet, the other end of the patch element is made of copper wire, or both ends of the patch element are made of copper sheet, and the method comprises: obtaining a PCB board by using the design method for the PCB board to avoid patch element tombstone according to claim 2; and mounting both ends of the patch element on the pad, to perform reflow soldering.

5. A packaging method for a PCB board to avoid patch element tombstone, wherein one end of a patch element is made of copper sheet, the other end of the patch element is made of copper wire, or both ends of the patch element are made of copper sheet, and the method comprises: providing at least one patch element placement area on a PCB board, and providing pads in each of the at least one patch element placement area, wherein each pad group comprises two pads, and the two pads are arranged side by side; establishing pad limiting areas around a part of the pads on the PCB board, wherein pad limiting area patterns are printed around the part of the pads on the PCB board; and mounting the copper sheet end of the patch element on the pad which is printed with pad limiting area patterns, to perform reflow soldering.

6. The packaging method for the PCB board to avoid patch element tombstone according to claim 5, comprising: mounting the copper wire end of the patch element on the pad which is not printed with pad limiting area patterns, to perform reflow soldering.

7. The packaging method for the PCB board to avoid patch element tombstone according to claim 5, wherein the pad limiting area pattern is divided into a left limiting area pattern and a right limiting area pattern, the left limiting area pattern has a symmetric sector shape, and the right limiting area pattern has an arch shape.

8. The packaging method for the PCB board to avoid patch element tombstone according to claim 7, wherein an isolation region is arranged between two adjacent pad limiting area patterns.

9. A PCB board, comprising: patch element placement areas; and pads, wherein the PCB board is provided with at least one patch element placement area, each of the at least one patch element placement area is provided with pads, each pad group comprises two pads, the two pads are arranged side by side, and pad limiting areas are established around the pads.

10. The PCB board according to claim 9, wherein the pad limiting areas are printed with pad limiting area patterns; the pad limiting area pattern is divided into a left limiting area pattern and a right limiting area pattern, the left limiting area pattern has a symmetric sector shape, the right limiting area pattern has an arch shape; and an isolation region is arranged between two adjacent pad limiting area patterns.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The present disclosure will be further described with reference to the drawings hereinafter.

[0026] FIG. 1 is a schematic structural view of a pad limiting area.

[0027] FIG. 2 is a schematic structural view of a PCB board with a pad limiting area.

[0028] Reference numbers in the drawings are listed as follow:

TABLE-US-00001 1 PCB board, 2 patch element placement area, 3 pad, 4 pad limiting area, 5 copper sheet, 6 copper wire, 7 isolation region, 8 patch element.

DETAILED DESCRIPTION OF THE EMBODIMENTS

[0029] A design and packaging method for a PCB board to avoid patch element tombstone, and a PCB board according to the disclosure are described in detail hereinafter with reference to the drawings and embodiments.

First Embodiment

[0030] A design method for a PCB board to avoid patch element tombstone of the disclosure includes the following steps.

[0031] In step a1, two patch element placement areas 2 are provided on a PCB board, and each patch element placement area 2 is provided with pads 3. Each pad group includes two pads 3, and the two pads 3 are arranged side by side.

[0032] In step a2, pad limit areas 4 are established around the pads 3.

[0033] Specifically, in step a2, pad limiting areas 4 are established around all the pads 3 on the PCB board 1; and the PCB board 1 is printed such that a pad limiting area pattern is printed on the pad limiting area 4.

Second Embodiment

[0034] A design method for a PCB board to avoid patch element tombstone of the disclosure includes the following steps.

[0035] In step a1, three patch element placement areas 2 are provided on a PCB board, and each patch element placement area 2 is provided with pads 3. Each pad group includes two pads 3, and the two pads 3 are arranged side by side.

[0036] In step a2, pad limit areas 4 are established around the pads 3.

[0037] Specifically, in step a2, pad limiting areas 4 are established around a part of the pads 3 on the PCB board 1; and the PCB board 1 is printed such that a pad limiting area pattern is printed on the pad limiting area 4.

Third Embodiment

[0038] A packaging method for a PCB board to avoid patch element tombstone according to the disclosure is provided. A patch element 8 is a 0402 patch capacitive element, one end of the patch elements 8 is made of copper sheet 5, the other end of the patch element 8 is made of copper wire 6; or both ends of the patch element 8 are made of copper sheet 5. Pad limiting areas 4 are established around all the pads 3 on the PCB board 1. A PCB board 1 is printed such that a pad limiting area pattern is printed on the pad limiting area 4 to obtain the PCB board 1. Both ends of the patch elements 8 are mounted on the pad 3 to perform reflow soldering by solder paste.

Fourth Embodiment

[0039] A packaging method for a PCB board to avoid patch element tombstone according to the disclosure is provided. The patch element 8 is a 0201 patch capacitive element, one end of the patch element 8 is made of copper sheet 5, the other end of the patch element is made of copper wire 6; or both ends of the patch element 8 are made of copper sheet 5. Pad limiting areas 4 are established around a part of the pads 3 on the PCB board 1. The PCB board 1 is printed such that a pad limiting area pattern is printed on the pad limiting area 4 to obtain the PCB board 1. The copper sheet 5 end of the patch element 8 is mounted on the pads 3 which are printed with pad limiting area patterns to perform reflow soldering by solder paste.

Fifth Embodiment

[0040] A packaging method for a PCB board to avoid patch element tombstone according to the disclosure is provided. The patch element 8 is a 0402 patch capacitive element, one end of the patch element 8 is made of copper sheet 5, and the other end of the patch element 8 is made of copper wire 6. Pad limiting areas 4 are established around a part of the pads 3 on the PCB board 1. The PCB board 1 is printed such that a pad limiting area pattern is printed on the pad limiting area 4, to obtain the PCB board 1. The pad limiting area pattern is divided into a left limiting area pattern and a right limiting area pattern, the left limiting area pattern has a symmetric sector shape, and the right limiting area pattern has an arch shape. The copper sheet 5 end of the patch element 8 is mounted on the pads 3 which are printed with pad limiting area patterns to perform reflow soldering by solder paste. The copper wire 6 end of the patch element 8 is mounted on the pads 3 which are not printed with pad limiting area patterns to perform reflow soldering by solder paste. An isolation region 7 is arranged between two adjacent pad limiting area patterns.

Sixth Embodiment

[0041] A PCB board according to the disclosure includes patch element placement areas 2 and pads 3. The PCB board 1 is provided with at least one patch element placement area 2, each patch element placement area 2 is provided with pads 3, each pad group includes two pads 3, and the two pads 3 are arranged side by side. Pad limiting areas 4 are established around the pads 3. The PCB board is printed, such that the pad limiting areas 4 are printed with pad limiting area patterns. The pad limiting area pattern is divided into a left limiting area pattern and a right limiting area pattern, the left limiting area pattern has a symmetric sector shape, and the right limiting area pattern has an arch shape. An isolation region 7 is arranged between two adjacent pad limiting area patterns.

[0042] Through the above specific embodiments, those skilled in the art can easily implement the present disclosure. However, it should be understood that the present disclosure is not limited to the above six specific embodiments. Based on the disclosed embodiments, those skilled in the art can combine different technical features to implement different technical solutions.

[0043] In addition to the technical features described in the specification, all other techniques are known to those skilled in the art.