Method for measuring a capacitance value

Abstract

A method for measuring a capacitance value of a capacitive sensor uses an integration process involving charge quantities being transferred in successive integration cycles from the capacitive sensor to an integration capacitor. The method includes performing the integration process until the number of integration cycles carried out has reached a number N of integration cycles to be carried out, wherein a starting value N.sub.Start is set to N and an end value N.sub.End is determined. An A/D converter measures a voltage value U.sub.CI(N) at the integration capacitor and the voltage value is added to a voltage sum value U.sub.Total. The number N is increased by a value n, where n is at least one and is less than N.sub.Diff=N.sub.End−N.sub.Start. The steps are repeated until the number N exceeds the end value N.sub.End. The ending voltage sum value is indicative of the capacitance value of the capacitive sensor.

Claims

1. A method for measuring a capacitance value C.sub.M of a capacitive sensor, the method comprising the following steps: (a) performing an initial integration process involving charge quantities being transferred in N successive integration cycles from the capacitive sensor to an integration capacitor, where N is an integer of at least two; (b) measuring immediately after the step (a), by an A/D converter, an initial voltage value at the integration capacitor and adding the initial voltage value to a voltage sum value U.sub.Total; (c) performing a subsequent integration process involving one or more charge quantities further being transferred in n further successive integration cycle or cycles from the capacitive sensor to the integration capacitor, where n is an integer of at least one; (d) measuring immediately after the step (c), by an A/D converter, a subsequent voltage value at the integration capacitor and adding the subsequent voltage value to the voltage sum value U.sub.Total; (e) repeating the steps (c) and (d) until a total number of integration cycles of all of the performed integration processes exceeds a predetermined amount; and (f) evaluating the voltage sum value U.sub.Total as a measurement result, wherein the voltage sum value U.sub.Total is indicative of the capacitance value C.sub.M of the capacitive sensor.

2. The method of claim 1, wherein the value n is a constant value as the step (c) is repeated.

3. The method of claim 1, wherein the value n varies as the step (c) is repeated.

4. A method for measuring a capacitance value C.sub.M of a capacitive sensor using an integration capacitor with a terminal of the capacitive sensor and a first terminal of the integration capacitor being electrically connected at a shared circuit node and the integration capacitor having a known capacitance value C.sub.I that is greater than the capacitance value C.sub.M of the capacitive sensor, the method comprising the following steps: (a) initializing a voltage sum value U.sub.Total to zero; (b) connecting the shared circuit node and a second terminal of the integration capacitor to a ground potential to reset a voltage at the integration capacitor to zero; (c) performing an initial integration process involving charge quantities being transferred in N successive integration cycles from the capacitive sensor to the integration capacitor, where N is an integer of at least two; (d) measuring immediately after the step (c), by an A/D converter, an initial voltage value at the integration capacitor and adding the initial voltage value to the voltage sum value U.sub.Total; (e) performing a subsequent integration process involving one or more charge quantities further being transferred in n further successive integration cycle or cycles from the capacitive sensor to the integration capacitor, where n is an integer of at least one; (f) measuring after performing the step (e), by an A/D converter, a subsequent voltage value at the integration capacitor and adding the subsequent voltage value to the voltage sum value U.sub.Total; (g) repeating the steps (e) and (f) until a total number of all of the performed integration cycles exceeds a predetermined amount; and (h) evaluating the voltage sum value U.sub.Total as a measurement result, wherein the voltage sum value U.sub.Total is indicative of the capacitance value C.sub.M of the capacitive sensor.

5. The method of claim 4, wherein the value n is a constant value as the step (e) is repeated.

6. The method of claim 4, wherein the value n varies as the step (e) is repeated.

7. The method of claim 4 wherein: performing each integration cycle includes keeping the shared circuit node at a potential-free voltage while applying a known supply voltage to a second terminal of the integration capacitor and then disconnecting the known supply voltage from the second terminal of the integration capacitor while connecting the shared circuit node to the ground potential.

8. A system for measuring a capacitance value C.sub.M of a capacitive sensor, the system comprising: an integration capacitor having a known capacitance value C.sub.I that is greater than the capacitance value C.sub.M of the capacitive sensor, wherein a first terminal of the integration capacitor is electrically connected at a shared circuit node to a terminal of the capacitive sensor; an A/D converter; a first switch configured to selectively connect the shared circuit node to a fixed supply voltage, an open circuit, or a ground potential; a second switch configured to selectively connect a second terminal of the integration capacitor to the fixed supply voltage, the A/D converter, or the ground potential; and a controller configured to control the first switch, the second switch, and the A/D converter to (a) perform an initial integration process involving charge quantities being transferred in N successive integration cycles from the capacitive sensor to an integration capacitor, where N is an integer of at least two; (b) measure immediately after the step (a), using the A/D converter, an initial voltage value at the integration capacitor and add the initial voltage value a voltage sum value U.sub.Total; (c) perform a subsequent integration process involving one or more charge quantities further being transferred in n further successive integration cycle or cycles from the capacitive sensor to the integration capacitor, where n is an integer of at least one; (d) measure immediately after the step (c), by an A/D converter, a subsequent voltage value at the integration capacitor and adding the subsequent voltage value to the voltage sum value U.sub.Total; (e) repeat the steps (c) and (d) until a total number of integration cycles of all of the performed integration processes exceeds a predetermined amount; and evaluate the voltage sum value U.sub.Total as a measurement result, wherein the voltage sum value U.sub.Total is indicative of the capacitance value C.sub.M of the capacitive sensor.

9. The system of claim 8, wherein the value n is a constant value as the step (c) is repeated.

10. The system of claim 8, wherein the value n varies as the step (c) is repeated.

11. The system of claim 8 wherein: performing each integration cycle includes the controller controlling the first switch and the second switch to keep the shared circuit node at a potential-free voltage while the fixed supply voltage is connected to the second terminal of the integration capacitor and then disconnect the fixed supply voltage from the second terminal of the integration capacitor while the shared circuit node is connected to the ground potential.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1A illustrates a schematic illustration of a system having an integration capacitor and an arrangement of switches for carrying out an integration process to measure a capacitance value of a capacitive sensor;

(2) FIG. 1B illustrates a timing diagram of the switching of the switches of the system for the system to carry out the integration process including N integration cycles for measuring the capacitance value of the capacitive sensor; and

(3) FIG. 2 illustrates a plot of the voltage (U.sub.CI(N)) at the integration capacitor as a function of the number (N) of integration cycles.

DETAILED DESCRIPTION

(4) Detailed embodiments of the present invention are disclosed herein; however, it is to be understood that the disclosed embodiments are merely exemplary of the present invention that may be embodied in various and alternative forms. The figures are not necessarily to scale; some features may be exaggerated or minimized to show details of particular components. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the present invention.

(5) Referring now to FIG. 1A, a schematic (circuit diagram) illustration of a system having an integration capacitor 2 and an arrangement of first and second switches S1 and S2 for carrying out an integration process to measure a capacitance value C.sub.M of a capacitive sensor 1 is shown. Capacitive sensor 1 forms, for example, a contact sensor having the shape of an electrode. Capacitive sensor 1 has a self-capacitance with a capacitance value C.sub.M with respect to a relative ground or earth potential. When the electrode is touched or approached, for example by a finger of a user, the capacitance value C.sub.M changes due to the contact capacitance of the capacitance value with respect to the ground or earth potential.

(6) The system further includes an integration capacitor 2. The system uses integration capacitor 2, first switch S1, and second switch S2 to implement the integration process to measure the capacitance value C.sub.M of capacitive sensor 1. In the system, to implement the integration process, a terminal of capacitive sensor 1 is electrically connected to a first terminal 2′ of integration capacitor 2 at a shared circuit node 3. Integration capacitor 2 has a known capacitance value C.sub.I that is large compared to the capacitance value C.sub.M of capacitive sensor 1 to be measured (i.e., C.sub.I>>C.sub.M).

(7) Shared circuit node 3 is also electrically connected to first switch S1. Shared circuit node 3, via first switch S1, is selectively (i) connectable to a fixed supply voltage U.sub.V, (ii) potential-free, i.e., held open (NC), or (iii) connectable to the ground or earth potential GND, depending on the switch position of first switch S1.

(8) A second terminal 2″ of integration capacitor 2 is electrically connected to second switch S2. Second terminal 2″ of integration capacitor 2, via second switch S2, is selectively connectable to (i) the fixed supply voltage U.sub.V, (ii) an input of an A/D converter of the system, or (iii) the ground or earth potential GND, depending on the switch position of second switch S2.

(9) The system uses an integration process, the basic steps of which are known, to measure the capacitance value C.sub.M of capacitive sensor 1. The integration process involves small charge quantities being transmitted from capacitive sensor 1 to integration capacitor 2 in multiple successive cycles. After a number N of these charge transfers, referred to as integration cycles, the voltage U.sub.CI(N) that is then present at integration capacitor 2 is measured by A/D converter 4. The voltage U.sub.CI(N) is directly proportional to the capacitance value C.sub.M of capacitive sensor 1. Therefore, the voltage U.sub.CI(N) at integration capacitor 2 is a measure of the capacitance value C.sub.M of capacitive sensor 1.

(10) Referring now to FIG. 1B, with continual reference to FIG. 1A, a timing diagram of the switching of switches S1 and S2 for the system to carry out the integration process including N integration cycles for measuring the capacitance value C.sub.M of capacitive sensor 1 is shown. An exemplary sequence for the integration process is described with reference to the timing diagram. The following steps represent the sequence of an integration cycle of the integration process.

(11) Shared circuit node 3, connected to first terminal 2′ of integration capacitor 2, is held open, and thus potential-free, by first switch S1. Concurrently, the supply voltage U.sub.V is applied to second terminal 2″ of integration capacitor 2 by second switch S2. The supply voltage U.sub.V is then disconnected from second terminal 2″ of integration capacitor 2 by second switch S2 and is held potential-free. Concurrently, shared circuit node 3 is connected to the ground potential GND by first switch S1.

(12) During the course of a measurement, the steps of this integration cycle are carried out repeatedly. Particularly, the integration cycle is repeated successively until the number IZ of integration cycles carried out has reached a predefined number N (“Integration Phase” shown in FIG. 1B). The voltage U.sub.CI(N) at integration capacitor 2 after these N integration cycles is subsequently measured by A/D converter 4 by connecting second terminal 2″ of integration capacitor 2 to the input of A/D converter 4 by second switch S2 (“Detection Phase” shown in FIG. 1B).

(13) The measured (digital) voltage value U.sub.CI(N) is transmitted from A/D converter 4 to a controller 5 of the system. Controller 5 further processes and evaluates the measured (digital) voltage value U.sub.CI(N). Controller 5 controls the sequence of the entire described method and integration process, and for this purpose includes a microcontroller, for example, as a key element.

(14) In accordance with embodiments of the present invention, the above-described measurement with N integration cycles is an integral part of a higher-order sequence comprising multiple such measurements. The higher-order sequence follows the above-described measurement of N integration cycles. The measurements of the higher-order sequence have different values of the number N of integration cycles to be carried out. Each of these measurements of the higher-order sequence have integration cycles carried out in the following manner, which becomes clear from the plot, shown in FIG. 2, of the voltage U.sub.CI(N) applied to integration capacitor 2 as a function of the number N of integration cycles.

(15) Initially, the number N of integration cycles to be carried out is set to a starting value N.sub.Start for the first measurement within the scope of the higher-order sequence. At the same time, a target or end value N.sub.End for the maximum number N of integration cycles to be carried out is set for the last measurement within the scope of the higher-order sequence. A voltage sum value U.sub.Total is initialized to the value zero. The number IZ of integration cycles carried out is initialized to the value zero.

(16) In addition, to initialize the measuring operation, shared circuit node 3, connected to first terminal 2′ of integration capacitor 2, and second terminal 2″ of integration capacitor 2 are connected to the ground potential GND. Thus, the voltage U.sub.CI across integration capacitor 2 to set to zero (e.g., “Reset Phase” shown in FIG. 1B).

(17) Subsequently, the integration process described above is carried out until the number IZ of integration cycles carried out, which upon each execution are increased by the value one, has reached the currently valid number N of integration cycles to be carried out. The voltage value U.sub.CI(N) at integration capacitor 2 is then measured by A/D converter 4 and is added to the currently valid voltage sum value U.sub.Total.

(18) The higher-order sequence then commences. The number N of integration cycles to be carried out is subsequently increased by a value n, and the steps described are repeated with the new number N. The number IZ of integration cycles carried out is not reset and the voltage at integration capacitor 2 is not cleared. As such, in effect, only n further integration cycles are carried out for the measurement step and the voltage at the integration capacitor 2 is correspondingly further increased.

(19) The increment value n is at least equal to one and is less than the difference N.sub.Diff=N.sub.End−N.sub.Start between the starting value N.sub.Start and the target or end value N.sub.End. To not obtain a quantity of measurements, with N integration cycles each, that is too small as the integral part of the higher-order sequence, the increment value n is generally selected to be much lower than N.sub.Diff. The increment value may either vary from measurement step to measurement step, or may assume a constant value of n=1, n=2, n=3, for example, or some other value. Repetition of the measurement step with the new number N takes place until the new number N exceeds the end value N.sub.End determined at the start.

(20) This is illustrated in FIG. 1B by way of example for n=2, with reference to the first two integration and detection phases. The first integration phase includes N.sub.Start integration cycles. The first detection phase subsequently takes place, in which the voltage U.sub.CI(N.sub.Start) at integration capacitor 2 at that moment is measured. In the second integration phase that follows, n=2 further integration cycles are executed. As such, the voltage U.sub.CI(N.sub.Start+2) at integration capacitor 2 now results from a total of N.sub.Start+2 integration cycles. The n=2 integration cycles that are executed are part of a measurement step and the resulting voltage U.sub.CI(N.sub.Start+2) at integration capacitor 2 is the voltage at the integration capacitor at the end of this measurement step. The measurement steps are continued in this way until the voltage U.sub.CI(N.sub.End) is ultimately measured as the last value.

(21) The voltage sum value U.sub.Total that has been summed up to this point in time from the respective measured voltages U.sub.CI(N), U.sub.CI(N.sub.Start+2), U.sub.CI(N.sub.Start+4), . . . U.sub.CI(N.sub.End) is then evaluated as the measurement result.

(22) Thus, as described, the individual measured voltage values (U.sub.CI(N), U.sub.CI(N.sub.Start+2), U.sub.CI(N.sub.Start+4), . . . U.sub.CI(N.sub.End)) are entered as summands in the voltage sum value U.sub.Total. Each of these voltage values has been determined by A/D converter 4, and therefore contains a quantization error, as explained above. The quantization proceeds linearly over the measuring range; i.e., the gradation heights of the voltage levels output by A/D converter 4 are the same in each case. In contrast, since the plot of the voltage U.sub.CI(N), present at integration capacitor 2, as a function of the number N of integration cycles is non-linear, as is apparent in FIG. 2, a statistical distribution of the quantization errors is obtained which, as a whole, results in at least partial compensation of same.

(23) While exemplary embodiments are described above, it is not intended that these embodiments describe all possible forms of the present invention. Rather, the words used in the specification are words of description rather than limitation, and it is understood that various changes may be made without departing from the spirit and scope of the present invention. Additionally, the features of various implementing embodiments may be combined to form further embodiments of the present invention.