Power Amplifier with Decreased RF Return Current Losses

Abstract

Example embodiments relate to power amplifiers with decreased RF return current losses. One embodiment includes a RF power amplifier package that includes a semiconductor die, an input lead, first bondwire connections, second bondwire connections, and a plurality of shields. The semiconductor die includes an RF power transistor that includes output bond pads, input bond pads, a plurality of input fingers, and a plurality of output fingers. Further, each shield of the plurality of shields is arranged in between a respective input finger of the plurality of input fingers and a respective output finger of the plurality of output fingers and extending along with said respective input finger and output finger. In addition, each shield of the plurality of shields is connected to a ground terminal of the RF power transistor. The input fingers, output fingers, and shields are formed using a metal layer stack of multiple metal layers.

Claims

1. A radio-frequency (RF) power amplifier package comprising: a semiconductor die comprising; an RF power transistor, such as a RF field-effect transistor, comprising: output bond pads, such as drain bond pads; input bond pads, such as gate bond pads; a plurality of input fingers, such as gate fingers, that are connected to the input bond pads; and a plurality of output fingers, such as drain fingers, that are connected to the output bond pads; an input lead arranged on an input side of the package and an output lead arranged on an output side of the package; first bondwire connections extending from the input bond pads towards the input side of the package and connecting, either directly or indirectly, the input bond pads to the input lead; second bondwire connections extending from the output bond pads towards the output side of the package and connecting, either directly or indirectly, the output bond pads to the output lead; and a plurality of shields, each shield of the plurality of shields being arranged in between a respective input finger of the plurality of input fingers and a respective output finger of the plurality of output fingers and extending along with said respective input finger and output finger, wherein each shield of the plurality of shields is connected to a ground terminal of the RF power transistor, wherein each input finger of the plurality of input fingers, each output finger of the plurality of output fingers, and each shield of the plurality of shields are formed using a metal layer stack of multiple metal layers of which upper metal layers have a greater thickness than lower metal layers, and wherein: each input finger of the plurality of input fingers physically extends for a larger part in a region in between the input side of the package and the input bond pads than in a region in between the input bond pads and the output side of the package, wherein each input finger of the plurality of input fingers physically extends for more than 70% in the region in between the input side of the package and the input bond pads, preferably more than 90%; and/or each output finger of the plurality of output fingers physically extends for a larger part in a region in between the output bond pads and the output side of the package than in a region in between the input side of the package and the output bond pads, wherein each output finger of the plurality of output fingers physically extends for more than 70% in the region in between the output bond pads and the output side of the package, preferably more than 90%.

2. The RF power amplifier package according to claim 1, wherein the input bond pads are grouped into an input bond bar, and wherein the output bond pads are grouped into an output bond bar.

3. The RF power amplifier package according to claim 2, wherein each output finger that is connected to the output bond bar corresponds to a respective output finger of the plurality of output fingers, and wherein each input finger that is connected to the input bond bar corresponds to a respective input finger of the plurality of input fingers.

4. The RF power amplifier package according to claim 2, wherein the output fingers extend underneath the input bond bar or the input fingers extend underneath the output bond bar.

5. The RF power amplifier package according to claim 1, wherein the output bond pads are arranged nearer to the edge of the semiconductor die that is closest to the input side of the package, wherein the RF power transistor preferably further comprises auxiliary output bond pads arranged on the semiconductor die and in between the output bond pads and the output side, wherein the second bondwire connections comprise a plurality of first output bondwires that extend between the output bond pads and the auxiliary output bond pads and a plurality of second output bondwires that extend from the auxiliary output bond pads towards the output lead, and wherein the auxiliary output bond pads are preferably grouped into an auxiliary output bond bar.

6. The RF power amplifier package according to claim 1, wherein the input bond pads are arranged nearer to the edge of the semiconductor die that is closest to the output side of the package, wherein the RF power transistor preferably further comprises auxiliary input bond pads arranged on the semiconductor die and in between the input bond pads and the input side, wherein the first bondwire connections comprise a plurality of first input bondwires that extend from the auxiliary input bond pads towards the input side and a plurality of second input bondwires that extend between the auxiliary input bond pads and the input bond pads, and wherein the auxiliary input bond pads are preferably grouped into an auxiliary input bond bar.

7. The RF power amplifier package according to claim 1, further comprising: a DC blocking capacitor having a first terminal and a second grounded terminal; and one or more resonance bondwires connected in between the output bond pads and the first terminal of the DC blocking capacitor, wherein the DC blocking capacitor essentially forms a short at an RF operating frequency of the RF power amplifier package, wherein an inductance of the one or more resonance bondwires is designed such that it resonates with an output capacitance of the RF power transistor at or close to the RF operating frequency, and wherein the DC blocking capacitor is preferably arranged on a separate semiconductor die in between the semiconductor die and the output lead or on the semiconductor die.

8. The RF power amplifier package according to claim 7, wherein the DC blocking capacitor is arranged on the semiconductor die, and wherein: the DC blocking capacitor is arranged nearer to edge of the semiconductor die that is closest to the input side of the package and wherein each output finger of the plurality of output fingers physically extends for a larger part in the region in between the input side of the package and the output bond pads than in the region in between the output bond pads and the output side of the package; or the DC blocking capacitor is arranged nearer to edge of the semiconductor die that is closest to the output side of the package and wherein each output finger of the plurality of output fingers physically extends for a larger part in a region in between the output bond pads and the output side of the package than in a region in between the input side of the package and the output bond pads.

9. The RF power amplifier package according to claim 1, wherein the first bondwire connections connect directly to the input lead.

10. The RF power amplifier package according to claim 6, further comprising an input matching network arranged in between the input lead and the semiconductor die, wherein the first bondwire connections comprise third input bondwires that extend between the input lead and the input matching network and fourth input bondwires that extend between the input matching network and the input bond pads or the auxiliary input bond pads, wherein the input matching network preferably comprises an input matching capacitor having a first terminal and a grounded second terminal, and wherein the third input bondwires and the fourth input bondwires are each connected to the first terminal of the input matching capacitor.

11. The RF power amplifier package according to claim 1, wherein the second bondwire connections connect directly to the output lead.

12. The RF power amplifier package according to claim 5, further comprising an output matching network arranged in between the output lead and the semiconductor die, wherein the second bondwire connections comprise fourth output bondwires that extend between the output lead and the output matching network and third output bondwires that extend between the output matching network and the output bond pads or the auxiliary output bond pads, wherein the output matching network preferably comprises an output matching capacitor having a first terminal and a grounded second terminal, and wherein the third output bondwires and the fourth output bondwires are each connected to the first terminal of the output matching capacitor.

13. (canceled)

14. The RF power amplifier package according to claim 1, wherein the RF power transistor comprises a RF power field-effect transistor (FET), and wherein the input of the RF power transistor corresponds to a gate of the RF power FET, the output of the RF power transistor to a drain of the RF power FET, and the ground terminal of the RF power transistor to a source of the RF power FET.

15. An electronic device comprising the RF power amplifier package according to claim 1.

16. The RF power amplifier package according to claim 7, further comprising a conductive substrate on which the semiconductor die is mounted, wherein the DC blocking capacitor is mounted on the conductive substrate, wherein the second terminal of the DC blocking capacitor is preferably connected to the conductive substrate, and wherein the ground terminal of the RF power transistor is preferably connected to the substrate via the conductive substrate of the semiconductor die.

17. The RF power amplifier package according to claim 10, further comprising a conductive substrate on which the semiconductor die is mounted, wherein the input matching capacitor is mounted on the conductive substrate, wherein the second terminal of the input capacitor is preferably connected to the conductive substrate, and wherein the ground terminal of the RF power transistor is preferably connected to the substrate via the conductive substrate of the semiconductor die.

18. The RF power amplifier package according to claim 12, further comprising a conductive substrate on which the semiconductor die is mounted, wherein the output matching capacitor is mounted on the conductive substrate, wherein the second terminal of the output capacitor is preferably connected to the conductive substrate, and wherein the ground terminal of the RF power transistor is preferably connected to the substrate via the conductive substrate of the semiconductor die.

Description

[0029] Next, the invention will be described in more detail referring to the appended drawings, wherein:

[0030] FIG. 1 illustrates a cross section of a known radiofrequency power amplifier package;

[0031] FIG. 2 illustrates an equivalent circuit of the radiofrequency power amplifier package of FIG. 1;

[0032] FIG. 3 illustrates a top view of a semiconductor die comprising a known RF power transistor that can be used in the topology in FIG. 1;

[0033] FIG. 4 illustrates a schematic cross section of the semiconductor die along line A shown in FIG. 3;

[0034] FIG. 5 illustrates a general aspect of the invention;

[0035] FIGS. 6A-6I illustrate various embodiments of the invention; and

[0036] FIG. 6J illustrates an equivalent circuit corresponding to the embodiment of FIG. 6I.

[0037] Hereinafter, when bondwires are shown, it should be noted that not all of the bondwires may be shown to improve the clarity of the figures. For example, instead of a large plurality of output bondwires only two or three will be shown. The same holds for the number of gate fingers and drain fingers that will be depicted.

[0038] FIG. 1 illustrates a known RF power amplifier package. FIG. 2 illustrates an electric circuit corresponding to the package of FIG. 1. As shown, the RF package comprises a semiconductor die 5 on which an RF power transistor Q1 is arranged. Here, transistor Q1 can be a Si based LDMOS transistor or a GaN field effect transistor that is suitable for generating high power levels (>5 W) at frequencies above 500 MHz.

[0039] Semiconductor die 5 is mounted on a conductive substrate 9. The RF package further comprises an input lead 10 and an output lead 11 which are each separated from substrate 9 using a spacer element 8 for example in the form of a ceramic ring.

[0040] Input lead 10 is connected to a matching network formed by bondwire(s) 1, bondwire(s) 2, and a capacitor 6 to ground. Bondwire(s) 2 are connected to an input, e.g. gate, of transistor Q1 and bondwire(s) 1 are connected to input lead 10. Furthermore, bondwires(s) 1 correspond to inductance L1, bondwire(s) 2 to inductance L2, and capacitor 6 to capacitor C1 in FIG. 2. Capacitor 6 may be in the form of a passive semiconductor die comprising one terminal to which bondwire(s) 1, 2 are connected and which is arranged at an upper surface of the die. Capacitor 6 further comprises another terminal at the backside of the die contacting the conductive substrate 9.

[0041] Transistor Q1 comprises an output capacitance Cds as shown in FIG. 2. As this capacitance may become large for high power transistors, it may have a detrimental influence on RF performance. To mitigate this problem it is known to arrange an inductance parallel to Cds, such as inductor L3 in FIG. 2. This inductance is generally configured to resonate with Cds at or close to an operational frequency of the amplifier to effectively present a high impedance at the output of Q1. A DC blocking capacitor, such as capacitor C2, is arranged in series with L3 to block a DC path to ground.

[0042] The abovementioned functionality is implemented in the RF package of FIG. 1. For example, inductance L3 is formed using bondwire(s) 3 and capacitor C2 by a passive semiconductor die 7 that is similar to passive semiconductor die 6. Here, bondwires(s) 3 extend from an output of Q1, e.g. drain, to an upper terminal of C2. The other terminal of C2 may be arranged on a backside of passive semiconductor die 6. The output of Q1 is further connected to output lead 11 using bondwire(s) 4, which are represented by inductor L4 in FIG. 2.

[0043] FIG. 3 schematically illustrates a top view of semiconductor die 5. Here, a gate bar 50 is formed to which bondwire(s) 2 are bonded (not shown). Similarly, at the output side, a drain bar 52 is formed to which bondwire(s) 3, 4 are bonded (not shown). Gate fingers 51 extend from gate bar 50 towards an output side of the package. Here, the output side of the package corresponds to the side of the package where output lead 11 is arranged. Drain fingers 53 extend from drain bar 52 towards an input side of the package, wherein the input side of the package corresponds to the side of the package where input lead 10 is arranged.

[0044] FIG. 4 schematically illustrates a cross section of semiconductor die 5 in a plane perpendicular to gate fingers 51. In FIG. 4, the position of the layers in semiconductor die 5 making up transistor Q1 is indicated by dotted rectangle 54. Furthermore, it is shown that gate fingers 51 and drain fingers 53 are each formed using a layer stack of one or more metals. Furthermore, FIG. 4 illustrates that the actual drain and gate connections on the semiconductor die are connected, using vias 24, 24A, to the various layers 20-23 of the metal stack. In this metal stack, the upper metal layers are considerably thicker than the lower metal layers.

[0045] FIG. 4 illustrates that gate finger G is formed using metal layers 21-23. In each layer, a finger such as illustrated in FIG. 3 may extend along semiconductor die 5. Alternatively, a finger may only extend in the upper metal layers. A similar arrangement holds for the drain finger D that may also comprise one or more fingers at specific metal layers.

[0046] FIG. 4 further illustrates that one or more shields Sh are arranged in between the gate and drain fingers. These shields are grounded. More in particular, FIG. 4 illustrates how shield Sh is connected via a track on metal layer 20 and via 24A to the source of the transistor. Furthermore, the source of transistor Q1 is electrically connected via a highly doped region (‘plug’, not shown) in semiconductor die 5 to conductive substrate 9.

[0047] Any current that leaves or enters a gate or drain terminal of transistor Q1 is associated with a return current. These return currents typically flow for a large part through shields Sh.

[0048] The Applicant has found that when using the topology of FIG. 3, a significant amount of the RF return current is not flowing through the upper metal layers of shield Sh. Instead, the return current flows through the lower metal layers. Due to the fact that these lower layers are thinner than the upper metal layers, losses may be higher.

[0049] A general solution of this problem in accordance with the present invention is shown in FIG. 5, which presents a partial top view of semiconductor die 100. Compared with the topology shown in FIG. 3, the positions at which the bondwires are connected to the semiconductor die has changed. More in particular, gate finger 2 extends over a length G1 from bondpad 150 towards the input side (left-hand side in FIG. 5) and extends over a length G2 from bondpad 150 towards the output side (right-hand side in FIG. 5). Similarly, drain finger 4 extends over a length D1 from bondpad 152 towards the input side and extends over a length D2 from bondpad 152 towards the output side.

[0050] According to the invention, at least one of the following conditions holds for the gate fingers and drain fingers: G1>G2 and D2>D1. The Applicant has found that when D2>D1, a larger part of the return current associated with the drain current flows through the upper metal layers of Shield Sh, thereby lowering losses associated with this return current when compared with the topology of FIG. 3. The Applicant further found that when G1>G2, a larger part of the return current associated with the gate current flows through the upper metal layers of Shield Sh, thereby lowering losses associated with this return current when compared with the topology of FIG. 3.

[0051] FIGS. 6A-6I illustrate various examples of reducing the losses associated with the drain and/or gate currents. In FIG. 6A, an example is presented wherein the drain bondpads are grouped in a drain bondbar 152 which is positioned in correspondence with FIG. 5, whereas the gate bondpads are grouped in a gate bondbar 150 which is positioned in correspondence with the prior art topology of FIG. 3.

[0052] As can be seen in FIG. 6A, gate fingers 151 extend underneath drain bondbar 152. This is indicated by the dashed portion. Such routing is made possible by using the multi-layer metal stack as discussed above.

[0053] In FIG. 6B, an example is presented wherein the gate bondpads are grouped in a gate bondbar 150 which is positioned in correspondence with FIG. 5, whereas the drain bondpads are grouped in a drain bondbar 152 which is positioned in correspondence with the prior art topology of FIG. 3. As can be seen in FIG. 6B, drain fingers 153 extend underneath gate bondbar 150.

[0054] It should be noted that when the drain bondbar 152 and gate bondbar 150 are arranged close to each other, such as illustrated in FIGS. 6A and 6B, it may equally be possible to reverse the order of the bondbars. In this way, intentional coupling between bondwires 2, 4 may or may not be generated. An example thereof is indicated in FIG. 6C. In this figure, gate bondbar 150 is arranged in between drain bondbar 152 and the output side of the package.

[0055] FIG. 6D illustrates an embodiment corresponding to FIG. 5. In this embodiment, there may be a relatively large electromagnetic coupling between bondwires 2, 4, which may be advantageously for tuning the amplifier for stability.

[0056] Depending on the placement of the bondbars, the length of the connecting bondwires 2, 4 may become large. It may then be advantageous to arrange auxiliary bondbars or bondpads on the semiconductor die. An example thereof is present in FIG. 6E, where an auxiliary drain bondbar 160 is used to divide bondwire 4 in a primary part 4′ and a secondary part 4″. The arrangement of bondbars 150, 152 in this embodiment is similar to the arrangement shown in FIG. 6D.

[0057] The embodiments shown in FIGS. 6F-6H illustrate embodiments, wherein an inductor is used to resonate with the output capacitance of the transistor, similar to the circuit shown in FIG. 2. In FIG. 6F, a separate semiconductor die 170 is shown on which a DC blocking capacitor C2 is integrated. Other means of realizing DC blocking capacitor C2 are not excluded. Bondwire(s) 171 extend between drain bondbar 152 and one terminal of capacitor C2. Similar to FIG. 1, the other terminal of C2 is arranged on the backside of die 170.

[0058] Instead of using a separate semiconductor die 170, C2 may be integrated in semiconductor die 100 itself. This is illustrated in FIG. 6G. Another example of such integration is shown in FIG. 6H, wherein C2 is positioned on an opposite side of the semiconductor die 100 as drain bondbar 152.

[0059] FIG. 6I illustrates an input matching network and an output matching network connected to semiconductor die 100. An equivalent circuit is shown in FIG. 6J. Each matching network comprises a capacitor C1, C3 to ground realized in a semiconductor die 180, 181, respectively, and two inductors in series. For example, an input matching network is formed by an inductor L1 formed by bondwires 2′, the capacitor to ground C1 formed on semiconductor die 180, and an inductor L2 formed by bondwires 2. Similarly, an output matching network is formed by an inductor L4_1 formed by bondwires 4, the capacitor to ground C3 formed on semiconductor die 181, and an inductor L4_2 formed by bondwires 172. Furthermore, in FIG. 6I, bondwires 171 correspond to inductor L3.

[0060] Although the FIG. 6I embodiment discloses that gate bondbar 150 is arranged close to the output side than to the input side, the skilled person will readily understand that the topology of FIG. 6I can be combined with any of the embodiments 6A-6H.

[0061] In the description above, the present invention has been explained using detailed embodiments thereof. It should however be noted that the present invention is not limited to these embodiments. Modifications to the embodiments can be made without departing from the scope of the invention, which is defined by the appended claims and their equivalents.