WAFER LEVEL PACKAGE AND METHOD OF MANUFACTURE

Abstract

A wafer level package comprises a functional wafer with a first surface, device structures connected to device pads arranged on the first surface. A cap wafer, having an inner and an outer surface, is bonded with the inner surface to the first surface of the functional wafer. A frame structure surrounding the device structures is arranged between functional wafer and cap wafer. Connection posts are connecting the device pads on the first surface to inner cap pads on the inner surface. Electrically conducting vias are guided through the cap wafer connecting inner cap pads on the inner surface and package pads on the outer surface of the cap wafer.

Claims

1. A wafer level package, comprising a functional wafer with a first surface device structures connected to device pads arranged on the first surface a cap wafer, having an inner and an outer surface, bonded with the inner surface to the first surface of the functional wafer a frame structure surrounding the device structures and being arranged between functional wafer and cap wafer connection posts connecting the device pads on the first surface to inner cap pads on the inner surface electrically conducting vias guided through the cap wafer connecting inner cap pads on the inner surface and package pads on the outer surface of the cap wafer.

2. The wafer level package of claim 1, wherein the functional wafer is a substrate wafer with a thin film functional layer on the first surface wherein the cap wafer comprises the same material like the substrate wafer wherein the thickness of the cap wafer is smaller than the thickness of the functional wafer.

3. The wafer level package of claim 1, wherein the functional wafer is a silicon wafer with a thin film piezoelectric layer applied on the first surface thereof wherein the device structures are electrodes adapted for exciting acoustic waves in the piezoelectric layer.

4. The wafer level package of claim 1, comprising a bridging line on the inner surface connecting two connection posts, and a conductor line on the first surface being flanked without contact by the two connection posts an air gap between bridging line and conductor line such that the bridging line and the conductor line are forming a contactless line crossing.

5. The wafer level package of claim 1, wherein the vias are filled with tungsten wherein one of inner cap pads or package pads on the inner surface or on the outer surface of the cap wafer comprise a structured tungsten layer.

6. A method of manufacturing the wafer level package of claim 1, comprising: a) providing a cap wafer b) forming a hole in the cap wafer to a depth dv c) filling up the hole with a metal to form a prestage of a via d) structuring of metal on surface if requested, else remove metal from wafer surface e) providing a structured metallization layer in contact with the hole filling metal to form first contact pads f) bonding the cap wafer with the contact pads to a second wafer g) grinding the cap wafer from the surface opposite to the contact pads and exposing the metal filled holes from the back thereby forming a through going via h) forming second contact pads on the cap wafer in contact with the exposed vias wherein according to a first variant step d) comprises applying a first bond metal onto the first contact pads, and wherein the second wafer used in step e) is a device wafer comprising a carrier wafer provided with a thin functional layer thereon, on which device structures and device pads covered with a second bond metal are arranged, wherein bonding in step e) is done by bonding the first contact pads covered with the first bond metal to the device pads covered with the second bond metal on the functional wafer.

7. The method of claim 6, wherein according to a second variant the method steps a) to g) are performed with the following deviating stipulations: in step f) a temporary carrier wafer is used as second wafer after step h) steps i) to l) are performed: i) providing a first bond metal to the first contact pads on the cap wafer j) providing a device wafer comprising a carrier wafer with a thin functional layer thereon, on which device structures and device pads covered with a second bond metal are arranged, k) performing a wafer-bond process by bonding the second contact pads to the device pads l) cleavage of the temporary carrier wafer from the cap wafer.

8. The method of claim 6, comprising a step b1) performed after step b) and a step g1) performed after step g) b1) forming a first passivation layer at least on the surface of the cap wafer with the hole g1) forming a second passivation layer at least on the surface of the cap wafer after exposing the via from the back.

9. The method of claim 6, wherein step c) comprises depositing a layer of tungsten to the entire surface of the cap wafer as a hole filling material and wherein step d) comprises structuring of the tungsten layer to form the first contact pads.

10. The method of claim 9, comprising deposition of a metal layer onto the first contact pads by electro-less plating or by electroplating.

11. The method of claim 6, wherein step b) comprises performing a lithography for defining the holes and dicing streets as well, the dicing streets being arranged between sections of the cap wafer that assigned to different devices wherein the holes and the dicing streets are produced by plasma etching wherein grinding in step g) comprises exposing the dicing streets together with the metal filled holes.

12. The method of claim 6, wherein step b) comprises defining and etching a ring-shaped trench concentric to the hole wherein step c) comprises filling the ring-shaped trench and the hole in the same step thereby forming a shield structure for the preformed via.

Description

[0046] The drawings are schematically only and not drawn to scale. Some elements may be depicted enlarged for better visibility. Others may depicted with reduced size.

[0047] FIGS. 1 to 6 show different stages of a method of manufacturing the wafer level package according to the first embodiment.

[0048] FIG. 7 shows a wafer level package according to the first embodiment.

[0049] FIGS. 8 to 12 show different stages of a method of manufacturing the wafer level package according to the second embodiment.

[0050] FIG. 13 shows a wafer level package according to the second embodiment.

[0051] A first embodiment for manufacturing the wafer level package is explained with reference to FIGS. 1 to 5 showing different stages during the manufacturing process of this embodiment. A cap wafer CW consists of a material like Si that is suitable for current wafer processing technology. On a surface of this cap wafer assigned to the later inner surface holes HL and trenches TR are etched in the same step. The holes are corresponding to later vias. The trenches are corresponding to the later dicing streets along which the later packages are singulated. Hence, the trenches are structuring the inner surface according to a grid defining and separating the single chip areas there between.

[0052] Holes and trenches are produced with a proper dry etching technique like a plasma etch thereby using a lithographic resist mask. Etching is performed until the depth of the holes HL exceeds the depth of the planned vias without extending through the whole cap wafer CW. A useful depth is between 20 and 100 μm. Similarly, the trenches must not go through the whole thickness of the cap wafer CW that the cap wafer maintains sufficient stability to be further processed on a wafer level. When using the same opening width for etching holes HL and trenches TR the same depth is achieved. With a higher width of the opening the etching process is faster and results in deeper holes.

[0053] In a next step the surface is passivated preferably by a step of thermal oxidation to produce a thin isolating oxide layer on the free surfaces of the wafer. FIG. 1 shows the so produced cap wafer at this stage.

[0054] In the next step a hole filling metal is deposited onto the inner surface of the cap wafer CW to fill the hole HL. Tungsten is preferred metal as it can be deposited in an isotropic and conformal manner in holes with high aspect ratios. But any other method for filling the holes is also useful. The hole filling metal can be chosen in dependence of the diameter of the hole opening. A smaller hole diameter requires higher hole filling properties and hence restricts the choice of suitable metals.

[0055] The hole filling metal is deposited to the entire surface and can thus be used for forming a structured metallization.

[0056] Optionally a further lithographic process including structuring the deposited metal can follow to form further wirings or passive elements like a planar coil or a redistribution for example. Finally the resist for the lithography has to be stripped.

[0057] If necessary a step of chemical mechanical polishing CMP can be provided in advance to provide a plane surface on the structured metallization with low roughness.

[0058] Otherwise the metallization can be etched back to the hole surface.

[0059] In a further metal layer a frame structure FR surrounding the area that is assigned to be enclosed by the later package cavity is formed as part of a second structured metallization.

[0060] FIG. 2 shows the cap wafer CW with filled holes HL and a structured layer SL of the hole filling metal and/or of the further metal layer on the inner surface. The trenches are kept or etched free from the metal.

[0061] In the next step a metallization for forming contact pads is deposited onto those locations of the existing metallization where contact to the later functional wafer is desired or necessary. For doing this a resist mask is formed in a lithographic step. The metal for the contact pads can be deposited according to the desired later bonding step. In case the existing metal structure comprises W preferably a Sn layer is deposited by evaporation followed by a lift-off process of the resist mask including part of the Sn that has been deposited on the resist mask. But any other metal and deposition technique can be used alternatively. FIG. 3 shows the cap wafer at this step with the so produced cap pads (contact pads) CP and the surrounding frame structure FR.

[0062] FIG. 4 shows a respective cross section of a functional wafer FW that is provided in parallel. The functional wafer FW preferably comprises the same bulk material like the cap wafer where a Si wafer is preferred. On top of the first surface of the functional wafer FW is a layer of a functional material like a thin piezoelectric layer PL having a thickness of about 500 nm to 10 μm.

[0063] At least on top of the piezoelectric device structures DS are formed comprising electrode structures and/or transducers of the electric device that is a SAW device or a BAW device. In the latter case the electrode comprises a bottom electrode and a top electrode sandwiching the piezoelectric layer PL. For a BAW device of the SMR type (solidly mounted resonator) a Bragg mirror is arranged below the sandwich.

[0064] The device structures DS further comprise device pads DP for electric contact of the electric device on the functional wafer to the cap wafer CW. Part of the device pads that are not required for electric contact to the external can be used for contact to a wiring structure/cap redistribution layer on the inner surface of the cap wafer CW. Using this wiring structure a contact-free line crossing of conductor lines can be achieved. This means that a line on the first surface of the functional wafer FW can be guided by means of device pad DP to a higher level that is on the inner surface to cross another line on the lower level that is on the first surface. By means of a second device pad return to the lower level is achieved after having crossed the second line.

[0065] Besides the device pads DP for electric coupling mere mechanical pads and a frame structure FR.sub.F are formed on the first surface and are made preferably from the same metallization like the device pads. Frame and optionally present mechanically supporting pads or posts (not shown in the figure) are adapted to be bonded to according metal structures on the inner surface of the cap wafer.

[0066] To make the metal structures on the functional wafer ready for the wafer bonding process a second bonding metal is applied to these structures in a lithographic step. The second bond metal may comprise Au that can be applied by evaporation onto the masked first surface. But any other metal that is able to for the bonding step to the first bonding metal on the inner surface of the cap wafer can be used too. Finally the evaporation mask can be stripped in a lift-off process.

[0067] The design of the second layer may overlap the first layer or not in dependence of achieving a hermetic package.

[0068] FIG. 5 shows the cap wafer CW and the functional wafer FW in a mutual arrangement where first surface and inner surface are facing each other such that metalizations like device pads DP, inner cap pads CP frame structures FR and optional mechanically supporting posts are opposite each other.

[0069] In a wafer bonding process mutually assigned structures are bonded to each other in the same step. After bonding the two wafers together the so-formed package arrangement has enough mechanical stability that the thickness of the cap wafer CW can be reduced. The resulting thickness is lower than the depth of holes and trench such that metal filled holes HL and trenches are exposed and opened at the outwardly facing surface of the cap wafer. Grinding of the cap wafer from the top surface is a preferred method for achieving a reduced thickness. By opening of the trench TR the cap wafer CW is singulated into a multitude of individual cap wafer sections each being assigned to a separate package for a separate device.

[0070] In a next step the exposed Si surface has to be passivated again, e.g. by plasma deposition or sputtering of an insulating material like SiO.sub.2. FIG. 6 shows a cross section of the resulting structure. The both wafers are connected by the frame structure, terminal posts TP for electrical connection and redistribution posts RP for making contact to the mentioned line crossing LC. The terminal posts TP, only one of a multitude of terminal posts is shown, are connecting device pads to the metal-filled via CV directly or by means of pad or conductor line on the inner surface. The bonded frame structures on inner and first surface are forming a frame surrounding and enclosing the device structures that a closed cavity is formed between frame, cap wafer and functional wafer. The frame needs no electric connection to an electric terminal but can optionally be grounded.

[0071] Further proceeding with the package can be done according to standard processes to achieve the ready manufactured package device. Such steps comprise one or more steps of [0072] forming external package pads on the outer surface of the cap wafer section [0073] singulating the packages by dicing through the functional wafer [0074] applying a redistribution layer as a multilayer structure [0075] forming a fan-out structure to enhance the distance between external package pads [0076] applying further isolating or passivating layers [0077] applying a molding to improve mechanical stability etc.

[0078] External package pads on the outer surface of the cap wafer section can be formed by different processes. A first of them comprises [0079] forming a seed layer e.g. by sputtering a seed metal [0080] forming a lithographic resist mask [0081] enforcing the seed layer by electroplating forming e.g. a layer of CuNiAu or Cu alone [0082] stripping the resist mask [0083] removing the seed layer in the areas exposed after the resist stripping by etching

[0084] A second process comprises [0085] forming a seed layer e.g. by sputtering a seed metal e.g. Ti/Al [0086] forming a lithographic etch mask [0087] etching the seed layer in the area not covered by the etch mask [0088] stripping the etch mask [0089] enforcing the exposed seed layer areas e.g. by E-less plating e.g. of Ni/Au

[0090] A third process comprises [0091] forming a lithographic mask [0092] evaporating a seed metal like Ti/Al for example [0093] stripping the mask in a lift-off process [0094] enforcing the exposed seed layer areas e.g. by E-less plating e.g. of Ni/Au

[0095] FIG. 7 shows a singulated package device after forming external package pads PP which can function as a UBM for bonding or soldering the package device to a PCB or another circuit environment.

[0096] After the process of singulating the individual package devices the fan-out structure can be produced as a multilayer structure. This and other optional processes that are performed after singulation can nevertheless be performed on a wafer-level when fixing the singulated devices in a matrix of e.g. a temporary carrier material like an adhesive foil for example.

[0097] A second embodiment for manufacturing the wafer level package is explained with reference to FIGS. 7 to 13 showing different stages during the manufacturing process of this embodiment.

[0098] FIG. 8 corresponds to FIG. 1 and shows the same or a similar cap wafer provide with holes HL for the later vias, trenches TR and a final passivation layer PL formed e.g. by thermal oxidation of the surface of the silicon wafer CW.

[0099] In the next step a hole filling metal like tungsten W is deposited on the entire surface S.sub.O until the hole HL is completely filled. An etch mask is lithographical formed above the W layer and the exposed areas of the W layer are etched. FIG. 9 shows the arrangement after stripping the etch mask.

[0100] The remaining and now exposed W layer areas are reinforced by plating, e.g. by E-less deposition of NiAu. According to this second embodiment the produced metal pads will later function as external package pads PP.

[0101] The cap wafer is now bonded to a temporary carrier wafer TW. This may be any carrier with an “adhesive” or another bonding layer BL on top. In an embodiment the bonding layer BL may be a thermos-release layer. FIG. 10 shows the arrangement just before bonding the cap wafer CW with the package pads PP to the bonding layer BL of the temporary carrier wafer TW.

[0102] After bonding the cap wafer CW to the temporary carrier wafer TW the so-formed arrangement has enough mechanical stability that the thickness of the cap wafer CW can be reduced. The resulting thickness is lower than the depth of holes and trench such that metal filled holes HL and trenches are exposed and opened at the outwardly facing surface of the cap wafer. Grinding of the cap wafer from the top surface is a preferred method for achieving a reduced thickness. By opening of the trench TR the cap wafer CW is singulated into a multitude of individual cap wafer sections each being assigned to a separate package for a separate device. A passivation layer PL is formed e.g. by plasma deposition or sputtering of an insulating material like SiO.sub.2 on the silicon cap wafer CW. FIG. 11 shows the arrangement at this step.

[0103] In the next step the later inner surface of the cap wafer that is the surface facing away from temporary carrier wafer TW is provided with inner cap pads CP. According to an embodiment but not restricted to this can be done by forming a lithographic mask and depositing a metal layer on the inner surface S.sub.I. e.g. by evaporation of Sn.

[0104] In the next step the so-formed arrangement is permanently bonded with the inner cap pads to the according metal structures of a functional wafer FW like that exemplarily shown in FIG. 4. FIG. 12 shows the arrangement at this step.

[0105] In a final step the temporary carrier wafer is released e.g. by softening the bonding layer BL in a thermal step or by decomposing or transforming the thermal release layer. FIG. 13 shows the arrangement at this step.

[0106] Singulation of individual package devices e.g. by dicing can follow. Further optional packaging steps can complete the package which are the same as already explained with reference to the first embodiment.

LIST OF USED TERMS AND REFERENCE SYMBOLS

[0107] CW cap wafer (second wafer) [0108] FW functional wafer (first wafer) [0109] TW temporary carrier wafer [0110] DS device structures [0111] PL thin film piezoelectric layer [0112] DP device pads [0113] S.sub.I inner surface of cap wafer [0114] CP inner cap pads [0115] CV via (through cap wafer) wafer level package [0116] PP package pads, comprising [0117] UBM under bump metallization cap redistribution layer [0118] LC line crossing connection posts, comprising [0119] TP terminal post [0120] RP redistribution post [0121] BM2 second bond metal (on device pads) [0122] BM1 first bond metal (on inner cap pads) [0123] PL passivation layer [0124] HL hole [0125] HM hole filling metal [0126] FR frame structure [0127] TR trench (=dicing street) [0128] SL structured layer of hole filling metal on inner surface [0129] CL conductor line on inner surface S.sub.I [0130] S.sub.O outer surface of CW [0131] BL bonding layer