METHOD FOR FABRICATING GERMANIUM/SILICON ON INSULATOR IN RADIO FREQUENCY SPUTTER SYSTEM

Abstract

Embodiments herein disclose a method providing deposition of Gadolinium Oxide (Gd.sub.2O.sub.3) on a semiconductor substrate. The method comprises of selecting, in an RF-sputter system, a predefined substrate and depositing, in an Ar-plasma struck, the Gd.sub.2O.sub.3, over the predefined substrate to obtain a layer of the Gd.sub.2O.sub.3 over the predefined substrate. The Gd.sub.2O.sub.3 is grown epitaxially over the predefined substrate. The method further provides performing, annealing, of the layer of the Gd.sub.2O.sub.3 over the predefined substrate at a predefined temperature for a predefined time and obtaining, a layer of the Gd.sub.2O.sub.3, over the predefined substrate. Embodiment also provides a method for fabricating Semiconductor on Insulator Substrate (SIS).

Claims

1. A method providing deposition of Gadolinium Oxide (Gd.sub.2O.sub.3) on a semiconductor substrate, the method comprising: selecting, in a Radio Frequency (RF)-sputter system, a predefined substrate; depositing, in an Ar-plasma struck, the Gd.sub.2O.sub.3, over the predefined substrate to obtain a layer of the Gd.sub.2O.sub.3 over the predefined substrate, wherein the Gd.sub.2O.sub.3 is grown epitaxially over the predefined substrate; performing, an anneal, of the layer of the Gd.sub.2O.sub.3 over the predefined substrate, at a predefined temperature for a predefined time; and obtaining, a resultant layer of the Gd.sub.2O.sub.3, over the predefined substrate.

2. The method as claimed in claim 1, wherein the predefined substrate comprises a Silicon (Si) or Germanium (Ge) substrate.

3. The method as claimed in claim 1, wherein the deposition is performed at a predefined pressure in a range of 1×10.sup.−7 torr to 1×10.sup.−6 torr, wherein the predefined pressure is performed in a process chamber in the RF-sputter system.

4. The method as claimed in claim 1, wherein depositing is performed one or more temperatures in a range of 600° C. to 800° C.

5. The method as claimed in claim 1, wherein the predefined substrate is selected in one or more orientations, wherein the one or more orientation comprises one of Si<111> or Si<100>.

6. The method as claimed in claim 1, wherein predefined temperature comprises in a range of 550° C. to 650° C.

7. The method as claimed in claim 1, wherein the predefined time comprises in a range of 10 minutes to 30 minutes.

8. A method for fabricating Semiconductor on Insulator Substrate (SIS), the method comprising: growing, an isolation layer of a Rare Earth (RE) oxide over a preselected substrate for obtaining a single crystalline seed layer at a predefined temperature, wherein the growing is performed in a Physical Vapor Deposition (PVD) system, and wherein the preselected substrate is a base layer; depositing, an amorphous semiconductor layer over the seed layer at a predefined temperature; forming, a capping layer of the RE oxide over the deposited amorphous semiconductor layer over the seed layer, at a predefined capping temperature; removing, the RE layer grown over the preselected substrate by using an etching process for obtaining the SIS.

9. The method as claimed in claim 8, wherein the preselected substrate comprises one of a Silicon (Si), Germanium (Ge), Tin (Sn), or alloys of the preselected substrate.

10. The method as claimed in claim 8, wherein the rare earth oxide comprises one of a Gd.sub.2O.sub.3, Pr.sub.2O.sub.3, Yr.sub.2O.sub.3, Sm.sub.2O.sub.3, Dy.sub.2O.sub.3.

11. The method as claimed in claim 8, wherein the PVD system comprises one of an RF-Magnetron Sputter system, evaporators or CVD system.

12. The method as claimed in claim 8, wherein the predefined temperature for depositing the amorphous semiconductor layer over the seed layer.

13. The method as claimed in claim 8, wherein the predefined temperature for growing comprises in a range of 500° C. to 800° C.

14. The method as claimed in claim 8, wherein the etching process comprises at least one of a dry etching process and a wet etching process.

15. The method as claimed in claim 8, wherein the predefined capping temperature comprises in a range of 500° C. to 800° C.

16. The method as claimed in claim 8, comprising: growing, after the etching, an epi-semiconductor layer over the SIS.

Description

BRIEF DESCRIPTION OF FIGURES

[0012] This method is illustrated in the accompanying drawings, throughout which like reference letters indicate corresponding parts in the various figures. The embodiments herein will be better understood from the following description with reference to the drawings, in which:

[0013] FIG. 1(a) shows flow chart for a method providing deposition of Gadolinium Oxide (Gd.sub.2O.sub.3) on a semiconductor substrate, according to embodiments as disclosed herein;

[0014] FIG. 1(b) shows a flow chart for a method fabricating Semiconductor on Insulator Substrate (SIS), according to embodiments as disclosed herein;

[0015] FIG. 2(a) shows Small angle range ω-2θ scan for Gd2O3 deposited on Si (111) at (i). 650° C., (ii). 700° C., (iii). 750° C. and (iv), on Si (100) at 700° C., according to embodiments as disclosed herein;

[0016] FIG. 2(b) shows each of before and after Forming Gas Annealing (FGA) ω-2θ comparison, according to embodiments as disclosed herein;

[0017] FIG. 2(c) shows a perfect fit of X-ray Reflectometry (XRR) against calculated data showing accuracy of thickness, according to embodiments as disclosed herein;

[0018] FIG. 3 shows Wide angle range ω-2θ scan of epi-Gd.sub.2O.sub.3/Si (111) stack deposited, according to embodiments as disclosed herein;

[0019] FIG. 4(a) illustrates Transmission Electron Microscopic (TEM) image of stack on 50 nm scale to show uniformity of epi-Gd.sub.2O.sub.3 layer, according to embodiments as disclosed herein;

[0020] FIG. 4(b) shows High-resolution TEM image of Gd.sub.2O.sub.3/Si stack at 2 nm scale, showing ordered stacking of the dielectric, according to embodiments as disclosed herein;

[0021] FIG. 5(a) illustrates Atomic Force Microscopic (AFM) image describing the surface roughness of the epi-Gd2O3 layer, according to embodiments as disclosed herein;

[0022] FIG. 5(b) shows schematic of the Metal Oxide Semiconductor Capacitance (MOSCAP) structure fabricated, according to embodiments as disclosed herein;

[0023] FIG. 5(c) shows fabrication process flow used to deposit epi-Gd.sub.2O.sub.3 on Si (111), according to embodiments as disclosed herein

[0024] FIG. 6(a) illustrates CV without FGA, according to embodiments as disclosed herein;

[0025] FIG. 6(b) shows CV with FGA, according to embodiments as disclosed herein;

[0026] FIG. 6(c) illustrates extracted D.sub.it for each of the CV without FGA and CV with FGA case, according to embodiments as disclosed herein;

[0027] FIG. 6(d) shows absolute current density profile for without-FGA MOSCAP, according to embodiments as disclosed herein;

[0028] FIG. 7 illustrates schematics of process flow involved in growing the Gd.sub.2O.sub.3—Ge—Gd.sub.2O.sub.3 hetero-structure on Si(111) substrate, according to embodiments as disclosed herein;

[0029] FIG. 8(a) illustrates the X-ray diffraction pattern for the Gd.sub.2O.sub.3—Ge—Gd.sub.2O.sub.3 hetero-structure deposited using solid phase epitaxy (SPE) in RF magnetron sputter chamber over Si(111) substrate for a symmetric ω-2θ scan on wide angle range for Gd.sub.2O.sub.3—Ge—Gd.sub.2O.sub.3 hetero-structure, showing Si peak, according to embodiments as disclosed herein;

[0030] FIG. 8(b) shows the X-ray diffraction pattern for the Gd.sub.2O.sub.3—Ge—Gd.sub.2O.sub.3 hetero-structure deposited using solid phase epitaxy (SPE) in RF magnetron sputter chamber over Si(111) substrate for a small angle range symmetric ω-2θ scan, where, the presence of Ge(111) peak at an angle 2θ=27.3° is highlighted in the inset, according to embodiments as disclosed herein;

[0031] FIG. 8(c) shows the X-ray diffraction pattern for the Gd.sub.2O.sub.3—Ge—Gd.sub.2O.sub.3 hetero-structure deposited using solid phase epitaxy (SPE) in RF magnetron sputter chamber over Si(111) substrate for a small angle range ω-2θ scan of the hetero-structure done with monochromator while aligning the sample with respect to the Ge(111) Bragg's angle (20=27.3°) by adjusting the χ to highlight the Ge(111) peak, according to embodiments as disclosed herein;

[0032] FIG. 9(a) illustrates a φ scan done for Ge(111) plane by fixing 2θ=27.3.sup.i and the χ=70.5°, according to embodiments as disclosed herein;

[0033] FIG. 9(b) shows a pole figure measurement done to probe Ge(111) crystal plane family by fixing 20=27.3° ′ according to embodiments as disclosed herein;

[0034] FIG. 9(c) shows an ω-2θ scan done by fixing φ=50° and χ=70.5°, according to embodiments as disclosed herein;

[0035] FIG. 10(a) illustrates a High-Resolution Transmission Electron Microscopy (HRTEM) image reflecting uniform layer of Ge crystals on Gd.sub.2O.sub.3 layer captured at Si—Gd.sub.2O.sub.3—Ge interface, according to embodiments as disclosed herein;

[0036] FIG. 10(b) illustrates TEM image captured at Ge—Gd.sub.2O.sub.3—Cr interface to show throughout uniformity of the Ge crystal stacking (Note: here Cr stands for Chromium), according to embodiments as disclosed herein;

[0037] FIG. 10(c) illustrates An HRTEM captured at Si—Gd.sub.2O.sub.3—Ge interface showing 180° rotated epitaxial relation between Si and the BOX Gd.sub.2O.sub.3 layer, according to embodiments as disclosed herein; and

[0038] FIG. 10(d) illustrates an HRTEM image captured at Ge—Gd.sub.2O.sub.3—Cr interface to show epitaxial relation between Ge and the cap Gd.sub.2O.sub.3 layer, according to embodiments as disclosed herein.

DETAILED DESCRIPTION OF INVENTION

[0039] The embodiments herein and the various features and advantageous details thereof are explained more fully with reference to the non-limiting embodiments that are illustrated in the accompanying drawings and detailed in the following description. Descriptions of well-known components and processing techniques are omitted so as to not unnecessarily obscure the embodiments herein. Also, the various embodiments described herein are not necessarily mutually exclusive, as some embodiments can be combined with one or more other embodiments to form new embodiments. The term “or” as used herein, refers to a non-exclusive or, unless otherwise indicated. The examples used herein are intended merely to facilitate an understanding of ways in which the embodiments herein can be practiced and to further enable those skilled in the art to practice the embodiments herein. Accordingly, the examples should not be construed as limiting the scope of the embodiments herein.

[0040] The proposed method provides Single crystal-Gd.sub.2O.sub.3 deposition in Radio Frequency (RF)-sputter. Proposed method explores, epi-Gd.sub.2O.sub.3 deposition process window. The deposition of the Gd.sub.2O.sub.3 is done on 2″ RCA cleaned p-Si substrate or a Germanium (Ge) substrate with a desirable resistivity. The desirable resistivity comprises one of value greater than 1000 Ω.Math.cm, low resistance value less than 10 Ω.Math.cm or a pattern of differently doped regions the in the RF-sputter system. The proposed method is a low-cost, high-throughput and production compatible process.

[0041] In accordance with an embodiment, referring to FIG. 1(a), a method 100 providing deposition of Gadolinium Oxide (Gd.sub.2O.sub.3) on a semiconductor substrate is shown. At step 102, the method 100 provides selection of a predefined substrate. The predefined substrate comprises one of a Silicon substrate or a Germanium (Ge) substrate. The predefined substrate is selected with a resistivity value greater than 1000 SI. The predefined substrate is selected in an RF-sputter system.

[0042] At step 104, the Gd.sub.2O.sub.3 is deposited over the predefined substrate in an Ar-plasma struck, to obtain a layer of the Gd.sub.2O.sub.3 over the predefined substrate. The Gd.sub.2O.sub.3 is deposited in an Ar-plasma struck. The Gd.sub.2O.sub.3 is grown epitaxially over the predefined substrate.

[0043] At step 106, annealing is performed of the layer of the Gd.sub.2O.sub.3 over the predefined substrate at a predefined temperature for a predefined time. The annealing is performed over one or more ambient conditions. The one or more ambient conditions comprise reducing H.sub.2, oxidizing with O.sub.2 or N.sub.2O and using inert gases such as He, N.sub.2 and Argon.

[0044] At step 108, the method 100 obtains a resultant layer of the Gd.sub.2O.sub.3, over the predefined substrate.

[0045] In another embodiment, referring to FIG. 1(b), a method 200 for fabricating Semiconductor on Insulator Substrate (SIS) is discussed. At step 202, the method provides growing, an isolation layer of a Rare Earth (RE) oxide over a preselected substrate for obtaining a single crystalline seed layer at a predefined temperature in a range of 500° C. to 800° C.). The growth of the RE oxide is performed in a Physical Vapor Deposition (PVD) system and the preselected substrate acts as a base layer.

[0046] The preselected substrate comprises one of a Silicon (Si), Germanium (Ge), Tin (Sn), or alloys of the preselected substrate. The rare earth oxide comprises one of a Gd.sub.2O.sub.3, Pr.sub.2O.sub.3, Yr.sub.2O.sub.3, Sm.sub.2O.sub.3, Dy.sub.2O.sub.3.

[0047] The PVD system comprises one of an RF-Magnetron Sputter system, evaporators or CVD system.

[0048] At step 204, an amorphous semiconductor layer is deposited over the seed layer at a predefined temperature in a range of 30° C. to 200° C. and at step 206, a capping layer of the RE oxide is formed over the deposited amorphous semiconductor layer over the seed layer. The capping layer is formed at a predefined capping temperature. The predefined capping temperature comprises in a range of 500° C. to 800° C.

[0049] At step 208, the method 200 provides a removal of the RE layer grown over the preselected substrate by using an etching process for obtaining the SIS. The etching process comprises at least one of a dry etching process and a wet etching process.

[0050] In accordance with an embodiment, details of the method 100 will now be explained.

[0051] The method 100 provides single crystal-Gd.sub.2O.sub.3 deposition on the Si or Ge in the RF-sputter. The method 100 provides deposition of Ge on the single crystal-Gd.sub.2O.sub.3 at Room Temperature (RT). Finally, the method 100 provides deposition of Gd.sub.2O.sub.3 on Ge at high temperature to cap and crystallize the Ge layer.

[0052] Proposed method 100 explores, epi-Gd.sub.2O.sub.3 deposition process window. The deposition is done on 2″ RCA cleaned p-Si substrate with resistivity >1000 Ω.Math.cm in RF-sputter system—A low-cost, high-throughput and production compatible process. The process chambers base pressure is 2×10.sup.−7 Torr.

[0053] The deposition of the Gd.sub.2O.sub.3 is done in the Ar-plasma struck at a power in range of low power from 60 W to 65 W) such that the deposition rate is less than 1 nm/min (0.1-0.5 nm/min). During the deposition, pressure of process chamber pressure of the Ar-plasma struck is maintained at a predefined pressure value. The predefined pressure comprises in a range of 1×10.sup.−7 torr to 1×10.sup.−6 torr.

[0054] The deposition may be performed at one or more temperature values. The one or more temperature values comprises in a range of 600° C. to 800° C. In an exemplary embodiment, the method 100 of deposition may be executed through an experiment carried out at three different temperatures selected from the one or more temperature values. The three different temperature selected are 650° C., 700° C. and 750° C.

[0055] The method 100 is executed by using two different orientations of the silicon substrate. The two different orientations comprise each of Si<111> and Si<100> (as shown in Table 1 below).

TABLE-US-00001 TABLE 1 Table 1 Experimental splits used in the method 100 Substrate orientation Si (111) Si (100) Deposition 650° C. 700° C. 750° C. 700° C. temperature (° C.) Observations No Gd.sub.2O.sub.3 Monoclinic Monoclinic Monoclinic peak Gd.sub.2O.sub.3 Gd.sub.2O.sub.3 Gd.sub.2O.sub.3 + cubic Gd.sub.2O.sub.3

[0056] In accordance with an embodiment, in FIG. 2(a) (i), it may be observed that Gd.sub.2O.sub.3 peak is absent for T=650° C. deposition on Si (111). For temperature T>700° C., a clear peak is present, representing (−402) orientation of monoclinic Gd.sub.2O.sub.3 (as shown in FIG. 2(a) (ii) and FIG. 2(a) (iii)).

[0057] Now compared to Si (111), Si (100) substrate results in a bi-phase (including each of cubic Gd.sub.2O.sub.3 layer and monoclinic Gd.sub.2O.sub.3 layer) formation as shown in FIG. 2(a) (iv).

[0058] Due to different thermal coefficient of Si (2.6×10.sup.−6K.sup.−1) and Gd.sub.2O.sub.3 (8.0×10.sup.−1K.sup.−1), lattice matching is tunable with temperature. It may be further reported that, at T˜700° C., lattice mismatch between the silicon substrate and Gd.sub.2O.sub.3 becomes zero.

[0059] Proposed method 100 also reports that, Gd.sub.2O.sub.3 deposition over the silicon substrate Si (111) follow layer-by-layer growth mechanism, due to favorable surface energy. Hence, Gd.sub.2O.sub.3 deposition at 700° C. on Si (111) is may be preferred for epitaxial growth of the Gd.sub.2O.sub.3 over the silicon substrate.

[0060] The method 100 also provides, Annealing (Forming Gas Annealing (FGA)) performed at a predefined temperature comprising in range of 550° C. to 650° C. The FGA is performed for a predefined time comprising in a range of 10 minutes to 30 minutes for improving Gd.sub.2O.sub.3/Si interface. It may be noted that an effect of the FGA on deposited Gd.sub.2O.sub.3 over the silicon substrate (in form of crystal) is negligible as peak intensity corresponding to m-Gd.sub.2O.sub.3 (−402) in ω-2θ scan remain intact (also shown FIG. 2(b)).

[0061] The method 100 provides the layer of the Gd.sub.2O.sub.3 (in the crystal form) deposited over the predefined substrate obtained in a predefined thickness. The predefined thickness comprises in a range of 30 nm to 33 nm.

[0062] In an embodiment, referring to FIG. 2(c), the thickness of the Gd.sub.2O.sub.3 layer from XRR global fit is 32.25 nm and gives 0.63 nm/min deposition rate. Density of the Gd.sub.2O.sub.3 layer is 8.69 g/cc.

[0063] As shown in FIG. 3, a wide-angle range ω-2θ for the Gd.sub.2O.sub.3/Si (111) stack shows peaks corresponding to Si (111) at 28.44° and monoclinic Gd2O3 (−402) at 30.01°. Appearance of Gd.sub.2O.sub.3 (−804) peak at 62.5° is expected from the ‘epi-Gd.sub.2O.sub.3 deposition’.

[0064] Referring to FIG. 4(a), Transmission Electron Microscopy (TEM) image on a 50 nm scale shows a uniform deposition of the Gd.sub.2O.sub.3 layer. A high-resolution TEM image of Gd.sub.2O.sub.3 (−402)/Si(111) stack on a 2 nm scale shows perfectly ordered Gd.sub.2O.sub.3 crystal planes. FIG. 4(b) shows respective Electron Diffraction (ED) for Gd.sub.2O.sub.3 crystal planes (FIG. 4(b)—inset). Ordered arrangement of (−402) planes in TEM image confirms epitaxial Gd.sub.2O.sub.3 deposition. The rms roughness of 0.29 nm is extracted for the epi-Gd.sub.2O.sub.3 layer from Atomic Force Microscope (AFM) (shown in FIG. 5(a)).

[0065] Now referring to FIG. 5(b), electrical characterization of the layer is shown. As shown in FIG. 5(b), MOSCAP structure (Al/Gd.sub.2O.sub.3/Si/Al) is fabricated and characterized. Top contact of the MOSCAP is patterned (50×50 μm.sup.2) using UV-lithography and back contact is a blanket Al-evaporation (shown in FIG. 5(c)).

[0066] In FIG. 6(a), Capacitance-Voltage (CV) measurements after series resistance correction show a kink due to the presence of sharp trap energy distribution at the Gd.sub.2O.sub.3/Si interface and the location shifts after FGA (shown in FIG. 6(b)).

[0067] Referring to FIG. 6(c), Interface trap density (D.sub.it) is extracted in each cases at 10 kHz frequency. The D.sub.it extracted before and after FGA is 8.4×10.sup.12 eV.sup.−1 cm.sup.−2 and 3.4×10.sup.12 eV.sup.−1 cm.sup.−2 respectively. Dielectric constant (K) extracted for before and after FGA structure is 13 and 11 respectively. Low leakage current density ˜2.48×10.sup.−5 A/cm.sup.2 is calculated at 4.6 MV/cm electric field (for without FGA) (shown in FIG. 6(d)). Further, hysteresis in current profile indicates trapped charge movement.

[0068] High temperature (700° C.) vis a vis process conditions to enable low deposition rate (0.63 nm/min) facilitates Gd.sub.2O.sub.3 epitaxy on Si with appropriate substrate orientation in RF sputter. Formation of monoclinic epi-Gd.sub.2O.sub.3 with (−402) orientation on Si (111) is confirmed by X-Ray Power Diffraction (XRD) and TEM imaging. Finally, comparable electrical qualities with state-of-art Gd.sub.2O.sub.3 (MBE, ALD and Sputter) results is demonstrated (Table 2). Demonstration of epi-Gd.sub.2O.sub.3 on Si in a HVM RF-sputter is a precursor to low-cost SOI-wafer.

[0069] Table-2 below shows performance comparison for Gd.sub.2O.sub.3 MOSCAP fabricated:

TABLE-US-00002 TABLE 2 Proposed Reference Prior art Prior art Prior art method 100 Stack Gd.sub.2O.sub.3/Si(001) Gd.sub.2O.sub.3/Si(111) Gd.sub.2O.sub.3/Si(111) Tool used ALD RF sputter MBE RF sputter Gd.sub.2O.sub.3 Poly Poly (Cubic SC (cubic) SC quality (cubic) + (Monoclinin) Monoclinic) Thickness 10 12 5 32.25 (nm) Dielectric 15 9.3-17.2 — 11-13 constant Trap 3.2 × 10.sup.12 — 2.4 × 10.sup.12 3.4 × 10.sup.12 density (eV.sup.−1cm.sup.−2) Current ~3.1 × 10.sup.−6 ~7 × 10.sup.−1 ~9 × 10.sup.−5 2.5 × 10.sup.−5 density (A/cm.sup.2) @ 4.6 MV/cm

[0070] In accordance with an embodiment, details of the method 200 will now be explained. The method 200 provides a low cost SOI, GeOI and SiGeOI substrate using solid phase epitaxy technique in a thin film deposition system, like RF magnetron sputter system. The RE oxides are used as isolation layer, due to low lattice mismatch and lattice parameters are tunable with temperature. The lattice parameters will be negligible at 700° C.

[0071] FIG. 7 illustrates the schematics of the method 200 showing process flow involved in growing the Gd.sub.2O.sub.3—Ge—Gd.sub.2O.sub.3 hetero-structure on Si(111) substrate.

[0072] The proposed method 200 also provides the deposition of Ge on the Gd.sub.2O.sub.3 at room temperature in the same RF sputter system (as discussed above). Further the method 100 provides deposition of Gd.sub.2O.sub.3 cap layer on the Ge at high temperature in order to crystalize the Ge layer and prevents an island formation in the Ge layer (shown in step 1 and step 2 of FIG. 7).

[0073] Once the Gd.sub.2O.sub.3—Ge—Gd.sub.2O.sub.3 hetero-structure is deposited on Si substrate, the Gd.sub.2O.sub.3 cap layer is removed using dilute sulfuric acid for obtaining the resultant of the Gd.sub.2O.sub.3 over the predefined substrate (shown in step 3, 4 and 5 of FIG. 7).

[0074] As discussed above, at first cubic rare earth (RE) oxide is grown as a seed layer on the Si substrate at high temperature in a range of (500° C.-800° C.) and predefined RF power. The predefined RF power comprises in a range of 15 W to 25 W essentially to keep the deposition rate less than 1 nm/min in a PVD (RF-Magnetron sputter) system.

[0075] After the RE oxide is grown as the seed layer, the amorphous semiconductor layer is then deposited over the seed layer at room temperature in the deposition chamber (step 2 of FIG. 7). The method 700 is the followed by depositing the capping layer of RE oxide over amorphous semiconductor layer at high temperature in the deposition chamber.

[0076] Lastly, for obtaining the SOI, RE oxide (as deposited on top) is removed by using the etching process. The removal may be done by using at least one of the wet etching and the dry etching (step 4 and step 5 of FIG. 7). In an example, at first a dry etching may be carried out and near an interface of the SOI, the wet etching may be used to prevent surface roughness increase.

[0077] The removal of RE oxide capping layer, will result in semiconductor on insulator stack which is essential to reduce substrate leakage and improve short channel effect in RF and CMOS logic applications.

[0078] Furthermore, the method 200 also provides a growth of an epi-semiconductor layer over the SOI after the etching is performed. The growth of the epi-semiconductor layer over the SOI improves semiconductor quality of the SOL The growth of the epi-semiconductor may be carried out in same deposition chamber (PVD or CVD) at high temperature.

[0079] FIG. 8(a) illustrates the X-ray diffraction pattern for the Gd.sub.2O.sub.3—Ge—Gd.sub.2O.sub.3 hetero-structure deposited using solid phase epitaxy (SPE) in RF magnetron sputter chamber over Si(111) substrate for a symmetric ω-2θ scan on wide angle range for Gd.sub.2O.sub.3—Ge—Gd.sub.2O.sub.3 hetero-structure, which primarily shows Si peak.

[0080] FIG. 8(b) illustrates the X-ray diffraction pattern for the Gd.sub.2O.sub.3—Ge—Gd.sub.2O.sub.3 hetero-structure deposited using solid phase epitaxy (SPE) in RF magnetron sputter chamber over Si(111) substrate for a small angle range symmetric ω-2θ scan, where, the presence of Ge(111) peak at an angle 2θ=27.3° is highlighted in the inset.

[0081] FIG. 8(c) illustrates the X-ray diffraction pattern for the Gd.sub.2O.sub.3—Ge—Gd.sub.2O.sub.3 hetero-structure deposited using solid phase epitaxy (SPE) in RF magnetron sputter chamber over Si(111) substrate for small angle range ω-2θ scan of the hetero-structure done with monochromator while aligning the samplew. r.t the Ge(111) Bragg's angle (20=27.3°) by adjusting the χ to highlight the Ge(111) peak, showing a significantly weak but clear intensity peak-consistent with the high intensity peak without the monochromator in (b).

[0082] Appearance of Ge(111) peak at 27.3° and absence of any other stray peak is a primary evidence of the Ge layer being single crystalline.

[0083] FIG. 9(a) illustrates φ scan is done for Ge(111) plane by fixing the 2θ=27.3.sup.i and the χ=70.5° and FIG. 9(b) shows a pole figure measurement done to probe Ge(111) crystal plane family by fixing 20=27.3°. FIG. 9(c) shows an ω-2θ scan done by fixing φ=50° and χ=70.5°. A presence of Ge(111) crystal plane establishes the formation of single crystalline Ge layer with (111) orientation.

[0084] FIG. 10 (a) illustrates a HRTEM image reflecting uniform layer of Ge crystals on Gd.sub.2O.sub.3 layer captured at Si—Gd.sub.2O.sub.3—Ge interface and FIG. 10(b) shows TEM image captured at Ge—Gd.sub.2O.sub.3—Cr interface to show throughout uniformity of the Ge crystal stacking (Note: here Cr stands for Chromium).

[0085] FIG. 10(c) shows the HRTEM captured at Si—Gd.sub.2O.sub.3—Ge interface showing 180° rotated epitaxial relation between Si and the BOX Gd.sub.2O.sub.3 layer and FIG. 10(d) shows the HRTEM image captured at Ge—Gd.sub.2O.sub.3—Cr interface to show epitaxial relation between Ge and the cap Gd.sub.2O.sub.3 layer.

[0086] In the proposed method 200, the single crystalline cubic RE oxide may be deposited on the Si substrate. Phase transformation from cubic crystal (SOI) to monoclinic crystal (SOI) without disturbing stacking order may be selected based on one or more deposition conditions. The one or more deposition conditions comprises deposition at 60±20 W RF power and at 750±100° C. substrate temperature.

[0087] Epi-semiconductor layer may be formed on the insulator, for example, the proposed method 200 is capable of fabricating substrates for PDSOI with thickness in a range of 50 nm to 80 nm and FDSOI with thickness in a range of 3 nm to 7 nm.

[0088] Use of Al.sub.2O.sub.3 as isolation and capping oxide or use of sapphire substrate will enable the III-V semiconductors as channel materials for semiconductor-on-insulator substrate fabrication.

[0089] Proposed SOI fabricated through the method 200 may be used for variety of applications. The variety of applications can be 3D integrations, 3D memory, optical devices (Bragg reflectors, waveguides etc.) etc.

[0090] The proposed SOI fabricated through the method 200 provides a hetero-structure with excellent structural quality and may be used for novel Nano-electronics applications such as Nano scale devices with high channel mobility, resonant tunneling devices etc. By altering deposition conditions, a desired strain may also be introduced in the SOI channel layer.

[0091] In addition to the sputter process provided through the method 700, a sample preparatory chamber may also be used to enable high temperature bake-out or pre-plasma treatment (e.g. H2 plasma or HF) for surface clean.

[0092] Interface quality of the SOI may also be fixed by interface engineering, e.g. (Gd.sub.2O.sub.3): (Al.sub.2O.sub.3) (x: y), may be graded in x-y and z direction to adjust lattice constant in an analog manner. The predefined substrate is silicon substrate with <111> orientation however, other orientations <100> and <110> are also possible.

[0093] The foregoing description of the specific embodiments will so fully reveal the general nature of the embodiments herein that others can, by applying current knowledge, readily modify and/or adapt for various applications such specific embodiments without departing from the generic concept, and, therefore, such adaptations and modifications should and are intended to be comprehended within the meaning and range of equivalents of the disclosed embodiments. It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Therefore, while the embodiments herein have been described in terms of preferred embodiments, those skilled in the art will recognize that the embodiments herein can be practiced with modification within the spirit and scope of the embodiments as described herein.