Readout circuit for resistive and capacitive sensors

Abstract

A readout circuit for resistive and capacitive sensors includes a first input coupled to a reference resistor in a first mode of operation and coupled to a resistive sensor in a second mode of operation; a second input coupled to a capacitive sensor in the first mode of operation and coupled to a reference capacitor in the second mode of operation; and an output for providing a capacitive sensor data stream in the first mode of operation and for providing a resistive sensor data stream in the second mode of operation.

Claims

1. A circuit comprising: a first input coupled to a reference resistor in a first mode of operation and coupled to a resistive sensor in a second mode of operation; a second input coupled to a capacitive sensor in the first mode of operation and coupled to a reference capacitor in the second mode of operation; an output for providing a capacitive sensor data stream in the first mode of operation and for providing a resistive sensor data stream in the second mode of operation; and a voltage-to-current converter coupled to the first input, wherein the voltage-to-current converter comprises an amplifier selectively coupled to a first current mirror portion in the first mode of operation and selectively coupled to a second current mirror portion different from the first current mirror portion in the second mode of operation by a switch directly coupled to an output of the amplifier, wherein a third current mirror portion is selectively coupled to the first current mirror portion in the first mode of operation, wherein the third current mirror portion is selectively coupled to the second current mirror portion in the second mode of operation, the first and third current mirror portions comprising a first current mirror in the first mode of operation, and the second and third current mirror portions comprising a second current mirror in the second mode of operation, and wherein the first current mirror portion comprises an input transistor of the first current mirror, the second current mirror portion comprises an input transistor of the second current mirror, and the third current mirror portion comprises an output transistor of the first current mirror in the first mode of operation and of the second current mirror in the second mode of operation.

2. The circuit of claim 1, further comprising an integrator coupled to the voltage-to-current converter and the second input.

3. The circuit of claim 2, wherein the integrator comprises an amplifier coupled to first and second switches configured in a first position in the first mode of operation and configured in a second position in the second mode of operation.

4. The circuit of claim 2, further comprising a logic circuit coupled to the integrator and to the output.

5. The circuit of claim 4, wherein the logic circuit comprises a first comparator having a first threshold voltage coupled to a second comparator having a second threshold voltage.

6. An integrated circuit comprising: a first input pin for coupling to a resistor; a second input pin for coupling to a capacitor; an output pin configured to provide a data stream corresponding to a value of the capacitor in a first mode of operation and for providing a data stream corresponding to a value of the resistor in a second mode of operation; and a voltage-to-current converter coupled to the first input, wherein the voltage-to-current converter comprises an amplifier selectively coupled to a first current mirror portion in the first mode of operation and selectively coupled to a second current mirror portion different from the first current mirror portion in the second mode of operation by a switch directly coupled to an output of the amplifier, wherein a third current mirror portion is selectively coupled to the first current mirror portion in the first mode of operation, wherein the third current mirror portion is selectively coupled to the second current mirror portion in the second mode of operation, the first and third current mirror portions comprising a first current mirror in the first mode of operation, and the second and third current mirror portions comprising a second current mirror in the second mode of operation, and wherein the first current mirror portion comprises an input transistor of the first current mirror, the second current mirror portion comprises an input transistor of the second current mirror, and the third current mirror portion comprises an output transistor of the first current mirror in the first mode of operation and of the second current mirror in the second mode of operation.

7. The circuit of claim 6, further comprising an integrator coupled to the voltage-to-current converter and the second input.

8. The circuit of claim 7, wherein the integrator comprises an amplifier coupled to first and second switches configured in a first position in the first mode of operation and configured in a second position in the second mode of operation.

9. The circuit of claim 7, further comprising a logic circuit coupled to the integrator and to the output.

10. The circuit of claim 9, wherein the logic circuit comprises a first comparator having a first threshold voltage coupled to a second comparator having a second threshold voltage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) For a more complete understanding of the invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

(2) FIGS. 1-3 are block diagram of ASIC integrated circuits according to embodiments;

(3) FIG. 4 is a schematic diagram of a substantially analog portion of a readout circuit according to an embodiment;

(4) FIG. 5 is a schematic diagram of a substantially analog portion of a readout circuit according to another embodiment;

(5) FIG. 6 is a block diagram of an ASIC integrated circuit according to another embodiment illustrating analog and digital portions, according to an embodiment;

(6) FIG. 7 is a timing diagram associated with the ASIC integrated circuit of FIG. 6; and

(7) FIG. 8 shows an integrated readout circuit embodiment resident in a device.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

(8) FIG. 1 shows an ASIC 100A including in pertinent part a voltage-to-current converter 102 coupled to an integrator 104, which is in turn coupled to a logic circuit 106 as will be described in further detail below. In a first mode of operation a two node input 108 is coupled to a variable resistor R.sub.SENS, which represents a resistive sensor, and a two node input 110 is coupled to a fixed capacitor C.sub.REF, which represents a capacitive reference. ASIC 100A is thus configured for reading out the data based on the resistive variations of the resistive sensor.

(9) FIG. 2 shows an ASIC 100B including in pertinent part a voltage-to-current converter 102 coupled to an integrator 104, which is in turn coupled to a logic circuit 106 as will be described in further detail below. In a second mode of operation a two node input 108 is coupled to a fixed resistor R.sub.REF, which represents a resistive reference, and a two node input 110 is coupled to a variable capacitor C.sub.SENS, which represents a capacitive sensor. ASIC 100B is thus configured for reading out data based on the capacitive variations of the capacitive sensor.

(10) FIG. 3 shows an ASIC 100C including in pertinent part a voltage-to-current converter 102 coupled to an integrator 104, which is in turn coupled to a logic circuit 106 as will be described in further detail below. In a third mode of operation a two node input 108 is coupled to a variable resistor R.sub.SENS, which represents a resistive sensor, and a two node input 110 is coupled to a variable capacitor C.sub.SENS, which represents a capacitive sensor. Both sensors are coupled to ASIC readout circuit at the same time in an embodiment. ASIC 100C is thus configured for reading out composite serial data based on the resistive variations of the resistive sensor and on the capacitive variations of the capacitive sensor. The third mode of operation may be used for example, in capacitive and resistive sensors that have non-overlapping response characteristics. The non-overlapping response characteristic can be viewed as the first sensor acting as a reference for the second sensor in, for example, a first frequency range, and the second sensor acting as a reference for the first sensor in, for example, a second non-overlapping frequency range. Other examples where both sensors can be coupled to the readout circuit at the same time can include differential sensors, including a first capacitive sensor and a second resistive sensor. Still further examples where both sensors can be coupled to the readout circuit at the same time can include triggered sensors, whose function is to change state in response to an input. Linear sensors can be used as well, but the output of the readout circuit will be a product of the two sensors outputs that may have use in a particular implementation.

(11) FIG. 4 shows a schematic of a possible implementation of the architecture of a readout circuit, according to an embodiment. Circuit 400 includes a voltage-to-current (V2I) converter, where two OPAMPs A1 and A2 and transistors M.sub.1A/M.sub.2A provide a biasing voltage across sensing resistance, R.sub.SENS, using two stable reference and bias voltages V.sub.REF_P and V.sub.REF_N. The two OPAMPs A1 and A2 and transistors M.sub.1B/M.sub.2B provide a biasing voltage across reference resistance, R.sub.REF, using the two stable reference and bias voltages V.sub.REF_P and V.sub.REF_N. Switches S1, S2, S3, and S4 couple the sensor resistor R.sub.SENS to the sources of transistors M.sub.1A and M.sub.2A in a first position, and couple the reference resistor R.sub.REF to the sources of transistors M.sub.1B and M.sub.2B in a second position. The feedback and source follower structure shown in FIG. 4 guarantees low output resistance at all buffered nodes (source of transistor M.sub.1A, source of transistor M.sub.2A, source of transistor M.sub.1B, and source of transistor M.sub.2B). The stable biasing at both sensing resistor R.sub.SENS terminals ensures a better stability of the sensor and isolates it from ground and supply voltages. A signal current I.sub.SENS=(V.sub.REF_P−V.sub.REF_N)/R.sub.SENS is then mirrored and alternatively sunk from or sourced in a virtual ground of an integrator including OPAMP A.sub.5, according to control signals CTRL_H and CTRL_L. These control signals direct switches S.sub.5 and S.sub.6. In a first position the drain of transistor M.sub.3 is coupled to the input of OPAMP A.sub.5, and the drain of transistor M.sub.4 is coupled to V.sub.DD. In a second position the drain of transistor M.sub.4 is coupled to the input of OPAMP A.sub.5, and the drain of transistor M.sub.3 is coupled to ground.

(12) Switches S.sub.9 and S.sub.10 are used to couple either the capacitive sensor C.sub.SENSE of the capacitive reference to OPAMP A.sub.5. A reset transistor M.sub.9 receives a Reset control signal and the source and drain nodes of transistor M.sub.9 are coupled between the negative input and output V.sub.O of OPAMP A.sub.5. The positive input of OPAMP A.sub.5 is coupled to a common mode voltage V.sub.CM.

(13) Switch S.sub.7 is used to form a first current mirror with transistors M.sub.5A and M.sub.7 in a first position, and is used to form a second current mirror with transistors M.sub.5B and M.sub.7 in a second position. Both current mirrors have a ratio of δ as shown. Similarly, switch S.sub.8 is used to form a first current with transistors M.sub.6A and M.sub.8 in a first position, and is used to form a second current with transistors M.sub.6B and M.sub.8 in a second position. Both current mirrors have a ratio of δ as shown. The current mirrors formed with transistor M.sub.7 include an output resistance boosting circuit using OPAMP A.sub.3 and transistor M.sub.3, as will be explained in further detail below. The current mirrors formed with transistor M.sub.8 include an output resistance boosting circuit using OPAMP A.sub.4 and transistor M.sub.4, as will be explained in further detail below.

(14) At the output of the integrator including OPAMP A.sub.5, the voltage V.sub.O is a triangular waveform that is compared to two reference voltages (V.sub.TH and V.sub.TL) to generate switch control signals and to steer current. A first comparator 402 receives the V.sub.O triangular output voltage and the V.sub.TH reference voltage to generate a first variable frequency output voltage that is coupled to the SN input of latch 406. A second comparator 404 receives the V.sub.O triangular output voltage and the V.sub.TL reference voltage to generate a second variable frequency output voltage that is coupled to the RN input of latch 406. Latch 406 generates the CTRL_H control signal at the Q output and the CTRL_L control signal at the QN output as shown. The presence of an additional latch 406 always guarantees the synchronized switching of comparators. A variable frequency output signal having a period T.sub.OSC in a particular time period is shown in FIG. 4. The variable frequency output of the circuit 400 shown in FIG. 4 is at the Q or QN output of latch 406.

(15) The output period waveform is proportional to the sensor resistance value according to the following expression:

(16) $\begin{array}{cc}{T}_{\mathrm{OSC}}=\frac{2C_{\mathrm{REF}}.Math.\Delta V.Math.R_{\mathrm{SENS}}}{\delta .Math.V_{\mathrm{REF}}}& \left[1\right]\end{array}$

(17) Where ΔV=V.sub.TH−V.sub.TL is the input switching window of comparators 402 and 404 and δ is the current ratio of the current mirrors including transistors M.sub.7 and M.sub.8 as previously discussed. The digital conversion of the variable frequency output signal to a serial data bit stream is performed by counting how many oscillations occur in a precisely defined time window, as will be discussed in further detail below with respect in particular to the description of FIG. 6.

(18) Equation [1] was used to measure the resistance value of a resistive sensor. By inverting the roles of R and C in the above equation it is possible to use the same architecture to measure an unknown capacitor value in a capacitive sensor. In the resistance-to-frequency conversion of equation [1] the unknown parameter is R.sub.SENS, and the capacitance value is fixed. In the capacitance-to-frequency conversion of equation [2] a reference resistor R.sub.REF is used to generate a constant current I.sub.SENS to be integrated in the sensor capacitance C.sub.SENS leading to an oscillation frequency proportional to C.sub.SENS itself:

(19) $\begin{array}{cc}{T}_{\mathrm{OSC}}=\frac{2C_{\mathrm{SENS}}.Math.\Delta V.Math.R_{\mathrm{REF}}}{\delta .Math.V_{\mathrm{REF}}}& \left[2\right]\end{array}$

(20) The interface can be adapted to convert a matrix of resistive sensors by having the multiplexing switches working on high impedance nodes as shown in FIG. 4, avoiding the introduction of parasitic resistances that can cause additional errors in the measurement. Alternatively, the interface can be adapted to convert a matrix of capacitive sensors by having the multiplexing switches or a combination of resistive and capacitive sensors. Switches S1 through S8 can be used to provide a multiplexing function, or can be set in a fixed position that might be required to accommodate a single sensor in an application. It will be apparent to those skilled in the art that a multiplicity of sensors can be used in a multiplexing mode of operation, but will result in a multiplexed data output stream, wherein only a periodic portion of the data output stream will be associated with an individual capacitive or resistive sensor.

(21) Current mirrors have to maintain a very high linearity for a very wide range of currents due to the large variations in the resistance value of R.sub.SENS. Choosing regulated cascoded topologies for the mirrors is then strongly advised and OPAMPs A3 and A4 should have sufficiently high gain to boost each current mirror's output impedance. To better fit operative point constraints OPAMP A3 uses a p-input topology while OPAMP A4 uses a complementary n-input topology.

(22) Transistors M.sub.1A, M.sub.1B, M.sub.2A, and M.sub.2B ideally have a very large W/L ratio to keep their overdrive low and to avoid saturation of the outputs of amplifier A.sub.1 and A.sub.2 in high I.sub.SENS conditions. Transistors M.sub.3 and M.sub.4 ideally ensure that the outputs of OPAMPs A3 and A4 are always sufficiently separated from V.sub.DD and GND, and thus they have a much lower W/L ratio.

(23) The value of R.sub.REF used to evaluate C.sub.SENS should be chosen to have the current mirrors working with a constant current in their best nominal operative point to ensure the best linearity response in all conditions.

(24) Integrator OPAMP (A5) and comparators 402 and 404 shown ideally be fast enough to cope with a maximum oscillation frequency. The comparators input switching window ΔV should be as large as possible to lower the comparators' offset impact on output resolution.

(25) A similar implementation to that of FIG. 4 is shown in FIG. 5. In the circuit 500 shown in FIG. 5 only one terminal of the resistive sensing element is available, and the V2I converter provides biasing between the available terminal and ground.

(26) Thus, FIG. 5 shows a schematic of a possible implementation of the architecture of a readout circuit, according to another embodiment. Circuit 500 includes a voltage-to-current (V2I) converter, where a single OPAMP A1 and transistors M.sub.1A provides a biasing voltage across sensing resistance, R.sub.SENS, using a stable reference and bias voltages V.sub.REF. The single OPAMP A1 and transistors M.sub.1B provides a biasing voltage across reference resistance, R.sub.REF, using a single stable reference and bias voltages V.sub.REF. Both the resistive sensor R.sub.SENS and the resistive reference resistance R.sub.REF are coupled to ground. Switches S1 and S2 couple the sensor resistor R.sub.SENS to the source of transistors M.sub.1A in a first position, and couple the reference resistor R.sub.REF to the source of transistors M.sub.1B in a second position. The feedback and source follower structure shown in FIG. 5 guarantees a low output resistance at the source of transistor M.sub.1A and the source of transistor M.sub.2A. A signal current I.sub.SENS=V.sub.REF/R.sub.SENS is then mirrored and alternatively sunk from or sourced in a virtual ground of an integrator including OPAMP A.sub.5, according to control signals CTRL_H and CTRL_L. These control signals direct switches S.sub.5 and S.sub.6. In a first position the drain of transistor M.sub.7B is coupled to the input of OPAMP A.sub.5, and the drain of transistor M.sub.8B is coupled to V.sub.DD. In a second position the drain of transistor M.sub.8B is coupled to the input of OPAMP A.sub.5, and the drain of transistor M.sub.7B is coupled to ground.

(27) Switch S.sub.7 is used to form a first dual output current mirror with transistors M.sub.5A and M.sub.7A and M.sub.7B in a first position, and is used to form a second dual output current mirror with transistors M.sub.5B and M.sub.7A and M.sub.7B in a second position. Both current mirrors have a ratio of δ as shown.

(28) The remaining circuitry in FIG. 5 relates to the integration circuit and the triangle wave to variable frequency output signal conversion previously described.

(29) An ASIC 100D is shown in FIG. 6 in greater detail than previously described, showing a substantially analog section 116 and a digital section 118 that includes, in part, a frequency-to-serial-data converter. The analog section 116 is substantially as previously described including the V2I converter 102, the integrator 104, and the comparator section 106. Also shown in the analog section 116 is a two node input 108 for receiving input from a resistive sensor, and a two node input 110 for receiving input from a reference capacitor in an embodiment. A reference internal clock 114 is used to generate a time window (used as a base for the sensor measurements.) Also shown is a bandgap circuit 112 for generating the voltage and current references used.

(30) The digital section 118 converts the frequency of the triangular wave signal at the output of the integrator into a digit which can be communicated at the ASIC output, with a single bit interface. In pertinent part, the number of rising/falling edges of the wave at the output of the integrator in a reference stable time window are counted. The digital section 118 includes a register 120, a comparator 122, a reference counter 124, and a GAS counter 126 having an output bus 128. Also shown in digital section 118 are a multiplexer 130, a state machine 132, and a parallel-to-serial converter 134. A reset and enable bus is coupled to the integrator 104, GAS counter 126, reference counter 124, state machine 132, and parallel-to-serial converter 134, and brought out to a strobe pin as shown.

(31) Pins on the ASIC 100D include, but are not limited to, an analog supply voltage VDDANA, a digital supply voltage VDDDIG, a two-bit time window select, a start measurement, and end measurement strobe, a data output, and two node inputs 108 and 110.

(32) Referring to the timing diagram of FIG. 6, a waveform diagram shows the following signals: clk, sensor_signal, start_meas, count_en, clk_count, signal_count, serial_data, and data_flag.

(33) The “clk” signal is the internal 500 KHz clock signal previously described.

(34) The “sensor_signal” is the output of a capacitive or resistive signal.

(35) The “start_meas” signal is a pulse that begins a measurement cycle.

(36) The “count_en” is a signal that goes high when the clock cycles and sensor signal cycles are being counted.

(37) The “clk_count” signal shows the count progression of the number of clock signals being counted.

(38) The “signal_count” signal counts the rising/falling (depending on the implementation but this is not relevant) edges of the voltage signal generated at the output of the integrator and squared with a comparator.

(39) The “serial_data” signal is sell explanatory and refers to the serial data provided at an output pin to the user, multiplexing one or more resistive and/or capacitive sensors.

(40) The resolution of the serial data provided by ASIC 100D depends on time window duration and clock frequency. The resolution will be improved, generally speaking, with a longer window duration and a higher clock frequency.

(41) FIG. 8 shows in block diagram form, a device 800, such as a cell phone, wherein an integrated readout circuit 802 interacts with a plurality of external resistive references 806, resistive sensors 808, capacitive references 810, and capacitive sensors 812. A device processor 804 is also shown for interacting with readout circuit 802 and for controlling the availability of the references and sensors. In FIG. 8, the sensors and references would be integrated together on the same integrated circuit 802, or external to the integrated circuit 802 but resident on the device 800, or a combination of the two. The six inputs shown in readout circuit 802 could correspond to the circuit 400 of FIG. 4 in an embodiment as follows: IN1 source of transistor M.sub.1A, IN2 source of transistor M.sub.2A, IN3 source of transistor M.sub.1B, IN4 source of transistor M.sub.2B, IN5 negative input of OPAMP A5, and IN6 output of OPAMP A6.

(42) In a first mode of operation, one of the reference resistors 806 and one of the capacitive sensors 812 could be selected and coupled to the appropriate inputs of circuit 400. In a second mode of operation, one of the reference capacitors 810 and one of the resistive sensors 808 could be selected and coupled to the appropriate inputs of circuit 400. In a third mode of operation, one of the resistive sensors 808 and one of the capacitive sensors 812 could be selected and coupled to the appropriate inputs of circuit 400.

(43) Circuit 400 can be configured in an embodiment to multiplex between two or all three modes of operation. Different sensors and references can also be selected from a plurality of sensors and references and multiplexed as desired. Other embodiments can be hardwired to fix operation in the first, second, or third mode operation if desired.

(44) While this invention has been described with reference to illustrative embodiments, this description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.