Abstract
An optoelectronic semiconductor device and a method for manufacturing an optoelectronic semiconductor device are disclosed. In an embodiment an optoelectronic semiconductor device includes a semiconductor body having a first region of a first conductive type, an active region configured to generate electromagnetic radiation, a second region of a second conductive type and a coupling-out surface configured to couple-out the electromagnetic radiation, wherein the first region, the active region and the second region are arranged along a stacking direction, wherein the active region extends from a rear surface opposite the coupling-out surface to the coupling-out surface along a longitudinal direction transverse to or perpendicular to the stacking direction, and wherein the coupling-out surface is arranged plane-parallel to the rear surface.
Claims
1. An optoelectronic semiconductor device comprising: a semiconductor body comprising: a first region of a first conductive type; an active region configured to generate electromagnetic radiation; a second region of a second conductive type; and a coupling-out surface configured to couple-out the electromagnetic radiation, wherein the first region, the active region and the second region are arranged along a stacking direction, wherein the active region extends from a rear surface opposite the coupling-out surface to the coupling-out surface along a longitudinal direction transverse to or perpendicular to the stacking direction, and wherein the coupling-out surface is arranged plane-parallel to the rear surface.
2. The optoelectronic semiconductor device according to claim 1, wherein the optoelectronic semiconductor device is configured to generate coherent radiation.
3. The optoelectronic semiconductor device according to claim 1, wherein the semiconductor body has an extension in the longitudinal direction of less than 300 μm.
4. The optoelectronic semiconductor device according to claim 1, wherein at least a portion of the semiconductor body is based on a nitride compound semiconductor material.
5. The optoelectronic semiconductor device according to claim 1, wherein the coupling-out surface and the rear surface run parallel to a m-plane of a crystal of the semiconductor body.
6. The optoelectronic semiconductor device according to claim 1, wherein the semiconductor body is deposited on a growth substrate and the growth substrate comprises sapphire, gallium nitride, silicon carbide or silicon.
7. The optoelectronic semiconductor device according to claim 1, wherein the coupling-out surface and the rear surface have an average roughness in a range from 0.1 nm to 10 nm.
8. The optoelectronic semiconductor device according to claim 1, further comprising a mirror arranged downstream of the rear surface.
9. The optoelectronic semiconductor device according to claim 8, wherein the mirror comprises a material of the semiconductor body.
10. The optoelectronic semiconductor device according to claim 1, further comprising a mirror arranged downstream of the coupling-out surface. ii. The optoelectronic semiconductor device according to claim 10, wherein the mirror comprises a material of the semiconductor body.
12. The optoelectronic semiconductor device according to claim 1, wherein the first region at the coupling-out surface has at least one step in the longitudinal direction.
13. The optoelectronic semiconductor device according to claim 12, wherein the step is structured so that the electromagnetic radiation emitted from the semiconductor body does not strike the step.
14. The optoelectronic semiconductor device according to claim 12, wherein a width b.sub.n of the at least one step of the first region in the longitudinal direction is structured in such a way that it satisfies the following formula up to a deviation of +/−10%: b.sub.n<[(h.sub.n-a-w)/tan(α/2)]−(b.sub.n-1-b.sub.n-2- . . . -b.sub.2-b.sub.1), wherein a is a distance of the active region from a side of the second region facing away from the active region, h.sub.n is an extent of the coupling-out surface in a direction parallel to the stacking direction of the semiconductor body, w is a waveguide thickness on a side of the first region remote from the active region, α is defined as vertical far field angle, and the index n stands for a number of steps.
15. The optoelectronic semiconductor device according to claim 1, wherein the coupling-out surface and the rear surface are coated with a semi-crystalline material.
16. The optoelectronic semiconductor device according to claim 1, wherein the coupling-out surface and the rear surface are coated with a dielectric material.
17. The optoelectronic semiconductor device according to claim 1, wherein the coupling-out surface and the rear surface are coated with a metal.
18. An optoelectronic semiconductor device comprising: a semiconductor body comprising: a first region of a first conductive type; an active region configured to generate electromagnetic radiation; a second region of a second conductive type; and a coupling-out surface configured to couple-out the electromagnetic radiation, wherein the first region, the active region and the second region are arranged along a stacking direction, wherein the active region extends from a rear surface opposite the coupling-out surface to the coupling-out surface along a longitudinal direction transverse to or perpendicular to the stacking direction, wherein the coupling-out surface is arranged plane-parallel to the rear surface, and wherein the coupling-out surface and the rear surface of the semiconductor body are produced by an etching process.
19. The optoelectronic semiconductor device according to claim 18, wherein characteristics of the coupling-out surface and the rear surface being produced by the etching process are verifiable on the optoelectronic semiconductor device, and wherein the characteristics are irregularities on the coupling-out surface and the rear surface caused by different etching rates in different materials or steps on the rear surface and the coupling-out surface.
20. The optoelectronic semiconductor device according to claim 18, wherein characteristic of the coupling-out surface and the rear surface being produced by the etching process are verifiable on the optoelectronic semiconductor device, and wherein the characteristic is a distance of less than 300 μm between the coupling-out surface and the rear surface.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0044] Further advantages and advantageous embodiments and further designs of the optoelectronic semiconductor device result from the following exemplary embodiments in connection with the figures.
[0045] Showing in:
[0046] FIGS. 1A, 2A, 3A, 4A, 5A and 6A show schematic representations of a top view of a wafer composite with a plurality of optoelectronic semiconductor devices in various steps of production according to an exemplary embodiment of a method;
[0047] FIGS. 1B, 2B, 3B, 4B, 5B and 6B show schematic cross-sections through an optoelectronic semiconductor device according to a first exemplary embodiment in different steps of its manufacturing according to the exemplary embodiment of a method;
[0048] FIG. 7 shows a schematic cross-section through an optoelectronic semiconductor device according to the first exemplary embodiment;
[0049] FIGS. 8A to 8C show an optoelectronic semiconductor device according to the first exemplary embodiment in various schematic sections and views;
[0050] FIGS. 9A and 9B show an optoelectronic semiconductor device according to a second exemplary embodiment in a schematic cross-section and a top view;
[0051] FIG. 10 shows a schematic cross-section through an optoelectronic semiconductor device according to a third exemplary embodiment;
[0052] FIG. 11 shows a schematic cross-section through an optoelectronic semiconductor device according to a fourth exemplary embodiment; and
[0053] FIG. 12 shows a top view of a plurality of optoelectronic semiconductor devices in a bar configuration.
[0054] Same, similar or equivalent elements are provided with the same reference signs in the figures. The figures and the proportions of the elements depicted in the figures are not to be regarded as true to scale. Rather, individual elements may be exaggeratedly large for better representability and/or better comprehensibility.
DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS
[0055] FIG. 1A shows a schematic representation of a top view of a wafer 90 with a plurality of optoelectronic semiconductor devices 1 in a first step of its manufacturing. The wafer 90 comprises a growth substrate 900, in particular sapphire. The wafer 90 further comprises a plurality of first contact structures 810 as well as a plurality of second regions 102. The first contact structures 810 are formed, for example, with a metal or a metal alloy and serve for electrical contacting of the optoelectronic semiconductor device 1. The second regions 102 have a second conductive type and are preferably epitaxially grown.
[0056] FIG. 1B shows a schematic cross-section through an optoelectronic semiconductor device 1 according to the first exemplary embodiment. The sectional view of an optoelectronic semiconductor device 1 shown here corresponds to a cut through the wafer 90, shown in FIG. 1A, along the cutting line A. The optoelectronic semiconductor device 1 comprises a first contact structure 810, a second region 102, an active region 103 and a first region 101, which together are associated with a semiconductor body 10. The regions of the semiconductor body 10 are preferably epitaxially grown on the growth substrate 900. The first region 101 has a first conductive type, the second region 102 has a second conductive type, and the active region 103 is designed for generating electromagnetic radiation.
[0057] FIG. 2A shows a mask layer 50 applied to the side of the second region 102 and the first contact structures 810 facing away from the active region 103. For structuring, a number of recesses have been made in the mask layer 52.
[0058] FIG. 2B shows a schematic cross-section through an optoelectronic semiconductor device 1 according to the first exemplary embodiment. The sectional view of an optoelectronic semiconductor device 1 shown here corresponds to a cut through the wafer 90, shown in FIG. 2A, along the cutting line A. In this further method step, a mask 50 is applied to the upper side of the optoelectronic semiconductor device 1. The mask 50 has a plurality of recesses in the mask layer 52, which defines the region of the optoelectronic semiconductor device 1 to be processed further and protects the regions not to be processed.
[0059] FIG. 3A shows the position of trench-shaped recesses 40, which are generated by means of a plasma etching process. The etching process generates an etching of the semiconductor body 10 at the locations of the recesses in the mask layer 52.
[0060] FIG. 3B shows a schematic cross-section through an optoelectronic semiconductor device i according to the first exemplary embodiment. The sectional view of an optoelectronic semiconductor device 1 shown here corresponds to a cut through the wafer 90, shown in FIG. 3A, along the cutting line A. A plurality of recesses 40 are introduced in the optoelectronic semiconductor device 1. This can be done, for example, by a plasma etching process or another dry chemical etching process. The recesses 40 completely penetrate the second region 102 and the active region 103. This results in irregularities and damaged regions 200 to the surface of the side walls of the recesses 40. To remove this damaged regions 200, a further etching process follows within the recesses 40. One of the following wet chemical etching agents can be used: KOH, NaOH, NH.sub.4OH, LiOH, TMAH, NMP. The mask layer 50 is then removed.
[0061] FIG. 4A schematically shows an ion cleaning process on the side walls of the recesses 40, by means of which etching residues and other foreign materials are removed.
[0062] FIG. 4B shows a schematic cross-section through an optoelectronic semiconductor device 1 according to the first exemplary embodiment. The sectional view of an optoelectronic semiconductor device 1 shown here corresponds to a cut through the wafer 90 shown in FIG. 4A along cutting line A. The ion cleaning is, for example, carried out by means of nitrogen ions, argon ions, hydrogen plasma, oxygen plasma or xenon ions of low kinetic energy. This allows etching residues or other foreign materials to be removed from the side surfaces of the recesses 40 in order to obtain the cleanest possible facet surface.
[0063] FIG. 5A shows a passivation 60 applied to the side surfaces of the recesses 40 by means of a coating process.
[0064] FIG. 5B shows a schematic cross-section through an optoelectronic semiconductor device 1 according to the first exemplary embodiment. The sectional view of an optoelectronic semiconductor device 1 shown here corresponds to a cut through the wafer 90 shown in FIG. 5A along the cutting line A. The side faces of the recesses 40 are coated with a semi-crystalline material such as aluminum nitride, silicon, aluminum oxynitride, silicon oxynitride, aluminum oxide, gallium nitride, zinc selenide, gallium arsenide, gallium phosphide, silicon nitride or another ternary or quaternary compound to form a passivation 60. The passivation 60 prevents damage to the active region 103 or the first region 101 or the second region 102 from external environmental influences such as moisture.
[0065] FIG. 6A shows a mirror layer 70 which is applied to the side surfaces of the recesses 40 by means of a further coating process.
[0066] FIG. 6B shows a schematic cross-section through an optoelectronic semiconductor device 1 according to the first exemplary embodiment. The sectional view of an optoelectronic semiconductor device 1 shown here corresponds to a cut through the wafer 90 shown in FIG. 6A along cutting line A. A mirror layer 70 is applied to the passivation layer 60 inside the recesses 40. The mirror layer 70, for example, comprises a metal layer or one or more layers of one or more dielectrics. The mirror layer 70 may contain or be formed from silicon nitride, aluminum oxide, aluminum oxynitride, tantalum oxide, silicon dioxide or silicon. The mirror layer 70 is applied, for example, by sputtering, vapor deposition, CVD or an ALD process. By applying the mirror layer 70, a defined reflectivity of the coupling-out surface 20 and the rear surface 30 of the optoelectronic semiconductor device 1 can be achieved.
[0067] FIGS. 1A, 2A, 3A, 4A, 5A, and 6A each show a top view of a wafer 90 at different steps of the fabrication method for a plurality of optoelectronic semiconductor devices 1. In particular, it can be seen that all the method steps shown here can be carried out advantageously in a wafer composite. The structuring of the wafer is carried out by inserting a plurality of recesses 40 in the form of trenches. Further processing, which includes polishing the side surfaces of the trenches as well as passivation and subsequent coating of the side surfaces of the trenches, can also be carried out in the wafer composite. This simplifies production and reduces the cost per device produced.
[0068] FIG. 7 shows a schematic cross-section through an optoelectronic semiconductor device 1 according to the first exemplary embodiment. The optoelectronic semiconductor device 1 comprises a semiconductor body 10 having a second region 102, an active region 103 and a first region 101. A first contact structure 810 is arranged on the side of the second region 102 facing away from the active region 103. A second contact structure 820 is arranged on the side of the first region 101 facing away from the active region 103. The first contact structure 810 and the second contact structure 820, for example, are formed with a metal such as gold and are intended for the electrical connection of the semiconductor body 10. At the end surfaces of the semiconductor body 10 a coupling-out surface 20 and a rear surface 30 are attached. The coupling-out surface 20 is arranged plane-parallel to the rear surface 30 and serves the coupling-out of electromagnetic radiation E generated in the active region 103. On the coupling-out surface 20 as well as on the rear surface 30 a layer sequence of passivation 60 and mirror layer 70 is applied.
[0069] The first region 101 is structured according to the formula b.sub.n<[(h.sub.n-a-w)/tan(α/2)]−(b.sub.n-1-b.sub.n-2- . . . -b.sub.2-b.sub.1). In this concrete example with two steps 1011, the width b.sub.1 of the first step 1011 is now b.sub.1<(h.sub.1-a-w)/tan(α/2) and the width b.sub.2 of the second step 1011 is b.sub.2<[(h.sub.2-a-w)/tan(α/2)]−b.sub.1 according to this formula. The variable a denotes the distance of the active region 103 from the side of the second region 102 remote from the active region 103; the variable h.sub.1 denotes the first etch depth of the recess 40 measured from the side of the second region 102 remote from the active region 103; the variable h.sub.2 denotes the second etch depth of another recess measured from the side of the second region 102 remote from the active region 103. The variable w denotes the thickness of a waveguide region within the first region 101 adjacent to the active region 103. The waveguide region is used for the optical guidance of the electromagnetic radiation generated in the active region 103. The variable a denotes the vertical far field angle of the electromagnetic radiation E emitted from the coupling-out surface 20. If the two steps 1011 are structured according to the above formula, a shadowing of the emitted electromagnetic radiation E by the material of the first region 101 is avoided and the electromagnetic radiation E can leave the optoelectronic semiconductor device 1 particularly unhindered.
[0070] FIG. 8A shows a schematic side view of an optoelectronic semiconductor device 1 according to the first exemplary embodiment. In contrast to the exemplary embodiment shown in FIG. 7, the exemplary embodiment shown here has only one step 1011.
[0071] FIG. 8B shows a schematic top view of an optoelectronic semiconductor device 1 according to the first exemplary embodiment. In the plan view, the small extension of the second region 102, which does not extend over the entire width of the semiconductor body 10, is obvious. This serves in particular to limit the active region 103 located below the second region 102. This limits the expansion of the electromagnetic radiation emitted in the active region 103, which improves the beam quality advantageously.
[0072] FIG. 8C shows a schematic frontal view of an optoelectronic semiconductor device 1 according to the first exemplary embodiment. The frontal view shown in FIG. 8C shows the coupling-out surface 20 of an optoelectronic semiconductor device 1. Electrical contact is made via the first contact structure 810 and a second contact structure 820 arranged on the opposite side of the first contact structure 810. Electromagnetic radiation E is coupled out in a narrowly defined region.
[0073] FIG. 9A shows a schematic side view of an optoelectronic semiconductor device 1 according to the second exemplary embodiment. The second exemplary embodiment essentially corresponds to the first exemplary embodiment and differs only in the type of electrical contacting. The second contact structure 820 is arranged on another level, next to the first contact element 810. The optoelectronic semiconductor device 1 shown here is therefore suitable for mounting on an electrically non-conductive substrate, for example.
[0074] FIG. 9B shows a schematic top view of an optoelectronic semiconductor device 1 according to the second exemplary embodiment. The electrical contacting is realized by the first contact structure 810 and the second contact structure 820 arranged next to it.
[0075] FIG. 10 shows an optoelectronic semiconductor device 1 according to the third exemplary embodiment. The optoelectronic semiconductor device 1 shown here comprises a plurality of recesses 40 arranged on the rear surface 30 opposite the coupling-out surface 20 and forming a mirror 701. Each of the recesses 40 is provided with a passivation layer 60 and a mirror layer 70. The mirror 701 comprises a so-called DBR structure. This DBR structure is characterized in particular by spectrally selective reflectivity and very high reflectivity. The recesses 40 generate a periodic sequence of refractive index variations through the transition between the material of the semiconductor body 10 and the recesses 40. The DBR mirror is incorporated directly into the semiconductor body 10. The recesses 40 can be filled with a BCB or another transparent polymer or dielectric, in particular for increased mechanical stability and/or to adjust the refractive index. The first region 101 has a step 1011 at the coupling-out surface 20 in the longitudinal direction X.
[0076] FIG. 11 shows an optoelectronic semiconductor device 1 according to the fourth exemplary embodiment. The fourth exemplary embodiment essentially corresponds to the third exemplary embodiment and additionally has a further mirror 702 on the coupling-out surface 20 of the optoelectronic semiconductor device 1. This additional mirror 702 is also designed as a DBR structure and has a plurality of recesses 40, each with a passivation 60 and a mirror layer 70. The second mirror 702 is inserted directly into the semiconductor body 10. The different refractive index of the semiconductor material of the semiconductor body 10 and the material in the recesses 40 allows a periodic variation of the refractive index and thus the construction of a DBR mirror. This also applies to recesses 40 only filled with air. The first region 101 has a step 1011 on the coupling-out surface 20 in the longitudinal direction X.
[0077] FIG. 12 shows a plurality of optoelectronic semiconductor devices 1 which are combined in a monolithic structure to form a bar. Monolithic means that the optoelectronic semiconductor devices 1 shown here are grown on a common growth substrate 900 and interconnected by the growth substrate 900 and/or epitaxially produced semiconductor layers. The manufacture of a bar comprising a plurality of optoelectronic semiconductor devices 1 can be advantageously direct and the assembly of several previously isolated optoelectronic semiconductor devices 1 can be advantageously omitted.
[0078] The invention is not limited by the description of the exemplary embodiments. Rather, the invention includes any new feature and any combination of features, which in particular includes any combination of features in the patent claims, even if that feature or combination itself is not explicitly mentioned in the patent claims or exemplary embodiments.
