Multi-channel inverter for a photovoltaic apparatus

Abstract

An inverter for a photovoltaic apparatus, which includes a DC section, a DC/AC conversion section, an AC section and a control section. The DC section includes a plurality of DC input channels each including a DC/DC converter electrically connected between input terminals and the output terminals of the DC input channels. The inverter includes a measuring circuit arrangement adapted to measure an isolation resistance of the photovoltaic strings electrically connected with the DC input channels, when the inverter operates in predefined test conditions.

Claims

1. An inverter for a photovoltaic apparatus, said inverter comprising a DC section, a DC/AC conversion section, an AC section and a control section, wherein said DC section includes a plurality of DC input channels, each DC input channel comprising: first and second input terminals adapted to be electrically connected with a corresponding photovoltaic string; first and second output terminals electrically connected with a third input terminal and a fourth input terminal of said DC/AC conversion section, respectively; a first electric line including said first input and output terminals and a second electric line including said second input and output terminals; a DC/DC converter electrically connected between said input terminals and said output terminals; wherein said DC section comprises a measuring circuit arrangement adapted to measure an isolation resistance of said photovoltaic strings, when said inverter operates in predefined test conditions, said measuring arrangement comprising: for each DC input channel, a switch circuit electrically connected with a common electric node operating at a different voltage potentials with respect to the third input terminal of said DC/AC conversion section, when said inverter operates in said test conditions and at least one of said switch circuits is in an interdiction state, said switch circuit being further electrically connected with: said first input terminal or an electric node of said first electric line that is short-circuited with said first input terminal, when said inverter operates in said test conditions; or said second input terminal or an electric node of said second electric line that is short-circuited with said second input terminal, when said inverter operates in said test conditions; a first detection circuit adapted to provide first detection signals indicative of a first voltage between the third input terminal of said DC/AC conversion section and the ground, when said inverter operates in said test conditions.

2. The inverter, according to claim 1, wherein said first detection circuit comprises a first resistive element and a switch electrically connected in series between the third input terminal of said DC/AC conversion section and the ground.

3. The inverter, according to claim 2, wherein said measuring circuit arrangement comprises a second detection circuit adapted to provide second detection signals indicative a second voltage between said common electric node and the fourth input terminal of said DC/AC conversion section, when said inverter operates in said test conditions.

4. The inverter, according to claim 3, wherein said second detection circuit comprises a second resistive element electrically connected in series between said common electric node and the fourth input terminal of said DC/AC conversion section and an operational circuit electrically connected in parallel with said second resistive element.

5. The inverter, according to claim 4, wherein said measuring circuit arrangement comprises, for each DC input channel, a third detection circuit adapted to provide third detection signals indicative of a third voltage between the first and second input terminals of said DC input channel, when said inverter operates in said test conditions.

6. The inverter, according to claim 5, wherein said third detection circuit comprises a resistive shunt electrically connected in parallel with the first and second input terminals of said DC input channel.

7. The inverter, according to claim 6, wherein said control section comprises first data processing means configured to carry out MPPT functionalities.

8. The inverter, according to claim 1, wherein said control section comprises second data processing means configured to carry out a test procedure adapted to test operating conditions of a switch circuit operatively associated with a DC input channel said test procedure operable to: command said inverter to take or maintain said predefined test conditions; select an input channel; command the switching circuit operatively associated with the selected input channel to switch in a conduction state; command the switching circuits operatively associated with input channels different from the selected input channel to switch in an interdiction state; receive said second detection signals including one or more first voltage values indicative of said second voltage; receive said third detection signals including one or more second voltage values indicative of said third voltage; compare said second voltage values with said third voltage values; determine a fault condition of the switching circuit operatively associated with the selected input channel, if a voltage difference value between said second and third second voltage values exceeds a given voltage threshold.

9. The inverter, according to claim 8, wherein said second data processing means are configured to carry out said test procedure for each DC input channel.

10. The inverter, according to claim 2, wherein said control section comprises third data processing means configured to carry out a measuring procedure to measure the isolation resistance of said photovoltaic strings, said detection procedure operable to: command said inverter to take or maintain said predefined test conditions; command the first switch of said first detection circuit to switch in an interdiction state; receive said first detection signals including one or more third voltage values indicative of said first voltage; command the first switch of said first detection circuit to switch in a conduction state; receive said first detection signals including one or more fourth voltage values indicative of said first voltage; calculate said isolation resistance value basing on said third and fourth voltage values.

11. The inverter, according to that claim 1, wherein said DC/DC converter has a two-level boost configuration.

12. A photovoltaic apparatus comprising an inverter, according to claim 1.

13. The inverter, according to claim 1, wherein said measuring circuit arrangement comprises a second detection circuit adapted to provide second detection signals indicative a second voltage between said common electric node and the fourth input terminal of said DC/AC conversion section, when said inverter operates in said test conditions.

14. The inverter, according to claim 13, wherein said second detection circuit comprises a second resistive element electrically connected in series between said common electric node and the fourth input terminal of said DC/AC conversion section and an operational circuit electrically connected in parallel with said second resistive element.

15. The inverter, according to claim 1, wherein said measuring circuit arrangement comprises, for each DC input channel, a third detection circuit adapted to provide third detection signals indicative of a third voltage between the first and second input terminals of said DC input channel, when said inverter operates in said test conditions.

16. The inverter, according to claim 15, wherein said third detection circuit comprises a resistive shunt electrically connected in parallel with the first and second input terminals of said DC input channel.

17. The inverter, according to claim 16, wherein said control section comprises first data processing means configured to carry out MPPT functionalities.

18. The inverter, according to claim 1, wherein said control section comprises first data processing means configured to carry out MPPT functionalities.

19. The inverter, according to claim 7, wherein said control section comprises second data processing means configured to carry out a test procedure-adapted to test operating conditions of a switch circuit operatively associated with a DC input channel, said test procedure operable to: command said inverter to take or maintain said predefined test conditions; select an input channel; command the switching circuit operatively associated with the selected input channel to switch in a conduction state; command the switching circuits operatively associated with input channels different from the selected input channel to switch in an interdiction state; receive said second detection signals including one or more first voltage values indicative of said second voltage; receive said third detection signals including one or more second voltage values indicative of said third voltage; compare said second voltage values with said third voltage values; determine a fault condition of the switching circuit operatively associated with the selected input channel, if a voltage difference value between said second and third second voltage values exceeds a given voltage threshold.

20. The inverter, according to claim 19, wherein said DC/DC converter has a two-level boost configuration.

Description

(1) Characteristics and advantages of the present invention will be more apparent with reference to the description given below and to the accompanying figures, provided purely for explanatory and non-limiting purposes, wherein:

(2) FIG. 1 schematically illustrates a photovoltaic apparatus including an inverter, according to the present invention;

(3) FIG. 2 schematically illustrates a partial view of a two-channel inverter, according to the present invention;

(4) FIG. 2A schematically illustrates a partial view of a multi-channel inverter, according to the present invention;

(5) FIGS. 3-6 schematically illustrate some aspects of the inverter, according to the present invention.

(6) With reference to the aforesaid figures, the present invention relates to an inverter 1 for a low voltage photovoltaic apparatus 100.

(7) For the sake of clarity, it is specified that the term “low voltage” refers to operating voltages lower than 1 kV AC and 2 kV DC.

(8) Referring to FIG. 1, a photovoltaic apparatus 100 including the inverter 1 is shown. The photovoltaic apparatus 100 comprises one or more photovoltaic strings 200, each of which may comprise one or more photovoltaic panels.

(9) The photovoltaic strings 200 are electrically connected with the inverter 1 that in turns is electrically connected with an electric power distribution grid 300 (e.g. the mains or a load circuit).

(10) In general, the inverter 1 is adapted to receive DC electric power from the photovoltaic strings, to convert said DC electric power into AC electric power and to provide said Ac electric power to the electric power distribution grid.

(11) The inverter 1 comprises a DC section 1A, an DC/AC conversion section 1B and an AC section 1C.

(12) The DC section 1A includes a DC bus electrically connected with the photovoltaic strings 200 to receive DC electric power from these latter.

(13) According to the invention, the inverter 1 is of the multi-channel type.

(14) The DC section 1A thus comprises a DC bus formed by a plurality of DC input channels CH.sub.1, CH.sub.2, CH.sub.N, each of which has an input port adapted to be electrically connected with a corresponding photovoltaic string 200 and an output port electrically connected with the DC/AC conversion section 1B.

(15) The DC/AC conversion section 1B is electrically connected between the DC section 1A and the AC section 1C.

(16) Conveniently, the DC/AC conversion section 1B comprises an input port (also referred to as “DC-link”) electrically connected in parallel with all the output ports of the DC input channels CH.sub.1, CH.sub.2, CH.sub.N of the DC section 1A and an output port electrically connected with the AC section 1C

(17) Preferably, the DC/AC conversion section 1B comprises one or more DC/AC converters adapted to provide a DC/AC conversion of DC electric power provided by the photovoltaic strings 200 into AC electric power.

(18) The AC section 1C of the inverter 1 is electrically connected with the DC/AC conversion section 1B and the electric power distribution grid 300.

(19) Preferably, the AC section 1C comprises an input port electrically connected with the output port of the DC/AC conversion section 1B and a suitable AC bus adapted to deliver the AC electric power provided by the DC/AC conversion section 1B to the electric power distribution grid 300.

(20) In general, the DC/AC conversion section 1B and the AC section 1C of the inverter 1 may be of known type and will not be further described in further details for the sake of brevity.

(21) In FIG. 2, an embodiment of the inverter 1 having two DC input channels CH.sub.1, CH.sub.2 is shown while, in FIG. 2A, an embodiment of the inverter 1 having a generic number of N (N>2) DC input channels CH.sub.1, CH.sub.2, CH.sub.N is shown.

(22) Each DC input channel CH.sub.1, CH.sub.2, CH.sub.N comprises an input port formed by a first input terminal IT+ (e.g. having a positive voltage polarity) and a second input terminal IT− (e.g. having a negative voltage polarity) electrically coupleable with output terminals of a corresponding photovoltaic string 200.

(23) Each DC input channel CH.sub.1, CH.sub.2, CH.sub.N comprises an output port formed by a first output terminal OT+ (e.g. having a positive voltage polarity) and a second output terminal OT− (e.g. having a negative voltage polarity).

(24) The output terminals OT+ and OT− of each DC input channel CH.sub.1, CH.sub.2, CH.sub.N are electrically coupled respectively with third and fourth input terminals T+ and T− (e.g. having a positive and negative voltage polarity, respectively) of the DC/AC conversion section 1B, which form the input port of this latter section of the inverter 1. In this way, the output ports of the DC input channels CH.sub.1, CH.sub.2, CH.sub.N are electrically connected in parallel with the input port of the DC/AC conversion section 1B.

(25) Each DC input channel CH.sub.1, CH.sub.2, CH.sub.N comprises a first electric line L+ (e.g. having a positive voltage polarity) between and including the first input and output terminals IT+ and OT+ and a second electric line L− (e.g. having a negative voltage polarity) between and including the second input and output terminals IT− and OT−.

(26) According to the invention, the DC section 1A comprises a DC/DC converter CV.sub.1, CV.sub.2, CV.sub.N for each DC input channel CH.sub.1, CH.sub.2, CH.sub.N.

(27) Each DC/DC converter CV.sub.1, CV.sub.2, CV.sub.N is electrically connected between the input terminals IT+, IT− and the output terminals OT+, OT− of the corresponding DC input channel CH.sub.1, CH.sub.2, CH.sub.N.

(28) Each DC/DC converter CV.sub.1, CV.sub.2, CV.sub.N comprises one or more first components electrically connected in series with the first input and output terminals IT+, OT+ of the corresponding DC input channel CH.sub.1, CH.sub.2, CH.sub.N and are part of the first electric line L+ of said DC input channel. Each DC/DC converter CV.sub.1, CV.sub.2, CV.sub.N comprises one or more second components electrically connected in series with the second input and output terminals IT−, OT− of the corresponding DC input channel CH.sub.1, CH.sub.2, CH.sub.N and are part of the second electric line L− of said DC input channel.

(29) According to some embodiments of the invention, said first components may include at least a diode arranged in such a way to allow the circulation of a current along the first electric line L+ with a flow direction going from the first input terminal IT+ to the first output terminal OT+ and/or said second components may include at least a diode arranged in such a way to allow the circulation of a current along the second electric line L− with a flow direction going from the second output terminal OT− to the second input terminal IT−.

(30) Preferably, as shown in FIGS. 2 and 2A, each DC/DC converter CV.sub.1, CV.sub.2, CV.sub.N has a so-called “two-level boost configuration”.

(31) In the embodiments of FIGS. 2 and 2A, each DC/DC converter CV.sub.1, CV.sub.2, CV.sub.N comprises a first inductance L1 and a first diode D1 arranged along the first electric line L+ of the corresponding DC input channel CH.sub.1, CH.sub.2, CH.sub.N.

(32) The first inductance L1 is electrically connected between the first input terminal IT+ and a first intermediate node N1 of the first electric line L+ whereas the first diode D1 has its anode electrically connected with the first intermediate node N1 and its cathode electrically connected with the first output terminal OT+.

(33) In the embodiments of FIGS. 2 and 2A, each DC/DC converter CV.sub.1, CV.sub.2, CV.sub.N comprises a second inductance L2 and a second diode D2 arranged along the second electric line L− of the corresponding DC input channel CH.sub.1, CH.sub.2, CH.sub.N.

(34) The second inductance L2 is electrically connected between the second input terminal IT− and a second intermediate node N2 of the second electric line L− whereas the second diode D2 has its cathode electrically connected between the second intermediate node N2 and its anode electrically connected with the second output terminal OT−.

(35) In the embodiments of FIGS. 2 and 2A, each DC/DC converter CV.sub.1, CV.sub.2, CV.sub.N further comprises an input capacitance C0 electrically connected in parallel with the input terminals IT+, IT− of the corresponding DC input channel CH.sub.1, CH.sub.2, CH.sub.N, a first switch S1 electrically connected between the first intermediate node N1 and a third intermediate node N3, a first output capacitance C1 electrically connected between the first output terminal OT+ and the third intermediate node N3, a second switch S2 electrically connected between the second intermediate node N2 and the third intermediate node N3 and a second output capacitance C2 electrically connected between the second output terminal OT− and the third intermediate node N3.

(36) The first and second switches S1 and S2 (e.g. MOSFETs) of each DC/DC converter CV.sub.1, CV.sub.2, CV.sub.N generally operate in response to first control signals (not shown) received in input.

(37) In the embodiments of FIGS. 2 and 2A, the third intermediate nodes N3 of the DC/DC converters CV.sub.1, CV.sub.2, CV.sub.N of all the DC input channels CH.sub.1, CH.sub.2, CH.sub.N are electrically connected one with another in such a way to be equipotential.

(38) As it may be noticed, in the embodiments of FIGS. 2 and 2A, the first diode D1 and the first inductance L1 therefore constitute the above-mentioned first components of the DC/DC converter CV.sub.1, CV.sub.2, CV.sub.N, which are electrically connected in series with the first input and output terminals IT+, OT+ of the corresponding DC input channel CH.sub.1, CH.sub.2, CH.sub.N along the first electric line L+ of said DC input channel.

(39) On the other hand, the second diode D2 and the second inductance L2 constitute the above-mentioned second components of the DC/DC converter CV.sub.1, CV.sub.2, CV.sub.N, which are electrically connected in series with the second input and output terminals IT−, OT− of the corresponding DC input channel CH.sub.1, CH.sub.2, CH.sub.N along the second electric line L− of said DC input channel.

(40) According to the invention, the DC section 1A of the inverter 1 comprises a measuring circuit arrangement for measuring the isolation resistance R.sub.ISO of the photovoltaic strings 200, when said inverter operates at predefined test conditions.

(41) For the sake of clarity, it is specified that the term “isolation resistance” identifies the overall resistive impedance R.sub.ISO towards ground of the photovoltaic strings 200, which is substantially given by the parallel of the single resistive components R.sub.1, R.sub.2 R.sub.N of the impedances towards ground of the single photovoltaic strings 200.

(42) For the sake of clarity, it is specified that, when it operates under said predefined test conditions, the inverter 1 carries out no power conversion functionalities.

(43) Thus, when the inverter 1 operates under said predefined test conditions: each DC/DC converter CV.sub.1, CV.sub.2, CV.sub.N of the DC section 1A is deactivated and has its active elements (switches S1 and S2) in an interdiction state; the DC/AC converters of the DC/AC conversion section 1B are deactivated and have their active elements (switches) in an interdiction state; a DC current, which is fed by the corresponding photovoltaic string 200, may flow along the first and second electric lines L+ and L− of each DC input channel CH.sub.1, CH.sub.2, CH.sub.N.

(44) As it may be noticed, in the embodiments of FIGS. 2 and 2A, when inverter 1 operates under said test conditions, a DC current may flow along the electric line L+ and L− of the corresponding DC input channel CH.sub.1, CH.sub.2, CH.sub.N only.

(45) The switches S1 and S2 of each DC/DC converter CV.sub.1, CV.sub.2, CV.sub.N are in an interdiction state and are equivalent to open circuits.

(46) The first intermediate node N1 of the first electric line L+ is substantially equipotential (namely short-circuited, apart the presence of possible parasitic resistances) with the first input terminal IT+ whereas the second intermediate node N2 of the second electric line L− is substantially equipotential (namely short-circuited, apart the presence of possible parasitic resistances) with the second input terminal IT−. The first and second inductances L1, L2 are substantially equivalent to short-circuits as their impedance is virtually null for very low or null operating frequencies.

(47) No DC currents flow along the input capacitance C0 and the output capacitances C1 and C2. These latter which are substantially equivalent to open circuits as their impedance is virtually infinite for very low or null operating frequencies.

(48) According to the invention, the above-mentioned measuring circuit arrangement comprises a switch circuit SW.sub.1, SW.sub.2, SW.sub.N for each DC input channel CH.sub.1, CH.sub.2, CH.sub.N.

(49) Each switch circuit SW.sub.1, SW.sub.2, SW.sub.N is electrically connected with a common electric node NO that conveniently operates a different voltage potentials with respect to the third input terminal T+ of the DC/AC conversion section 1B, when the inverter 1 operates in the above-mentioned predefined test conditions and at least one of said switch circuits is in an interdiction state.

(50) In practice, each switch circuit SW.sub.1, SW.sub.2, SW.sub.N is electrically connected with a common node NO that is not electrically connected in a direct matter with the third input terminal T+ of the DC/AC conversion section 1B so as to be equipotential with said third input terminal and at least one of said switch circuits is in an interdiction state.

(51) This solution is quite advantageous as it allows substantially improving the accuracy of the isolation resistance measurements, which may otherwise be affected by relevant errors, if the common node was always equipotential with the third input terminal T+ of the DC/AC conversion section 1B, as it occurs in some known solutions of the state of the art.

(52) According to some embodiments of the invention, each switch circuit SW.sub.1, SW.sub.2, SW.sub.N is electrically connected with the first input terminal IT+ of the corresponding DC input channel CH.sub.1, CH.sub.2, CH.sub.N or with an electric node (e.g. the first intermediate electric node N1) of the first electric line L+ of the corresponding DC input channel CH.sub.1, CH.sub.2, CH.sub.N. Said electric node N1 is short-circuited (apart the presence of possible parasitic resistances) with the first input terminal IT+, when the inverter 1 operates at the above-mentioned test conditions.

(53) According to alternative embodiments of the invention, each switch circuit SW.sub.1, SW.sub.2, SW.sub.N is electrically connected with the second input terminal IT− of the corresponding DC input channel CH.sub.1, CH.sub.2, CH.sub.N or with an electric node (e.g. the second intermediate electric node N2) of the second electric line L− of the corresponding DC input channel CH.sub.1, CH.sub.2, CH.sub.N. Said electric node N2 is short-circuited (apart the presence of possible parasitic resistances) with the first input terminal IT−, when the inverter 1 operates at the above-mentioned test conditions.

(54) Preferably, each switch circuit SW.sub.1, SW.sub.2, SW.sub.N comprises a first resistive element R.sub.S and a third switch S.sub.SW (e.g. a MOSFET) electrically connected in series between the first input terminal IT+ and the common electric node NO (FIG. 3).

(55) Preferably, each switch circuit SW.sub.1, SW.sub.2, SW.sub.N comprises a first driving circuit DV.sub.SW to suitably drive the third switch S.sub.SW in response to second control signals C.sub.SW received in input.

(56) According to the invention, the above-mentioned measuring circuit arrangement comprises a first detection circuit 10.

(57) The first detection circuit 10 is adapted to provide first detection signals D1 indicative of a first voltage V.sub.ISO between the third input terminal T+ of the DC/AC conversion section 1B and the ground, when the inverter 1 operates at the above-mentioned test conditions (FIGS. 2, 2A, 4).

(58) As it may be easily understood, the first voltage V.sub.ISO is indicative of the voltage difference between the operative voltage of the third input terminal T+ and the ground voltage, when the inverter 1 operates at the above-mentioned test conditions.

(59) Preferably, the first detection circuit 10 comprises a first resistive element Rio and a fourth switch S.sub.10 (e.g. a MOSFET) electrically connected in series between the third input terminal T+ and the ground.

(60) Preferably, the first detection circuit 10 comprises a second driving circuit DV.sub.10 to suitably drive the fourth switch S.sub.10 in response to third control signals C.sub.10 received in input.

(61) Preferably, the first detection circuit 10 further comprises a first detection output Mio, at which it makes available the first detection signals D1.

(62) As it will better emerge from the following, the arrangement of the first detection circuit 10 is essential to measure the isolation resistance R.sub.ISO of the photovoltaic strings 200.

(63) Preferably, the above-mentioned measuring circuit arrangement comprises a second detection circuit 20 adapted to provide second detection signals D2 indicative a second voltage V.sub.TEST between the common electric node NO and the fourth input terminal T− of the DC/AC conversion section 1B, when the inverter 1 operates at the above-mentioned test conditions (FIGS. 2, 2A, 6).

(64) As it may be easily understood, the second voltage V.sub.TEST is indicative of the voltage difference between the operating voltage of the common electric node NO and the operating voltage of the fourth input terminal T−, when the inverter 1 operates in the above-mentioned test conditions.

(65) Preferably, the second detection circuit 20 comprises a second resistive element R.sub.20 electrically connected in series between the common electric node NO and the fourth input terminal T− and an operational circuit OP electrically connected in parallel with the second resistive element R.sub.20 (FIG. 6).

(66) Preferably, the operational circuit OP comprises an operational amplifier and a suitable polarization circuit CP electrically connected with the fourth input terminal T− to suitably drive said operational amplifier.

(67) Preferably, the second detection circuit 20 comprises a second detection output M.sub.20, at which it makes available the second detection signals D2.

(68) Preferably, the above-mentioned measuring circuit arrangement comprises a third detection circuit 30 for each DC input channel CH.sub.1, CH.sub.2, CH.sub.N.

(69) Each third detection circuit 30 is adapted to provide third detection signals D3 indicative of a third voltage V.sub.IN between the first and second input terminals IT+, IT− of the corresponding DC input channel CH.sub.1, CH.sub.2, CH.sub.N, when the inverter 1 operates in the above-mentioned test conditions.

(70) As it may be easily understood, the third voltage V.sub.IN is indicative of the voltage difference between the operating voltages of the first and second input terminals IT+, IT− of the corresponding DC input channel CH.sub.1, CH.sub.2, CH.sub.N, when the inverter 1 operates in the above-mentioned test conditions.

(71) Preferably, each third detection circuit 30 is comprises a resistive shunt R.sub.30 electrically connected in parallel with the first and second input terminals IT+, IT− of the corresponding DC input channel CH.sub.1, CH.sub.2, CH.sub.N (FIG. 5).

(72) Preferably, each third detection circuit 30 comprises a third detection output M.sub.30, at which it makes available the third detection signals D3.

(73) As it will better emerge from the following, the arrangement of the second and third detection circuits 20, 30 is quite important to check the operating status of each switching circuit SW.sub.1, SW.sub.2, SW.sub.N, preferably before carrying out a measurement of the isolation resistance R.sub.ISO of the photovoltaic strings 200.

(74) According to the invention, the inverter 1 comprises a control section 1D operatively associated with the DC section 1A, the DC/AC conversion section 1B and the AC section 1C to control the operation of these latter.

(75) The control section 1D may include one or more control boards or units, each of which may include one or more digital processing devices (e.g. microcontrollers, DSPs, and the like) and suitable electronic circuits of digital or analog type.

(76) Conveniently, the control section 1D comprises suitable data processing means to carry out its functionalities, some of which (the first, second and third processing means 51, 52, 53) will be better described in the following.

(77) If implemented in a digital manner, said data processing means may comprise suitably arranged software instructions stored in a medium and executable by one or more digital processing devices of the control section 1D to perform said functionalities.

(78) If implemented in analog manner, said data processing means may comprise electronic circuits suitably arranged to perform said functionalities.

(79) Additional variant solutions to implement said data processing means are available to the skilled person.

(80) Preferably, the control section 1D is operatively coupled with the first and second switches S1, S2 of each DC/DC converter CV.sub.1, CV.sub.2, CV.sub.N and it is capable to provide first control signals (not shown) to control the operation of these latter switches.

(81) Conveniently, the control section 1D is operatively coupled with each switch circuit SW.sub.1, SW.sub.2, SW.sub.N and it is capable to provide second control signals C.sub.SW to control the operation of the third switch S.sub.SW of each switch circuit SW.sub.1, SW.sub.2, SW.sub.N.

(82) Conveniently, the control section 1D is operatively coupled with the above-mentioned first detection circuit 10 (namely with the first detection output Mio and second driving circuit DV.sub.10 thereof) to receive the first detection signals D1 and to provide third control signals C.sub.10 to control the operation of the fourth switch S.sub.10.

(83) Preferably, the control section 1D is operatively coupled with the above-mentioned second detection circuit 20 (namely with the second detection output M.sub.20 thereof) to receive the second detection signals D1.

(84) Preferably, the control section 1D is operatively coupled with the above-mentioned third detection circuit 30 (namely with the third detection output M.sub.30 thereof) to receive the third detection signals D3.

(85) Preferably, the control section 1D comprises first data processing means 51 adapted to carry out MPPT (Maximum Power Point Tracking) functionalities by suitably controlling the DC/DC converters CV.sub.1, CV.sub.2, CV.sub.N of the input channels CH.sub.1, CH.sub.2, CH.sub.N and the DC/AC converters of the DC/AC conversion section 1B.

(86) In order to carry out said MPPT functionalities, the first data processing means 51 may implement algorithms or procedures of known type that will be not described in the following for the sake of brevity.

(87) Preferably, the control section 1D comprises second data processing means 52 configured to carry out a test procedure P.sub.T adapted to test the operating conditions of a switch circuit SW.sub.1, SW.sub.2, SW.sub.N operatively associated with a given DC input channel CH.sub.1, CH.sub.2, CH.sub.N of the DC section 1A.

(88) The test procedure P.sub.T will now be described in details in accordance to a preferred embodiment of the invention.

(89) The test procedure P.sub.T comprises a step of commanding the inverter 1 to take or maintain the above-mentioned predefined test conditions.

(90) In order to implement this step, the second data processing means conveniently provides suitable control signals to the switches S1, S2 of each DC/DC converter CV.sub.1, CV.sub.2, CV.sub.N and suitable control signals to the DC/AC converters of the DC/AC conversion section 1B to maintain said switches i an interdiction state.

(91) The test procedure P.sub.T then comprises the step of selecting an input channel (for example the input channel CH.sub.1—FIGS. 2, 2A).

(92) The test procedure P.sub.T then comprises the step of commanding the switching circuit SW.sub.1 operatively associated with the selected input channel CH.sub.1 to switch in a conduction state and the step of commanding the switching circuits SW.sub.2, SW.sub.N operatively associated with the input channels CH.sub.2, CH.sub.N different from the selected input channel CH.sub.1 to switch in an interdiction state.

(93) In order to implement this step, the second data processing means conveniently provides suitable control signals C.sub.SW to the driving circuits DV.sub.SW of the switching circuits SW.sub.1, SW.sub.2, SW.sub.N in such a way that the corresponding switches S.sub.SW are operated in an interdiction state or in a conduction state.

(94) Following the above-mentioned steps, the common node NO becomes substantially equipotential with the first input terminal IT+ of the selected DC input channel CH.sub.1 and its decoupled from the first input terminals IT+ of the remaining DC input channels CH.sub.2, CH.sub.N.

(95) The test procedure P.sub.T then comprises the step of receiving the second detection signals D2 from said the detection circuit 20 and the step of receiving the third detection signals D3 from said third detection circuit 30.

(96) The second detection signals D2 include one or more first voltage values V.sub.A indicative of the detected second voltage V.sub.TEST whereas the third detection signals D3 include one or more second voltage values V.sub.B indicative of the detected third voltage V.sub.IN.

(97) The test procedure P.sub.T then comprises the step of comparing the above-mentioned first and second voltage values V.sub.A, V.sub.B.

(98) As the common node NO is substantially equipotential with the first input terminal IT+ of the selected DC input channel CH.sub.1, the second and third voltages V.sub.TEST and V.sub.IN should have similar first and second voltage values V.sub.A, V.sub.B, if the switching circuit SW.sub.1 operatively associated with the selected input channel CH.sub.1 works properly. Otherwise, a substantial voltage difference between the first and second voltages V.sub.A, V.sub.B will be certainly present.

(99) The test procedure P.sub.T then comprises the step of determining a fault condition of the switching circuit SW.sub.1 operatively associated with the selected input channel CH.sub.1, if a voltage difference value between the second and third second voltages V.sub.TEST, V.sub.IN exceeds a given voltage threshold value V.sub.TH.

(100) In practice, a fault condition of the switching circuit SW.sub.1 operatively associated with the selected input channel CH.sub.1 is determined if the following condition occurs:
|V.sub.A−V.sub.B|>V.sub.TH
where V.sub.A is a first voltage value of the detected second voltage V.sub.TEST, V.sub.B is a second voltage value of the detected third voltage V.sub.IN and V.sub.TH is the above-mentioned threshold value.

(101) Preferably, the second data processing means 52 are configured to carry out the above-described test procedure P.sub.TEST for each DC input channel CH.sub.1, CH.sub.2, CH.sub.N.

(102) At each execution cycle of the test procedure P.sub.T, the second processing means 52 will conveniently select a different DC input channel CH.sub.1, CH.sub.2, CH.sub.N to check the actual operative status of the corresponding switching circuit SW.sub.1, SW.sub.2, SW.sub.N.

(103) It is evidenced that at each execution cycle of the test procedure P.sub.T, the common electric node NO always operates a different voltage potentials with respect to the third input terminal T+ of the DC/AC conversion section 1B, as N−1 switch circuits among the switching circuits switching circuit SW.sub.1, SW.sub.2, SW.sub.N are in an interdiction state.

(104) The above-mentioned test procedure P.sub.T allows testing the actual operating status of the switching circuits SW.sub.1, SW.sub.2, SW.sub.N operatively associated with the DC input channels CH.sub.1, CH.sub.2, CH.sub.N.

(105) Conveniently, the actual operating status of the switching circuits SW.sub.1, SW.sub.2, SW.sub.N may be checked by carrying above-mentioned test procedure P.sub.T before measuring the isolation resistance R.sub.ISO of the photovoltaic strings 200

(106) In this way, relevant measurement errors of the isolation resistance R.sub.ISO of the photovoltaic strings 200 may be preventively avoided with relevant advantages in terms of reliability and accuracy.

(107) Preferably, the control section 1D comprises third data processing means 53 configured to carry out a measuring procedure P.sub.M adapted to measure the isolation resistance R.sub.ISO of the photovoltaic strings 200.

(108) The measuring procedure P.sub.M will now be described in details in accordance to a preferred embodiment of the invention.

(109) The measuring procedure P.sub.M comprises a step of commanding the inverter 1 to take or maintain the above-mentioned predefined test conditions.

(110) In order to implement this step, the second data processing means conveniently provides suitable control signals to the switches S1, S2 of each DC/DC converter CV.sub.1, CV.sub.2, CV.sub.N and suitable control signals to the DC/AC converters of the DC/AC conversion section 1B to maintain said switches in an interdiction state.

(111) The measuring procedure P.sub.M comprises a step of commanding the first switch S.sub.10 of the first detection circuit 10 to switch in an interdiction state.

(112) In order to implement this step, the third data processing means 53 conveniently provides suitable control signals C.sub.10 to the driving circuits DV.sub.10 of the switch S.sub.10.

(113) The measuring procedure P.sub.M comprises a step of receiving the first detection signals D1 indicative of the first voltage V.sub.ISO. The first detection signals D1 include one or more third voltage values V.sub.C indicative of the detected first voltage V.sub.ISO.

(114) The measuring procedure P.sub.M then comprises a step of commanding the first switch S.sub.10 of the first detection circuit 10 to switch in a conduction state.

(115) In order to implement this step, the third data processing means 53 conveniently provides suitable control signals C.sub.10 to the driving circuits DV.sub.10 of the switch S.sub.10.

(116) The measuring procedure P.sub.M comprises a further step of receiving the first detection signals D1 indicative of the first voltage V.sub.ISO. The first detection signals D1 include one or more fourth voltage values V.sub.D indicative of the detected first voltage V.sub.ISO.

(117) The measuring procedure P.sub.M then comprises a step of calculating the isolation resistance R.sub.ISO of the photovoltaic strings 200 basing on the third and fourth voltage values V.sub.C, V.sub.D.

(118) In order to calculate the isolation resistance R.sub.ISO, the third processing means 53 may adopt known algorithms of know type.

(119) As an example, the isolation resistance R.sub.ISO may be calculated as:

(120) $R_{\mathrm{ISO}}=\frac{\left(\left(V_C-V_D\right)*R_{10}\right)}{V_D}$
where V.sub.C is a third voltage value of the detected first voltage V.sub.ISO with the switch S.sub.10 in interdiction state, V.sub.D is a third voltage value of the detected first voltage V.sub.ISO with the switch S.sub.10 in conduction state and Rio is the known resistance value of the first resistive element Rio of the first detection circuit 10.

(121) The measuring procedure P.sub.M allows measuring the isolation resistance of the photovoltaic strings 200 in a simple manner by carrying out subsequent measurements of a single circuit point (the third input terminal T+ of the DC/AC conversion section 1B) with respect to the ground.

(122) This constitutes an important advantages with respect to known MPPT inverters the state of the art where the voltages of multiple points of the DC section have to be measured to calculate the isolation resistance of the photovoltaic strings.

(123) The present invention allows achieving the intended aims and objects.

(124) The inverter 1 is provided with a measuring circuit arrangement that allows measuring the isolation resistance R.sub.ISO of the photovoltaic strings 200 in an accurate and reliable manner.

(125) The measuring circuit arrangement employed in the inverter 1 is particularly adapted for use in an inverters is capable of providing MPPT functionalities and having the DC input channels CH.sub.1, CN2, CH.sub.N without equipotential lines in common.

(126) The inverter 1 has a compact structure with a relatively small size. The above-mentioned measuring circuit arrangement may in fact be easily integrated in the DC section 1A and it may employ MOSFETs or equivalent switching devices for its practical implementation.

(127) The inverter 1 can be easily manufactured at industrial level with highly automated operations at competitive costs with respect to known solutions of the state of the art.