Amplification interface, and corresponding measurement system and method for calibrating an amplification interface

Abstract

An amplification interface includes a drain of a first FET connected to a first node, a drain of a second FET connected to a second node, and sources of the first and second FETs connected to a third node. First and second bias-current generators are connected to the first and second nodes. A third FET is connected between the third node and a reference voltage. A regulation circuit drives the gate of the third FET to regulate the common mode of the voltage at the first node and the voltage at the second node to a desired value. A current generator applies a correction current to the first and/or second node. A differential current integrator has a first and second inputs connected to the second and first nodes. The integrator supplies a voltage representing the integral of the difference between the currents received at the second and first inputs.

Claims

1. An amplification interface, comprising: a first field effect transistor (FET) having a drain terminal connected to a first node and a source terminal connected to a third node; a second FET having a drain terminal connected to a second node and a source terminal connected to the third node; a first bias current generator configured to apply a first bias current to said first node; a second bias current generator configured to apply a second bias current to said second node; a third FET having a drain terminal connected to said third node and a source terminal connected to a reference voltage; a regulation circuit configured to drive a gate terminal of said third FET in order to regulate a common mode voltage at said first node and a common mode voltage at said second node to a given value; at least one current generator configured to apply a correction current to one of said first node and said second node; and a differential current integrator comprising a first input terminal connected to said second node and a second input terminal connected to said first node, wherein said differential current integrator is configured to provide via two output terminals an output voltage indicative of an integral of a difference between a first output current received at said first input terminal of said differential current integrator from the second node and a second output current received at said second input terminal of said differential current integrator from the first node.

2. The amplification interface according to claim 1, wherein said regulation circuit is configured to drive said gate terminal of said third FET such that:
(V.sub.O1P+V.sub.O1N)/2=V.sub.CM1 where V.sub.O1P corresponds to the common mode voltage at said first node, V.sub.O1N corresponds to the common mode voltage at said second node, and V.sub.CM1 corresponds to said given value.

3. The amplification interface according to claim 1, wherein said differential current integrator comprises a differential operational amplifier comprising: a first capacitor connected between a first output terminal of said differential operational amplifier and the first input terminal; and a second capacitor connected between a second output terminal of said differential operational amplifier and the second input terminal.

4. The amplification interface according to claim 3, wherein said differential current integrator further comprises first and second electronic switches respectively connected in parallel with said first and second capacitors, wherein said first and second electronic switches are driven via a reset signal.

5. The amplification interface according to claim 4, further comprising a sample-and-hold circuit configured to: store said output voltage when a control signal has a first logic value, and maintain said output voltage when said control signal has a second logic value different than the first logic value.

6. The amplification interface according to claim 5, comprising a control circuit configured to: generate said reset signal, such that said differential current integrator is periodically reset during a reset interval and activated during a measurement interval; and during each measurement interval, set said control signal to said first logic value for a sampling interval and set said control signal to said second logic value for a hold interval.

7. The amplification interface according to claim 6, further comprising an RC oscillator having a capacitor and a resistor which define an oscillation period of said RC oscillator, and wherein said control circuit is configured to generate said control signal such that said sampling interval corresponds to a multiple of said oscillation period of said RC oscillator.

8. The amplification interface according to claim 1, wherein said first and second bias currents are proportional to absolute temperature (PTAT).

9. The amplification interface according to claim 1, wherein said first and said second FETs comprise n-channel MOS transistors.

10. The amplification interface according to claim 1, wherein said first and said second FETs are thermally isolated transistors, and wherein gate terminals of said first FET and said second FET are connected to a further reference voltage.

11. The amplification interface according to claim 1, wherein said at least one current generator comprises: a first current generator configured to apply a positive correction current to said first node in addition to the first bias current, and a second current generator configured to apply a negative correction current to said second node in addition to the second bias current.

12. The amplification interface according to claim 11, further comprising a first chopper circuit connected between the first and second input terminal of said differential current integrator, and said first and said second nodes.

13. The amplification interface according to claim 12, further comprising a second chopper circuit connected between said first current generator and said second current generator, and said first and said second nodes.

14. The amplification interface according to claim 13, further comprising a third chopper circuit connected between said two output terminals of said differential current integrator and two output terminals of said amplification interface.

15. The amplification interface according to claim 1, wherein the first and second FETs form an amplifier having a voltage offset and wherein the correction current compensates for said voltage offset.

16. A measurement system, comprising: an amplification interface, comprising: a first field effect transistor (FET) having a drain terminal connected to a first node and a source terminal connected to a third node; a second FET having a drain terminal connected to a second node and a source terminal connected to the third node; a first bias current generator configured to apply a first bias current to said first node; a second bias current generator configured to apply a second bias current to said second node; a third FET having a drain terminal connected to said third node and a source terminal connected to a reference voltage; a regulation circuit configured to drive a gate terminal of said third FET in order to regulate a common mode voltage at said first node and a common mode voltage at said second node to a given value; at least one current generator configured to apply a correction current to one of said first node and said second node; and a differential current integrator comprising a first input terminal connected to said second node and a second input terminal connected to said first node, wherein said differential current integrator is configured to provide via two output terminals an output voltage indicative of an integral of a difference between a first output current received at said first input terminal of said differential current integrator from the second node and a second output current received at said second input terminal of said differential current integrator from the first node; an analog-to-digital converter connected to the two output terminals of said differential current integrator of said amplification interface; and a processing circuit connected to an output of said analog-to-digital converter.

17. The measurement system according to claim 16, wherein said regulation circuit is configured to drive said gate terminal of said third FET such that:
(V.sub.O1P+V.sub.O1N)/2=V.sub.CM1. where V.sub.O1P corresponds to the common mode voltage at said first node, V.sub.O1N corresponds to the common mode voltage at said second node, and V.sub.CM1 corresponds to said given value.

18. The measurement system according to claim 16, wherein said differential current integrator comprises a differential operational amplifier comprising: a first capacitor connected between a first output terminal of said differential operational amplifier and the first input terminal; and a second capacitor connected between a second output terminal of said differential operational amplifier and the second input terminal.

19. The measurement system according to claim 18, wherein said differential current integrator further comprises first and second electronic switches respectively connected in parallel with said first and second capacitors, wherein said first and second electronic switches are driven via a reset signal.

20. The measurement system according to claim 18, wherein the first and second FETs form an amplifier having a voltage offset and wherein the correction current compensates for said voltage offset.

21. An amplification interface, comprising: first, second, and third nodes; a first field effect transistor (FET) having a drain connected to the first node and a source connected to the third node; a second FET having a drain terminal connected to the second node and a source connected to the third node; a first bias current generator having an output connected to the first node, the first bias current generator configured to apply a first bias current to the first node; a second bias current generator having an output connected to the second node, the second bias current generator configured to apply a second bias current to the second node; a third FET having a drain connected to the third node and a source connected to a reference voltage; a regulation circuit configured to drive a gate terminal of the third FET in order to regulate voltages at the first and second nodes to a given value; and at least one current generator configured to apply a correction current to the first node and/or the second node.

22. The amplification interface according to claim 21, wherein said regulation circuit is configured to drive said gate terminal of said third FET such that:
(V.sub.O1P+V.sub.O1N)/2=V.sub.CM1 where V.sub.O1P corresponds to the voltage at said first node, V.sub.O1N corresponds to the voltage at said second node, and V.sub.CM1 corresponds to said given value.

23. The amplification interface according to claim 21, wherein said first and said second FETs are thermally insulated transistors, and wherein gate terminals of said first FET and said second FET are connected to a further reference voltage.

24. The amplification interface according to claim 21, wherein said at least one current generator comprises: a first current generator configured to apply a positive correction current to said first node, and a second current generator configured to apply a negative correction current to said second node.

25. The amplification interface according to claim 21, wherein the first and second FETs form an amplifier having a voltage offset and wherein the correction current compensates for said voltage offset.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The embodiments of the present disclosure will now be described with reference to the annexed plates of drawings, which are provided purely to way of non-limiting example and in which:

(2) FIG. 1 shows a measurement system;

(3) FIG. 2 shows a first embodiment of an amplification interface;

(4) FIG. 3 shows an embodiment of operation of the amplification interface of FIG. 2;

(5) FIG. 4 shows a second embodiment of an amplification interface;

(6) FIG. 5 shows an embodiment of operation of the amplification interface of FIG. 4;

(7) FIG. 6 shows a third embodiment of an amplification interface;

(8) FIG. 7 shows a fourth embodiment of an amplification interface; and

(9) FIG. 8 shows a detail of the amplification interfaces of FIGS. 2, 4, 6, and 7.

DETAILED DESCRIPTION

(10) In the ensuing description, various specific details are illustrated aimed at enabling an in-depth understanding of the embodiments. The embodiments may be provided without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not shown or described in detail so that various aspects of the embodiments will not be obscured.

(11) Reference to “an embodiment” or “one embodiment” in the framework of this description is meant to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is comprised in at least one embodiment. Hence, phrases such as “in an embodiment”, “in one embodiment”, or the like that may be present in various points of this description do not necessarily refer to one and the same embodiment. Moreover, particular conformations, structures, or characteristics may be combined in any adequate way in one or more embodiments.

(12) The references used herein are only provided for convenience and hence do not define the sphere of protection or the scope of the embodiments.

(13) In FIGS. 2 to 7 described below, parts, elements or components that have already been described with reference to FIG. 1 are designated by the same references used previously in these figures. The description of these elements has already been made and will not be repeated in what follows in order not to burden the present detailed description.

(14) As explained previously, various embodiments of the present description regard an electronic amplification interface devised for “reading” the signal produced by TMOS sensors.

(15) FIG. 2 shows a first embodiment of a measurement system comprising a TMOS sensor 10, an electronic amplification interface, and an optional analog-to-digital converter 30.

(16) In particular, in the embodiment, the TMOS sensor 10 comprises two TMOS transistors M.sub.BLIND and M.sub.EXP. In the embodiment considered, these transistors are FETs (Field-Effect Transistors), for example of the n-channel type.

(17) In various embodiments, these two TMOS transistors are provided within one and the same integrated circuit/die and have the same characteristics, in particular with reference to sizing of the transistors; i.e., the transistor M.sub.BLIND is substantially a copy of the transistor M.sub.EXP. Preferably, the TMOS transistors M.sub.BLIND and M.sub.EXP are positioned in the proximity of one another.

(18) In the embodiment considered, the electronic amplification interface is configured for amplifying the differential signal between the two transistors, for example the differential signal between the drain terminals of the transistors M.sub.BLIND and M.sub.EXP. For example, as will be described hereinafter, this enables rejection of the common-mode signals and of disturbance that arrive at both of the transistors of the TMOS sensor.

(19) In the embodiment considered, the differential signal results from the fact that the TMOS transistor M.sub.EXP is “exposed”, i.e., it is configured for being exposed to the variation of temperature that the quantity to be measured produces thereon, whereas the other TMOS transistor M.sub.BLIND is “blind”, i.e., it is configured in such a way that the physical quantity that is to be measured does not produce any effect thereon.

(20) For example, in various embodiments, the quantity that is to be measured is the infrared radiation produced by an object set at a distance from the TMOS sensor 10. Infrared radiation is a function of the temperature of the object itself. Hence, the measurement of the infrared radiation emitted by an object enables an indirect measurement of the temperature of the object. In this case, the transistor M.sub.BLIND is hence shielded from the IR radiation, whereas the transistor M.sub.EXP is configured for receiving the IR radiation produced by the object. Consequently, the power of the IR radiation received by the transistor M.sub.EXP will cause slight heating of the transistor M.sub.EXP (and not of the transistor M.sub.BLIND). This difference in temperature hence generates a variation in the differential signal across the sensor 10 that the amplification interface should amplify. In fact, in general, a small variation in temperature of the transistor M.sub.EXP causes a small displacement within the I-V characteristic of the transistor M.sub.EXP, which in turn generates a small variation in the differential signal between the transistors M.sub.BLIND and M.sub.EXP.

(21) Consequently, in general, the variation of temperature of the transistor M.sub.EXP (and not of the transistor M.sub.BLIND) that the physical quantity to be measured (IR radiation, gas flow, etc.) produces results in a variation of the electrical characteristics of the transistor M.sub.EXP (and not of the transistor M.sub.BLIND), which in turn results in a variation of the differential signal that the amplification interface should amplify. Instead, the amplification interface may be configured in such a way that the common-mode variations on the transistors M.sub.EXP and M.sub.EXP (for example, the variation of the ambient temperature, and in general any common-mode disturbance) will not produce any variation of the differential signal and hence their effect is filtered/compensated.

(22) Even though the present description has been conceived and devised for amplifying as well as possible the signal generated by a TMOS sensor 10, the electronic amplification interface proposed is functional and suitable also in the case where, instead of the TMOS transistors, two MOS transistors are used, since the amplification interface is configured for amplifying a differential signal between two transistors, such as a differential signal on the drain terminals of two n-channel transistors.

(23) As explained previously, the electronic amplification interface may amplify the differential signal between the two transistors M.sub.BLIND and M.sub.EXP. To generate such a differential signal, a circuit which generates an appropriate biasing of the transistors M.sub.BLIND and M.sub.EXP is utilized.

(24) For example, in the embodiment considered, the electronic amplification interface comprises for this purpose two current generators 206 and 208. In particular, the current generator 206 is connected in series with the drain and source terminals of the transistor M.sub.BLIND, and the current generator 208 is connected in series with the drain and source terminals of the transistor M.sub.EXP.

(25) For instance, in the embodiment considered, the transistors M.sub.BLIND and M.sub.EXP are n-channel transistors. In this case, as also described in United States Patent Application Publication No. 2017/0205366, the current generator 206 may be connected (for example, directly) between the drain terminal of the transistor M.sub.BLIND and a reference voltage V.sub.DD, which, for example, corresponds to the supply voltage of the integrated circuit and/or of the processing circuit 40 shown in FIG. 1. Likewise, the current generator 208 may be connected (for example, directly) between the drain terminal of the transistor M.sub.EXP and the reference voltage V.sub.DD.

(26) In the embodiment considered, the gate terminal of the transistor M.sub.BLIND is connected (for example, directly) to the gate terminal of the transistor M.sub.EXP, which in turn is connected (for example, directly) to a reference voltage V.sub.CM2. In general, when instead of the TMOS transistors two normal transistors are used, the input signal may be applied between the gate terminals of the transistors M.sub.BLIND and M.sub.EXP.

(27) However, whereas according to the teachings of United States Patent Application Publication No. 2017/0205366 the source terminals of the transistors M.sub.BLIND and M.sub.EXP were directly connected to ground, the embodiment represented in FIG. 2 also comprises a common-mode control circuit. In particular, in the embodiment considered, the source terminal of the transistor M.sub.BLIND is connected (for example, directly) to the source terminal of the transistor M.sub.EXP, which in turn is connected (for example, directly) by means of a transistor M.sub.B to a reference voltage, for example, ground GND. Considering that, in the embodiment considered, the TMOS transistors are of the n-channel type, preferably also the transistor M.sub.B is of the n-channel type. In the embodiment considered, the drain terminal of the transistor M.sub.B is hence connected (for example, directly) to the source terminal of the transistor M.sub.BLIND/source terminal of the transistor M.sub.EXP, i.e., the terminal 106, and the source terminal of the transistor M.sub.B is connected (for example, directly) to the reference voltage/GND.

(28) Consequently, in the embodiment considered, the sensor 10 is connected to the amplification interface by three terminals: a terminal 102 that corresponds to the drain terminal of the transistor M.sub.BLIND; a terminal 104 that corresponds to the drain terminal of the transistor M.sub.EXP; and a terminal 106 that corresponds to the source terminals of the transistors M.sub.BLIND and M.sub.EXP.

(29) In various embodiments, each of the current generators 206 and 208 supplies a current I.sub.B. For example, the current generators 206 and 208 may be implemented with a current mirror. Consequently, in the embodiment considered, the bias current of the transistor M.sub.EXP and of the transistor M.sub.BLIND is substantially equal to IB, whereas the current of the transistor M.sub.B is substantially equal to 2.Math.I.sub.B.

(30) This part of the circuit hence basically corresponds to an OTA (Operational Transconductance Amplifier) as described, for example, in U.S. Pat. No. 6,693,485, the contents of which are incorporated herein by reference.

(31) However, in the embodiment considered, the gate terminal of the transistor M.sub.B is not driven by a constant signal, but by a control circuit 204. In particular, the aforesaid control circuit 204 is configured for monitoring the voltage V.sub.O1P on the drain terminal of the transistor M.sub.BLIND and the voltage V.sub.O1N on the drain terminal of the transistor M.sub.EXP, and for generating the driving signal for the gate terminal of the transistor M.sub.B as a function of these voltages. In particular, in the embodiment considered, the control circuit 204 is configured for controlling (by feedback of the voltages V.sub.O1P and V.sub.O1N) the voltage on the gate of the transistor M.sub.B so that the common mode of the voltages V.sub.O1P and V.sub.O1N will be equal to a reference voltage V.sub.CM1, i.e., the control circuit 204 is configured for regulating the gate-to-source voltage V.sub.GS of the transistor M.sub.B in such a way that:
(V.sub.O1P+V.sub.O1N)/2=V.sub.CM1

(32) For example, in various embodiments, the control circuit 204 may be implemented with a regulator that comprises at least one I (Integral) component and possibly a P (Proportional) component. For instance, the control circuit 204 may be implemented by one or more operational amplifiers.

(33) In various embodiments, the amplification interface is configured in such a way that the transistors M.sub.BLIND and M.sub.EXP are biased so as to work in the sub-threshold region. For example, once the bias current of the transistors M.sub.EXP and M.sub.BLIND has been fixed equal to I.sub.B, these transistors can be sized with a (width-to-length W/L) ratio sufficiently high to help guarantee that the voltage between the gate and source terminals V.sub.GS will be lower than the threshold voltage V.sub.T of the transistors; i.e., V.sub.GS<V.sub.T.

(34) There now follows an analysis of the effect of temperature T of the TMOS transistors on the differential signal. In particular, assuming that the transistors M.sub.BLIND and M.sub.EXP are biased in sub-threshold conditions, the current on the drain terminal I.sub.D may be modelled, for example, using the model described by Clifton Fonstad, “MOSFETs in the Sub-threshold Region (i.e. a bit below VT)”, Oct. 28, 2009 (the contents of which are hereby incorporated by reference), in particular Eq. (29) appearing therein:

(35) $\begin{array}{cc}{I}_D=\frac{W}{L}.Math.{\mu }_e.Math.C_{ox}.Math.\left(n-1\right).Math.{\varphi }_t^2.Math.e^{\frac{V_{GS}-V_T}{n{\varphi }_t}}.Math.\left(1-e^{-\frac{V_{DS}}{{\varphi }_t}}\right)& \left(1\right)\end{array}$

(36) For a definition of the parameters of Eq. (1) reference may be made to the document cited. In particular, the inventors have noted that the following parameters of the equation depend upon the temperature T of the transistor: μ.sub.e, which represents the electron mobility, and V.sub.T, which is the threshold voltage of the transistor.

(37) In various embodiments, the voltages V.sub.CM1 and V.sub.CM2 are chosen in such a way that the voltages between the drain and source terminals V.sub.DS of the transistors M.sub.BLIND and M.sub.EXP are high with respect to the thermal voltage ϕ.sub.t, for example V.sub.DS>3ϕ.sub.t. In this case, Eq. (1) simplifies to

(38) $\begin{array}{cc}{I}_D=\frac{W}{L}.Math.{\mu }_e.Math.C_{ox}.Math.\left(n-1\right).Math.{\varphi }_t^2.Math.e^{\frac{V_{GS}-V_T}{n{\varphi }_t}}& \left(2\right)\end{array}$

(39) Moreover, substituting the thermal voltage ϕ.sub.t with kT/q and assuming that the mobility μ.sub.e of the transistors can be approximated by

(40) $\begin{array}{cc}{\mu }_e\left(T\right)\cong {{\mu }_{e0}\left(\frac{T_0}{T}\right)}^2& \left(3\right)\end{array}$
where μ.sub.e0 and T.sub.0 are two constants, the current I.sub.D of the transistors can be written as follows:

(41) $\begin{array}{cc}{I}_D\cong \frac{W}{L}.Math.{{\mu }_{e0}\left(\frac{T_0}{T}\right)}^2.Math.C_{ox}.Math.\left(n-1\right).Math.{\left(\frac{kT}{q}\right)}^2.Math.e^{\frac{V_{GS}-V_T\left(T\right)}{n\frac{kT}{q}}}i.e.,& \left(4\right)\\ \begin{array}{c}{I}_D=\frac{W}{L}.Math.{{\mu }_{e0}\left(\frac{k{T}_0}{q}\right)}^2.Math.C_{ox}.Math.\left(n-1\right).Math.e^{\frac{q}{nkT}\left(V_{GS}-V_T\left(T\right)\right)}\\ =I_{D0}.Math.e^{\frac{q}{nkT}\left(V_{GS}-V_T\left(T\right)\right)}\end{array}& \left(5\right)\end{array}$
where I.sub.D0 is a constant.

(42) In the ensuing treatment, the difference in temperature between the two TMOS transistors, which gives rise to the differential signal, will be denoted as
ΔT.sub.TMOS=T.sub.M.sub.EXP−T.sub.M.sub.BLIND.  (6)

(43) The variation of the current of the TMOS transistors caused by a small variation of temperature of the transistor itself can hence be evaluated by computing the derivative with respect to the temperature of Eq. (5) and then multiplying the result by the difference ΔT.sub.TMOS. Differentiating Eq. (5) we obtain

(44) $\begin{array}{cc}\begin{array}{c}\frac{{\mathrm{dI}}_D}{\mathrm{dT}}=I_{D0}.Math.e^{\frac{q}{nkT}\left(V_{GS}-V_T\left(T\right)\right)}.Math.\frac{d}{\mathrm{dT}}\left(\frac{q}{nkT}\left(V_{GS}-V_T\left(T\right)\right)\right)\\ =I_D.Math.\frac{q}{nkT}\left[\frac{V_{GS}-V_T\left(T\right)}{T}-\frac{{\mathrm{dV}}_T\left(T\right)}{\mathrm{dT}}\right]=g_m\left(T\right).Math.{\alpha }_{VGS}\left(T\right)\end{array}& \left(7\right)\end{array}$
where the factor (I.sub.Dq)/(nkT) is the small-signal transconductance of the TMOS transistors, which is denoted by g.sub.m.

(45) Considering that in the solution proposed I.sub.D≈I.sub.B, we have

(46) $\begin{array}{cc}{g}_m=\frac{{\mathrm{dI}}_D}{{\mathrm{dV}}_{GS}}=\frac{I_D}{n\frac{\mathrm{kT}}{q}}\cong \frac{I_B}{n{\varphi }_t}& \left(8\right)\end{array}$

(47) The multiplying factor α.sub.VGS(T)

(48) ${\alpha }_{VGS}\left(T\right)=\left[\frac{V_{GS}-V_T\left(T\right)}{T}-\frac{d{V}_T\left(T\right)}{dT}\right]$
can be considered equal to

(49) $\begin{array}{cc}{\alpha }_{VGS}\left(T\right)=\frac{d{V}_{GS}}{dT}& \left(9\right)\end{array}$
since

(50) ${\alpha }_{VGS}\left(T\right)\frac{{\mathrm{dI}}_D}{d{V}_{GS}}=\frac{{\mathrm{dI}}_D}{dT}$
i.e., α.sub.VGS(T) represents the non-normalized temperature coefficient of the voltage V.sub.GS of the transistors.

(51) The inventors have noted that, for typical values, the term α.sub.VGS(T) has little effect on the temperature variation. In fact, by rendering g.sub.m(T) substantially independent of the temperature, also the term g.sub.m(T).Math.α.sub.VGS(T) will likewise be a good approximation independent of the temperature.

(52) In general, the current of the TMOS transistors can hence be written as the sum of a biasing value plus a small-signal value:
I.sub.D,EXP=I.sub.B+i.sub.SIG_EXP  (10)
I.sub.D,BLIND=I.sub.B+i.sub.SIG_BLIND  (11)
where the small-signal contribution is the one due to a small temperature variation that is obtained on the TMOS transistors M.sub.EXP and M.sub.BLIND, respectively:

(53) 0$\begin{array}{cc}{i_{\mathrm{SIG}\_\mathrm{EX}P}\cong \frac{{\mathrm{dI}}_D}{\mathrm{dT}}.Math.}_{T_{\mathrm{amb}}}.Math.\Delta T_{M_{\mathrm{EX}P}}=\frac{I_B}{n{\varphi }_t}.Math.{\alpha }_{\mathrm{VGS}}\left(T\right)\left(T_{M_{\mathrm{EX}P}}-T_{\mathrm{amb}}\right)& \left(12\right)\\ {i_{\mathrm{SIG}\_\mathrm{BLIND}}\cong \frac{{\mathrm{dI}}_D}{\mathrm{dT}}.Math.}_{T_{\mathrm{amb}}}.Math.\Delta T_{M_{\mathrm{BLIND}}}=\frac{I_B}{n{\varphi }_t}.Math.{\alpha }_{\mathrm{VGS}}\left(T\right)\left(T_{M_{\mathrm{BLIND}}}-T_{\mathrm{amb}}\right)& \left(13\right)\end{array}$

(54) In the embodiment considered, the amplifier circuit hence does not amplify the voltage difference between the drain terminals of the transistors M.sub.BLIND and M.sub.EXP, but the circuit amplifies a current i.sub.S that corresponds to the difference of the currents in Eqs. (12) and (13).

(55) For this purpose, the drain terminal of the transistor M.sub.BLIND and the drain terminal of the transistor M.sub.EXP are connected to a differential current integrator 20. In particular, the circuit 20 comprises two input terminals, one of which receives a first current i.sub.1 and the other a second current i.sub.2. Moreover, the circuit 20 is configured for generating an output signal, such as a voltage V.sub.out, which is proportional to the integral of the difference between the currents i.sub.2 and i.sub.1.

(56) For example, in the embodiment considered, the circuit 20 is implemented with a single operational amplifier 202, such as an OTA. However, in general, the circuit 20 could also comprise a plurality of operational amplifiers.

(57) In particular, in the embodiment considered, a first input terminal of the operational amplifier 202 (typically, the negative terminal) is connected (for example, directly) to the drain terminal of the transistor M.sub.EXP, i.e., the terminal 104, and hence receives the current i.sub.1. A second input terminal of the operational amplifier 202 (typically, the positive terminal) is connected (for example, directly) to the drain terminal of the transistor M.sub.BLIND, i.e., the terminal 102, and hence receives the current i.sub.2. A first terminal of the differential output of the operational amplifier 202 (typically, the positive output terminal) is connected by a first feedback network to the first input terminal of the operational amplifier 202, and a second output terminal of the operational amplifier 202 (typically, the negative output terminal) is connected by a second feedback network to the first input terminal of the operational amplifier 202. In particular, the first and second feedback networks comprise, respectively, at least one integration capacitor. For example, in the embodiment considered, a capacitor C.sub.GAIN1 is connected (for example, directly) between the first output terminal and the first input terminal, and a capacitor C.sub.GAIN2 is connected (for example, directly) between the second output terminal and the second input terminal.

(58) Consequently, in the embodiment considered, the current i.sub.1 charges the capacitor C.sub.GAIN1, the current i.sub.2 charges the capacitor C.sub.GAIN2, and the output voltage corresponds to the difference of the voltages across the capacitors C.sub.GAIN1 and C.sub.GAIN2. Hence, considering the inverting configuration shown in FIG. 2, the amplifier 20 is configured for amplifying a current i.sub.S=i.sub.2−i.sub.1.

(59) Consequently, considering also Eqs. (10) and (11), in various embodiments, the amplifier circuit 20 receives at input a current
i.sub.S=i.sub.SIG_EXP−i.sub.SIG_BLIN  (14)

(60) In various embodiments, the amplification interface may also comprise a current generator 50, which supplies an additional compensation current i.sub.SC at input to the integrator 20. For example, in the embodiment considered, the current generator 50 comprises a first current generator 52, which supplies a current I.sub.SC/2 to the first input terminal of the integrator circuit 20 and a second current generator 58, which supplies a current −I.sub.SC/2 to the second input terminal of the integrator circuit 20.

(61) Consequently, in various embodiments, the amplifier circuit 20 receives at input a current
i.sub.S=i.sub.SIG_EXP−i.sub.SIG.sub.BLIND+I.sub.SC  (15)

(62) Hence, considering also Eqs. (12) and (13), the current i.sub.S corresponds to

(63) $\begin{array}{cc}{i}_S=\frac{I_B}{n{\varphi }_t}.Math.{\alpha }_{VGS}\left(T_{amb}\right)\Delta T_{TMOS}+I_{SC}& \left(16\right)\end{array}$

(64) The optional current I.sub.SC (as will be described in greater detail hereinafter) substantially makes it possible to carry out an offset correction in the output signal V.sub.out. Such an offset correction of the output may be useful for correcting any possible leakage or undesired signals that might lead the circuit 20 and/or the A/D converter 30 to exit from the dynamic range of proper operation.

(65) The current i.sub.S according to Eq. (14) or Eq. (16) is then supplied at input to the integrator circuit 20, and the integrator circuit 20 is configured for generating an output signal representing the integral of the current i.sub.S.

(66) For enabling a correct measurement of the current i.sub.S, the integrator circuit 20 further comprises a reset circuit, configured for selectively discharging the capacitors C.sub.GAIN1 and C.sub.GAIN2. For example, in the embodiment considered, the reset circuit is implemented with a first electronic switch SW.sub.RST1 connected in parallel to the capacitor C.sub.GAIN1 and a second electronic switch SW.sub.RST2 connected in parallel to the capacitor C.sub.GAIN2.

(67) In various embodiments, the amplification interface may also comprise a sample-and-hold circuit 80. In particular, this circuit 80 represents an analog memory configured for storing the value of the voltage V.sub.out at output from the integrator 20 as a function of a control signal SAMPLE. For example, in the simplest case, such a circuit 80 may be implemented with a capacitor C.sub.S that is selectively connected, for instance through one or more electronic switches, to the voltage V.sub.out as a function of the signal SAMPLE. For example, FIG. 2 represents schematically two switches SW.sub.S1 and SW.sub.S2. The capacitor C.sub.S may even correspond to the input capacitance of the A/D converter 30.

(68) For example, in the embodiment considered, the reset signal RST and the signal SAMPLE are generated by a single control circuit 70, which sets the reset signal RST for a first time interval T.sub.1 at a first logic level (typically high), for resetting the analog integrator, and for a second time interval T.sub.2 at a second logic level (typically low), for activating the analog integrator 20. Consequently, the duration T.sub.2 represents a measurement interval that corresponds to the integration period used by the analog integrator 20. In various embodiments, the time intervals T.sub.1 and T.sub.2 are constant.

(69) In general, on the basis of the implementation of the circuit 80, the signal SAMPLE may also correspond to the reset signal RST or to its inverted version. However, preferably, the control circuit 70 is configured for generating the signal SAMPLE so as to guarantee sampling of the voltage V.sub.out through the circuit 80 before the reset signal RST is set for discharging the capacitors C.sub.GAIN1 and C.sub.GAIN2. For example, in the embodiment considered, discharge starts upon switching of the signal RST from the second logic level (low) to the first level (high), and the signal SAMPLE is set to a low logic value after an interval T.sub.4, which is shorter than the interval T.sub.2, i.e., T.sub.4<T.sub.2.

(70) For instance, in various embodiments, the control circuit 70 generates the reset signal RST using a counter/timer 702 configured for incrementing a count value as a function of a clock signal CLK and for setting the logic level of the reset signal RST by comparing the count value with at least one first threshold that identifies the duration of the measurement interval T.sub.2. Likewise, the control circuit 70 can set the logic level of the signal SAMPLE by comparing the count value with at least one second threshold that identifies the duration of the interval T.sub.4. Hence, in various embodiments, the control circuit 70 is configured for generating the signals RST and SAMPLE synchronously with the clock signal CLK, which has a given oscillation frequency f.sub.osc; i.e., the time intervals during which these signals are set at “0” or else at “1” are a given multiple of the oscillation period 1/f.sub.osc.

(71) As shown schematically in FIG. 2, such a clock signal CLK can be supplied by an appropriate oscillator 72. In particular, as will be described in greater detail hereinafter, the oscillator 72 may be an oscillator that comprises at least one RC element, which defines the oscillation frequency f.sub.osc of the oscillator 72.

(72) A possible operation of the control circuit 70 and of the integrator circuit 20 is shown in FIG. 3. In particular, as explained previously, the control circuit 70 generates the reset signal RST; in particular, the control circuit 70 is configured for repeating periodically the following operations: at an instant t.sub.0, the signal RST is set at a first logic level (high) for resetting the analog integrator 20; and at an instant t.sub.1, the signal RST is set at a second logic level (low), thus determining the end of the reset step, i.e., the start of the integration step.

(73) Consequently, the time interval between the instants t.sub.0 and t.sub.1 corresponds to the reset interval T.sub.1, whereas the time interval between the instant t.sub.1 and the next instant t.sub.0′ corresponds to the measurement interval T.sub.2.

(74) In the embodiment considered, an example of the signal SAMPLE is also shown. In particular, as explained previously, the signal SAMPLE stores the value of the voltage V.sub.out before the analog integrator 20 is reset.

(75) For instance, for this purpose, the signal SAMPLE can be set with respect to start of the measurement interval T.sub.2 (i.e., with respect to the instant t.sub.1) for a sample time T.sub.4 at a first logic value, during which the circuit 80 stores the value of the signal V.sub.out, and for a hold time T.sub.5=T.sub.2−T.sub.4 it does not store the value of the signal V.sub.out and holds the value stored at the end of the interval T.sub.4. Consequently, for enabling a comparison of different measured values, the duration of the measurement interval T.sub.2 is not particularly important, but the time T.sub.4 should be constant.

(76) For example, in the embodiment considered, when the signal SAMPLE is “1” (high logic level), the differential voltage V.sub.ADC, which in the embodiment considered corresponds to the voltage on the capacitance C.sub.S (additional capacitor and/or input capacitance of the A/D converter 30), corresponds to the voltage V.sub.out. At the instant t.sub.2, i.e., when the signal SAMPLE is set at “0” (low logic level) the capacitance C.sub.S is disconnected from the output of the integrator 20, and the voltage V.sub.ADC remains fixed at the last voltage value assumed at the instant t.sub.2 thanks to the memory function of the capacitance C.sub.S. From the instant t.sub.2 up to the next instant t.sub.0′ (when the signal RESET goes to “1” cancelling out the differential signal V.sub.out, and the signal SAMPLE goes to “1” bringing the voltage V.sub.ADC to the value V.sub.out) the voltage V.sub.ADC remains fixed at the value that is to be sampled. Hence, between the instants t.sub.2 and t.sub.0′ the A/D converter 30 receives at input a fixed analog signal and can carry out a digital conversion of this analog level.

(77) As explained previously, in various embodiments, the reset time T.sub.1, the sample time T.sub.4, and the hold time T.sub.5 can be determined by means of an oscillator and a counter 702 and may hence correspond to
T.sub.1=N.sub.R/f.sub.osc  (17)
T.sub.4=N.sub.S/f.sub.osc  (18)
T.sub.5=N.sub.H/f.sub.osc  (19)

(78) In various embodiments, the values N.sub.R, N.sub.S, and N.sub.H are integers and may optionally also be programmable.

(79) Consequently, the amplification interface shown in FIG. 3 enables acquisition/sampling during each hold interval T.sub.5 through the A/D converter 30 of one or more respective samples of the voltage V.sub.out at the instant t.sub.2 of the respective sampling period T.sub.PERIOD=T.sub.1+T.sub.4+T.sub.5. For example, in FIG. 3, the processing circuit 40 can acquire through the A/D converter 30 a sequence of n samples SAMPLE.sub.1, SAMPLE.sub.2, . . . , SAMPLE.sub.n that represent, respectively, for the voltages V.sub.out(1), V.sub.out(2), . . . , V.sub.out(n).

(80) In particular, with reference to the embodiment represented in FIG. 2, during the reset step T.sub.1, the switches SW.sub.RST1, SW.sub.RST2, SW.sub.S1, and SW.sub.S2 (driven via the signals RST and SAMPLE) are closed. Consequently, the current i.sub.S flows in the switches SW.sub.RST1 and SW.sub.RST2 and is absorbed by the output of the OTA 202. In fact, given that the switches SW.sub.RST1 and SW.sub.RST2 are closed, the differential output V.sub.out is zero, since, by definition of virtual short-circuit, the differential voltage between the input terminals of the operational amplifier 202 is zero. In particular, in the embodiment considered, between the instants t.sub.0 and t.sub.1 the signal RST is “1”, and the signal SAMPLE is “1”. In this step, the signal current i.sub.S flows in the switches SW.sub.RST1 and SW.sub.RST2, which are closed. If these switches have a very low on-state resistance (ideally zero) the signal current i.sub.S causes a zero voltage drop, and hence the differential voltage V.sub.out is zero (as in FIG. 3). Moreover, the voltage V.sub.ADC at output from the circuit 80/at input to the A/D converter is equal to V.sub.out in so far as the switches SW.sub.S1 and SW.sub.S2 are closed.

(81) Consequently, while the control circuit 204 is configured for regulating the gate-to-source voltage V.sub.GS of the transistor M.sub.B in such a way that (V.sub.O1P+V.sub.O1N)/2=V.sub.CM1, the operational amplifier 202 imposes that the differential component (V.sub.O1P−V.sub.O1N) is zero.

(82) During the sampling phase T.sub.4, the switches SW.sub.RST1 and SW.sub.RST2 are open and the switches SW.sub.S1 and SW.sub.S2 are closed. Consequently, the current i.sub.S charges the capacitances C.sub.GAIN1 and C.sub.GAIN2, thus varying the voltage V.sub.out on the differential output of the OTA 202 and likewise also V.sub.ADC in so far as the switches SW.sub.S1 and SW.sub.S2 are closed. In particular, in the embodiment considered, at the instant t.sub.1 the signal RST is set at “0”, and hence the switches SW.sub.RST1 and SW.sub.RST2 are opened, and therefore the current i.sub.S flows in the capacitances C.sub.GAIN1 and C.sub.GAIN2, thus causing charging thereof. For example, in FIG. 3 it is assumed that the current i.sub.S is substantially constant and therefore the charging ramp of the capacitances C.sub.GAIN1 and C.sub.GAIN2 has a constant slope. Between the instants t.sub.2 and t.sub.0′, the voltage V.sub.ADC then remains stored at the value assumed at the instant t.sub.2 thanks to the action of the capacitance C.sub.S.

(83) Finally, during the hold phase T.sub.5, the switches SW.sub.RST1 and SW.sub.RST2 continue to remain open and hence the differential output V.sub.out continues to be charged by the current i.sub.S; however, in this phase (unlike in the sampling phase) T.sub.4 the switches SW.sub.S1 and SW.sub.S2 are opened. Consequently, throughout the hold phase T.sub.5, the voltage V.sub.ADC remains “frozen” constant at the value of the voltage V.sub.out assumed at the instants t.sub.2.

(84) As explained previously, during the sampling phase the current i.sub.S charges the capacitances C.sub.GAIN1 and C.sub.GAIN2. In particular, by choosing the capacitances of these capacitors so that C.sub.GAIN1=C.sub.GAIN2=C.sub.GAIN, the current i.sub.S is integrated by this capacitance C.sub.GAIN.

(85) Hence, a generic j-th sample V.sub.out(j) may be obtained as the integral of the current i.sub.S during the sampling window between the respective instants t.sub.1 and t.sub.2:

(86) $\begin{array}{cc}{V}_{out}=\frac{1}{C_{\mathrm{GAIN}}}.Math.{\int }_{t1}^{t2}{i}_S\left(t\right)dt& \left(20\right)\end{array}$

(87) For example, assuming for simplicity that the current i.sub.S(t) is substantially constant in the time interval between t.sub.1 and t.sub.3 and equal to the value i.sub.S,j, and considering moreover that the duration of the interval T.sub.1, is constant, e.g., T.sub.1=N.sub.S/f.sub.osc, then Eq. (20) can be written as follows:

(88) $\begin{array}{cc}{V}_{out,j}=\frac{1}{C_{\mathrm{GAIN}}}.Math.T_1.Math.i_{S,j}=\frac{1}{C_{\mathrm{GAIN}}}.Math.\frac{N_S}{f_{osc}}.Math.i_{S,j}& \left(21\right)\end{array}$

(89) For example, substituting the current i.sub.s,j with the expression defined by Eq. (16), then Eq. (21) can be written as follows:

(90) $\begin{array}{cc}{V}_{out,j}=\frac{1}{C_{\mathrm{GAIN}}}.Math.\frac{N_S}{f_{osc}}.Math.\left[\frac{I_B}{n{\varphi }_t}.Math.{\alpha }_{VGS}\left(T_{amb}\right)\Delta T_{TMOS}+I_{SC}\right]& \left(22\right)\end{array}$

(91) The inventors have noted that Eq. (22) can then be reformulated as follows:

(92) $\begin{array}{cc}{V}_{out,j}=\frac{1}{C_{\mathrm{GAIN}}}.Math.\frac{N_S}{f_{osc}}.Math.\frac{I_B}{{\varphi }_t}.Math.\left[\frac{{\alpha }_{VGS}\left(T_{amb}\right)}{n}.Math.\Delta T_{TMOS}+\frac{{\varphi }_t}{I_B}.Math.I_{SC}\right]& \left(23\right)\end{array}$

(93) In fact, Eq. (23) highlights the fact that, if the bias current I.sub.B and the clock frequency f.sub.osc are chosen with given characteristics, the implementation can be rendered robust and insensitive to the process spread, i.e., to the variation of the resistances and capacitances. In particular, in various embodiments, the current generators 206 and 208, and the oscillator 72 are configured in such a way that the coefficient I.sub.B/f.sub.osc will remain constant.

(94) Specifically, in various embodiments, the current generators 206 and 208 are configured as PTAT current generators, i.e., ones which supply a current proportional to the temperature.

(95) These PTAT current generators are well known. For example, FIG. 8 shows a possible embodiment of a PTAT current generator.

(96) In the embodiment considered, the above current generator comprises a first bipolar transistor Q1, for example, a pnp transistor, and a second bipolar transistor Q2, for example a pnp transistor. For instance, in the embodiment considered, the collector and the base of the transistor Q1, and the collector and the base of the transistor Q2 are connected to a reference voltage, for example ground.

(97) Furthermore, appropriate biasing circuits are provided for the transistors Q1 and Q2. For example, in the embodiment considered, there is a first current generator in the form of a FET M3, for example of the p-channel type, which supplies a bias current to the emitter of the transistor Q1, and a second current generator in the form of a FET M4, for example of the p-channel type, which supplies a bias current to the emitter of the transistor Q2.

(98) The bias current supplied by the transistor M4, i.e., the current that traverses the transistor Q2, also traverses a resistor R.sub.BIAS. In particular, in the embodiment considered, the source terminal of the transistor M3 is connected (for example, directly) to a supply voltage, e.g., V.sub.DD, and the drain terminal of the transistor M3 is connected (for example, directly) to the emitter of the transistor Q1. Likewise, the source terminal of the transistor M4 is connected (for example, directly) to the supply voltage, e.g., V.sub.DD, and the drain terminal of the transistor M4 is connected (for example, directly) to a first terminal of the resistor R.sub.BIAS, and a second terminal of the resistor R.sub.BIAS is connected (for example, directly) to the emitter of the transistor Q2.

(99) Consequently, the transistors Q1 and Q2 are biased, and the voltage on the emitter of the transistor Q1 corresponds to the emitter-to-base voltage V.sub.EB1 of the transistor Q1, and the voltage on the emitter of the transistor Q2 corresponds to the emitter-to-base voltage V.sub.EB2 of the transistor Q2.

(100) The voltage difference ΔV.sub.BE=V.sub.EB1−V.sub.EB2 is then applied to the resistor R.sub.BIAS. In particular, in the embodiment considered, the current generator comprises, for this purpose, an operational amplifier 230, where: a first input terminal of the operational amplifier 230 (typically, the negative terminal) is connected (for example, directly) to the emitter of the transistor Q1/drain terminal of the transistor M3; a second input terminal of the operational amplifier 230 (typically, the positive terminal) is connected (for example, directly) to the drain terminal of the transistor M4; and the output terminal of the operational amplifier 230 drives the gate terminals of the transistors M3 and M4.

(101) Consequently, in the embodiment considered, the voltage V.sub.EB1 is applied by the virtual short-circuit of the operational amplifier 230 across the resistor R.sub.BIAS, since the operational amplifier 230 regulates the current that traverses the resistor R.sub.BIAS accordingly. In the embodiment considered, the current that traverses the resistor R.sub.BIAS hence corresponds to a reference current F that depends upon the resistance R.sub.BIAS and the voltage difference ΔV.sub.BE=V.sub.EB1−V.sub.EB2.

(102) In the embodiment considered, the current i.sub.REF is then also transferred to the output of the current generator; i.e., the current generator supplies a current I.sub.B proportional to the current i.sub.REF. For example, in the embodiment considered, a transistor M1 is used, where the source terminal is connected (for example, directly) to the supply voltage, the gate terminal is connected (for example, directly) to the gate terminal of the transistor M4, and the drain terminal supplies the current I.sub.B. Consequently, the transistor M1 could correspond to the current generator 206 of FIG. 2 that is connected to the terminal 102. Likewise, the current generator 208 may be provided by adding a transistor M2, where the source terminal is connected (for example, directly) to the supply voltage, the gate terminal is connected (for example, directly) to the gate terminal of the transistor M4, and the drain terminal supplies the current I.sub.B to the terminal 104.

(103) Other schemes of PTAT current generators are described, for example, in U.S. Pat. No. 8,159,206 or in Carlos Christoffersen, et al., “An Ultra-Low Power CMOS PTAT Current Source”, Proceedings of the Argentine-Uruguay School of Micro-Nanoelectronics, Technology and Applications 2010, EAMTA 2010, the contents of both of which are hereby incorporated by reference.

(104) Consequently, in various embodiments, a PTAT current generator comprises one or more transistors that supply a reference voltage ΔV.sub.BE, which corresponds to a voltage difference which is applied to a bias resistance R.sub.BIAS, and the current (i.sub.REF) that traverses the resistor R.sub.BIAS is applied, possibly by one or more current mirrors, to the output of the current generator, i.e.,

(105) $\begin{array}{cc}{I}_B\sim \frac{\Delta V_{BE}}{R_{\mathrm{BIAS}}}& \left(24\right)\end{array}$

(106) For example, the current of a PTAT current generator may be defined as:

(107) $\begin{array}{cc}{I}_B=\frac{{\varphi }_t\ln \left(b\right)}{R_{\mathrm{BIAS}}}& \left(25\right)\end{array}$

(108) In particular, in the embodiment represented in FIG. 8, the parameter b is the ratio between the area A2 of the transistor Q2 and the area A1 of the transistor Q1, i.e., A2=b.Math.A1, with b>1. The parameter b is hence a constant number, which can be fixed with a good precision (being a ratio of areas).

(109) Instead, in various embodiments, the oscillator 72 is based upon an RC oscillator. These RC oscillators may be from, for example, U.S. Pat. No. 6,590,463, the contents of which are hereby incorporated by reference. In particular, an RC oscillator comprises a resistor R.sub.osc and a capacitor C.sub.osc, and the clock frequency f.sub.osc is proportional to the inverse of an RC product; namely,

(110) $\begin{array}{cc}{f}_{\mathrm{osc}}\sim \frac{1}{R_{\mathrm{osc}}.Math.C_{\mathrm{osc}}}& \left(26\right)\end{array}$

(111) The proportionality may be rendered explicit by introducing a gain coefficient G.sub.osc of the oscillator; i.e.,

(112) $\begin{array}{cc}{f}_{\mathrm{osc}}=\frac{G_{\mathrm{osc}}}{R_{\mathrm{osc}}.Math.C_{\mathrm{osc}}}& \left(27\right)\end{array}$

(113) In this context, the inventors have noted that, by appropriately sizing the above values, the influence of the process spread may be (at least partially) compensated. In particular, in various embodiments, the oscillator 72 is configured in such a way that:
R.sub.osc=M.Math.R.sub.BIAS  (28)
C.sub.osc=P.Math.C.sub.GAIN  (29)

(114) where P and M are coefficients.

(115) Consequently, in various embodiments, the resistance R.sub.osc of the oscillator 72 and the resistance R.sub.BIAS of the current generators 206 and 208 are obtained with the same process. Furthermore, in various embodiments, these resistances are provided in the same integrated circuit/die and are preferably arranged in the proximity of one another in such a way as to be exposed to the same temperature variations.

(116) Likewise, in various embodiments, the capacitance C.sub.osc of the oscillator 72 and the capacitance C.sub.GAIN of the integrator 20 are obtained using the same process. Furthermore, in various embodiments, these capacitances are provided in the same integrated circuit/die and are preferably arranged in the proximity of one another in such a way as to be exposed to the same temperature variations.

(117) Consequently, in various embodiments, Eq. (23) corresponds to

(118) 0$\begin{array}{cc}{V}_{\mathrm{out}}=\frac{N_S.Math.M.Math.P.Math.\ln \left(b\right)}{G_{\mathrm{osc}}}.Math.\left[\frac{{\alpha }_{VGS}\left(T_{amb}\right)}{n}.Math.\Delta T_{TMOS}+\frac{R_{\mathrm{BIAS}}}{\ln \left(b\right)}.Math.I_{SC}\right]& \left(30\right)\end{array}$

(119) This equation highlights also why the current I.sub.SC is useful for carrying out an offset correction in the differential output signal V.sub.out. In particular, as explained previously, the current generator 50, together with the circuit 204 that carries out the common-mode control, makes it possible to correct any possible leakage or undesired signals that might lead the OTA block 202 and/or the A/D converter 30 to exit from the dynamic range of proper operation, or else might lead the TMOS transistors out of the desired operating point. Hence, the system proposed is robust for compensating possible leakage-current signals injected into the high-impedance nodes V.sub.O1N and V.sub.O1NP, i.e., the input terminals of the integrator circuit 20. In particular, the common-mode component of these leakage signals is compensated by the circuit 204, thus preventing common-mode drifts. Instead, the differential leakage component may be eliminated by tuning, i.e., trimming, the value of the current I.sub.SC supplied by the current generator 50.

(120) The way in which the current I.sub.SC is generated defines the type of offset compensation that is carried out.

(121) For example, in various embodiments, the current generator is programmable for supplying a variable current I.sub.SC. For instance, for this purpose, a circuit, for example the processing circuit 40, can monitor the voltage V.sub.out and vary the current I.sub.SC as a function of the voltage V.sub.out. For instance, in this context, reference may be made to Italian Patent Application No. 102019000001847, the contents of which are hereby incorporated by reference.

(122) In particular, this document describes amplification interfaces, where the current generator 50 may be an IDAC (Current Digital-to-Analog Converter), which hence supplies a current that has an amplitude variable as a function of a digital signal having a plurality of bits.

(123) Moreover, this document describes the fact that, in the case of an amplifier provided by an analog integrator, the current generator could also supply a current that is modulated, for example by a PWM (Pulse-Width Modulation) signal, thereby varying the mean value of the current supplied by the current generator 50. For example, the current generator 50 may supply, as a function of a driving signal, a positive current or a negative current. Consequently, when the driving signal has a first logic value, the current generator 50 supplies the positive current, and, when the driving signal has a second logic value, the current generator 50 supplies the negative current. Hence, the control circuit 70 can determine for each measurement interval T.sub.2 a first duration T.sub.3 during which the driving signal has the first logic value, and a second duration (T.sub.2−T.sub.3) during which the driving signal has the second logic value. Consequently, by varying the duration T.sub.3 it is possible to choose, for each measurement interval T.sub.2, the mean value of the current I.sub.SC supplied by the current generator 50. This modulation is not perceivable by the A/D converter 30, since the analog integrator supplies at output the integral of the current, which, at the end of a measurement/sampling interval, only represents the mean value of the current.

(124) For example, by applying this to the circuit scheme shown in FIG. 2, the control circuit 70 can be configured, during each measurement interval T.sub.2, for: activating the current generator 52 and deactivating the generator 58 for the duration T.sub.3; and deactivating the current generator 52 and activating the generator 58 for the duration (T.sub.2−T.sub.3).

(125) In this case, the current generators 52 and 58 can hence be configured for supplying a respective constant current. Preferably, the current generators 52 and 58 supply in this case currents with the same amplitude but with opposite sign.

(126) However, the current generator 50 may even not be programmable.

(127) For example, in various embodiments, the current generator 50 generates the current I.sub.SC as a bandgap current, where a reference voltage V.sub.REF supplied by a bandgap voltage generator (i.e., one that does not vary with temperature) is used. For example, reference may be made to Kleczek, et al. “Low voltage area efficient current-mode CMOS bandgap reference in deep submicron technology” 2014 Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES) (2014): 247-251, the contents of which are hereby incorporated by reference. In particular, this document describes, in the introductory part, various solutions for generation of a PTAT or bandgap current.

(128) In this case, also the offset correction that is obtained is independent of the temperature. For instance, in this case, the current I.sub.SC is typically

(129) $\begin{array}{cc}{I}_{\mathrm{SC}}\sim \frac{V_{REF}}{R_{\mathrm{BIAS}2}}& \left(31\right)\end{array}$

(130) In various embodiments, the resistance R.sub.BIAS2 of the current generator 50 and the resistance R.sub.BIAS of the current generators 206 and 208 are obtained with the same process. Furthermore, in various embodiments, these resistances are provided in the same integrated circuit/die and are preferably set in the proximity of one another in such a way as to be exposed to the same temperature variations; namely,

(131) $\begin{array}{cc}{I}_{\mathrm{SC}}=\frac{V_{REF}}{B.Math.R_{\mathrm{BIAS}}}& \left(32\right)\end{array}$

(132) Consequently, in this case, Eq. (30) can be reformulated as follows:

(133) $\begin{array}{cc}{V}_{\mathrm{out}}=\frac{N_S.Math.M.Math.P.Math.\ln \left(b\right)}{G_{\mathrm{osc}}}.Math.\left[\frac{{\alpha }_{VGS}\left(T_{amb}\right)}{n}.Math.\Delta T_{TMOS}+\frac{R_{\mathrm{BIAS}}}{B.Math.\ln \left(b\right)}\right]& \left(33\right)\end{array}$

(134) Instead, in other embodiments, the current generator 50 generates the current I.sub.SC as a PTAT current (i.e., a current proportional to the temperature), for example,

(135) $\begin{array}{cc}{I}_{\mathrm{SC}}\sim \frac{\Delta V_{BE}}{R_{\mathrm{BIAS}2}}& \left(34\right)\end{array}$

(136) for instance,

(137) $\begin{array}{cc}{I}_{\mathrm{SC}}=\frac{{\varphi }_t\ln \left(a\right)}{R_{\mathrm{BIAS}2}}& \left(35\right)\end{array}$

(138) In various embodiments, the resistance R.sub.BIAS2 of the current generator 50 and the resistance R.sub.BIAS of the current generators 206 and 208 are obtained with the same process. Furthermore, in various embodiments, these resistances are provided in the same integrated circuit/die and are preferably arranged in the proximity of one another in such a way as to be exposed to the same temperature variations; for example,

(139) $\begin{array}{cc}{I}_{\mathrm{SC}}=\frac{{\varphi }_t\ln \left(a\right)}{B.Math.R_{\mathrm{BIAS}}}=\frac{\ln \left(a\right)}{B.Math.R_{\mathrm{BIAS}}}.Math.\frac{k}{q}.Math.T& \left(36\right)\end{array}$

(140) Consequently, in this case, Eq. (30) can be reformulated as follows:

(141) $\begin{array}{cc}{V}_{out}=\frac{N_S.Math.M.Math.P.Math.\ln \left(b\right)}{G_{\mathrm{osc}}}.Math.\left[\frac{{\alpha }_{VGS}\left(T_{amb}\right)}{n}.Math.\Delta T_{TMOS}+\frac{\ln \left(a\right)}{B.Math.\ln \left(b\right)}.Math.\frac{k}{q}.Math.T\right]& \left(37\right)\end{array}$

(142) From Eqs. (33) and (37) it may be noted how in the approach proposed the dependence of the output signal upon the spread of the technological process used for manufacturing the resistances and the capacitances has been eliminated, since there remain only the coefficients of proportionality B, M, and P.

(143) This result has been obtained thanks to the architectural choice made and thanks to an appropriate choice of the bias current I.sub.B and of the clock frequency f.sub.osc. Moreover, from Eq. (33) it may be concluded that in the first case (I.sub.SC of a bandgap type) a possible offset independent of the temperature T may be corrected, whereas in the second case (I.sub.SC of a PTAT type) a possible offset that varies in temperature can be corrected. In general, the current generator 50 could also be implemented with two current generators, where the first supplies a current I.sub.SC1 of a bandgap type and the second supplies a current I.sub.SC2 of a PTAT type, which hence enables correction of an offset contribution that, in addition to a part that does not vary in temperature, also has a part variable in temperature.

(144) FIG. 4 shows a second embodiment. Basically, as compared to FIG. 2, the amplification interface moreover comprises three circuits 210, 212 and 214. In addition, the control circuit 70 is configured for generating two control signals C1 and C2 for these circuits, and the amplifier 20 or the processing circuit 40 comprises a circuit module 216 configured for processing the digital samples supplied by the A/D converter 30.

(145) In particular, the circuits 210, 212, and 214 are chopper circuits that reverse the connection between two respective circuits.

(146) In particular, in the embodiment considered, the current generator 208 is connected to the first input terminal of the current integrator 20 (for example, the negative terminal), and the current generator 206 is connected to the second input terminal of the current integrator 20 (for example, the positive terminal).

(147) In this case, as a function of the signals C1 and C2, the chopper circuit 210 is configured for selectively connecting the transistor M.sub.EXP to the first input terminal or to the second input terminal of the current integrator 20, and likewise the transistor M.sub.BLIND to the second input terminal or to the first input terminal of the current integrator 20.

(148) For instance, in the embodiment considered, the chopper circuit 210 comprises: a switch SW.sub.5 for selectively connecting the transistor M.sub.BLIND to the second input terminal of the current integrator 20 as a function of the signal C1; and a switch SW.sub.7 for selectively connecting the transistor M.sub.BLIND to the first input terminal of the current integrator 20 as a function of the signal C2. Moreover, the chopper circuit 210 comprises a switch SW.sub.8 for selectively connecting the transistor M.sub.EXP to the first input terminal of the current integrator 20 as a function of the signal C1 and a switch SW.sub.6 for selectively connecting the transistor M.sub.EXP to the second input terminal of the current integrator 20 as a function of the signal C2.

(149) Likewise, as a function of the signals C1 and C2, the chopper circuit 214 is configured for selectively connecting the current generator 58 to the first input terminal or to the second input terminal of the current integrator 20, and likewise the current generator 52 to the second input terminal or to the first input terminal of the current integrator 20.

(150) For instance, in the embodiment considered, the chopper circuit 214 comprises: a switch SW.sub.1 for selectively connecting the current generator 52 to the second input terminal of the current integrator 20 as a function of the signal C1; and a switch SW.sub.2 for selectively connecting the current generator 52 to the first input terminal of the current integrator 20 as a function of the signal C2. Moreover, the chopper circuit 214 comprises: a switch SW.sub.4 for selectively connecting the current generator 58 to the first input terminal of the current integrator 20 as a function of the signal C1; and a switch SW.sub.3 for selectively connecting the current generator 58 to the second input terminal of the current integrator 20 as a function of the signal C2.

(151) Consequently, the chopper circuits 210 and 214 make it possible to reverse the connection, respectively, of the transistors M.sub.EXP and M.sub.BLIND and of the current generators 52 and 58 to the input terminals of the current integrator 20.

(152) In the embodiment considered, the chopper circuit 212 is configured for reversing the connection of the output of the integrator 20 to the input of the A/D converter 30, i.e., for inverting the output voltage V.sub.out of the current integrator 20.

(153) For instance, in the embodiment considered, the chopper circuit 212 comprises: a switch SW.sub.9 for selectively connecting the positive output terminal of the current integrator 20 to the positive input terminal of the A/D converter 30 as a function of the signal C1; and a switch SW.sub.10 for selectively connecting the positive output terminal of the current integrator 20 to the negative input terminal of the A/D converter 30 as a function of the signal C2. Moreover, the chopper circuit 212 comprises: a switch SW.sub.12 for selectively connecting the negative output terminal of the current integrator 20 to the negative input terminal of the A/D converter 30 as a function of the signal C1; and a switch SW.sub.11 for selectively connecting the negative output terminal of the current integrator 20 to the positive input terminal of the A/D converter 30 as a function of the signal C2.

(154) In general, the chopper circuit 212 can also implement the switches SW.sub.S1 and SW.sub.S2 of the sample-and-hold circuit 80 of FIG. 2. In fact, in the embodiment considered, by opening the switches S.sub.9, S.sub.10, S.sub.11, and S.sub.12, the A/D converter is disconnected from the output of the integrator 20.

(155) FIG. 5 shows a possible operation of the control circuit 70.

(156) In the embodiment considered, during each interval T.sub.PERIOD, the control circuit 70 drives one of the signals C1 or C2, and the other signal is kept at its logic level. For instance, during the first interval the signal C1 is varied, and during the second interval the signal C2 is varied.

(157) Consequently, operation of the circuit during the first interval basically corresponds to what has been described with reference to FIG. 2, where the current generator 58 and the transistor M.sub.EXP are connected to the first input terminal of the integrator 20, and the current generator 52 and the transistor M.sub.BLIND are connected to the second input terminal of the integrator 20. Moreover, the signal C1 performs the function of the signal SAMPLE described with reference to FIG. 3. Consequently, in the embodiment considered, the control circuit 70: resets the integrator 20 (using the switches SW.sub.RST1 and SW.sub.RST2 and the signal RST) at an instant t.sub.0; activates the integrator 20 (using the switches SW.sub.RST1 and SW.sub.RST2 and the signal RST) at an instant t.sub.1; and disconnects the output of the integrator (using the switches SW.sub.9 and SW.sub.12 and the signal C1) at an instant t.sub.2, thus enabling sampling of the voltage V.sub.ADC.

(158) Instead, operation of the circuit during the second interval is reversed. In particular, the current generator 58 and the transistor M.sub.EXP are connected to the second input terminal of the integrator 20, and the current generator 52 and the transistor M.sub.BLIND are connected to the first input terminal of the integrator 20. Moreover, the signal C2 performs the function of the signal SAMPLE described with reference to FIG. 3. Consequently, in the embodiment considered, the control circuit: resets the integrator 20 (using the switches SW.sub.RST1 and SW.sub.RST2 and the signal RST) at an instant t.sub.0; activates the integrator 20 (using the switches SW.sub.RST1 and I.sub.2 and the signal RST) at an instant t.sub.1; and disconnects the output of the integrator (using the switches SW.sub.10 and SW.sub.11 and the signal C2) at an instant t.sub.2, thus enabling sampling of the voltage V.sub.ADC.

(159) For this reason, the integrator 20 integrates, during the second interval, a current i.sub.S that has an opposite sign with respect to the current i.sub.S during the first interval (since the input of the integrator 20 is substantially reversed).

(160) Consequently, also the output voltage V.sub.out increases during an interval (for example, the first interval for the case provided by way of example) and decreases during the other (for example, the second interval for the case provided by way of example). However, by inverting the output of the integrator 20, the voltage V.sub.ADC will always present the same behavior.

(161) In various embodiments, the block 216 consequently carries out a calculation of the mean value of the digital sample and may, for example, be a moving-average filter that receives at input the samples from the ADC 30 at the sampling frequency 1/T.sub.PERIOD and produces at output a signal at the sampling frequency 1/T.sub.PERIOD, where each sample is obtained by averaging the last n samples received from the ADC (where n is preferably considered an even number).

(162) In general, introduction of the block 216 downstream of the ADC 30 is possible also in the embodiment of FIG. 2 in order to average the output signals produced at the sampling frequency T.sub.PERIOD, thus obtaining a signal that is averaged and hence less noisy. In general, also in the approach of FIG. 4, introduction of the block 216 likewise enables a reduction of the noise. However, in FIG. 4 it is not only a possible improvement, but its introduction also enables elimination of the component that the output signal presents at the chopping frequency.

(163) In general, similar chopping operations may be used for eliminating the offset of the OTA 202. Instead, in the embodiment considered, such chopping operations are also extended for compensating the differences between the current generators. In the embodiment considered, the chopping frequency is hence half of the sampling frequency.

(164) In particular, as mentioned previously, the integrator 20 is configured for integrating, during a first interval, a current

(165) $\begin{array}{cc}{i}_S=i_{\mathrm{SIG\_EXP}}-i_{{\mathrm{SIG}}_{\mathrm{BLIND}}}+I_{SC}=\frac{I_B}{n{\varphi }_t}.Math.{\alpha }_{VGS}\left(T_{amb}\right)\Delta T_{TMOS}+I_{SC}& \left(38\right)\end{array}$

(166) and, during the second interval, a current

(167) $\begin{array}{cc}{i}_S=-i_{{\mathrm{SIG}}_{\mathrm{EXP}}}+i_{{\mathrm{SIG}}_{\mathrm{BLIND}}}-I_{SC}=-\frac{I_B}{n{\varphi }_t}.Math.{\alpha }_{VGS}\left(T_{amb}\right)\Delta T_{TMOS}-I_{SC}& \left(39\right)\end{array}$

(168) Consequently, the signal V.sub.OUT that is obtained from integration has a slope of a different sign during the first and second intervals. However, if there is also considered the further signal inversion carried out by the circuit 212 inserted before the A/D converter 30, the signal will always have the same sign.

(169) Hence, from a mathematical standpoint, the signal V.sub.ADC would have to be equal to the one obtained with the embodiment illustrated in FIG. 2. Instead, in the actual implementation, the two current generators 206 and 208 may present a mismatch (denoted hereinafter by ΔI.sub.B), and/or the OTA block 202 may present an equivalent offset at input (denoted hereinafter by V.sub.off_OTA).

(170) Assuming that both of the non-idealities ΔI.sub.B and V.sub.off_OTA are present, two successive samples V.sub.out(j) and V.sub.out(j+1) will have the following values in the embodiment represented in FIG. 2:

(171) 0$\begin{array}{cc}{V}_{\mathrm{ADC}}\left(j\right)=V_{\mathrm{out}}\left(j\right)=\frac{N_S.Math.M.Math.P.Math.\ln \left(b\right)}{G_{\mathrm{osc}}}.Math.\hspace{1em}\left[\frac{{\alpha }_{VGS}\left(T_{amb}\right)}{n}.Math.\Delta T_{TMOS}+\frac{R_{\mathrm{BIAS}}}{\ln \left(b\right)}.Math.\left(I_{\mathrm{SC}}+\Delta I_B\right)\right]+V_{\mathrm{off\_OTA}}& \left(40\right)\\ V_{\mathrm{ADC}}\left(j+1\right)=V_{\mathrm{out}}\left(j+1\right)=\frac{N_S.Math.M.Math.P.Math.\ln \left(b\right)}{G_{\mathrm{osc}}}.Math.\hspace{1em}\left[\frac{{\alpha }_{VGS}\left(T_{amb}\right)}{n}.Math.\Delta T_{TMOS}+\frac{R_{\mathrm{BIAS}}}{\ln \left(b\right)}.Math.\left(I_{\mathrm{SC}}+\Delta I_B\right)\right]+V_{\mathrm{off\_OTA}}& \left(41\right)\end{array}$

(172) Instead, two successive samples V.sub.out(j) and V.sub.out(j+1) will have the following values in the embodiment represented in FIG. 4:

(173) $\begin{array}{cc}{V}_{\mathrm{ADC}}\left(j\right)=V_{\mathrm{out}}\left(j\right)=\frac{N_S.Math.M.Math.P.Math.\ln \left(b\right)}{G_{\mathrm{osc}}}.Math.\hspace{1em}\left[\frac{{\alpha }_{VGS}\left(T_{amb}\right)}{n}.Math.\Delta T_{TMOS}+\frac{R_{\mathrm{BIAS}}}{\ln \left(b\right)}.Math.\left(I_{\mathrm{SC}}+\Delta I_B\right)\right]+V_{\mathrm{off\_OTA}}& \left(42\right)\\ V_{\mathrm{ADC}}\left(j+1\right)=-V_{\mathrm{out}}\left(j+1\right)=\frac{N_S.Math.M.Math.P.Math.\ln \left(b\right)}{G_{\mathrm{osc}}}.Math.\hspace{1em}\left[\frac{{\alpha }_{VGS}\left(T_{amb}\right)}{n}.Math.\Delta T_{TMOS}+\frac{R_{\mathrm{BIAS}}}{\ln \left(b\right)}.Math.\left(I_{\mathrm{SC}}+\Delta I_B\right)\right]-V_{\mathrm{off\_OTA}}& \left(43\right)\end{array}$

(174) Consequently, by computing the average of both values, or in general an even number of samples, the block 216 filters the effect of the non-idealities ΔI.sub.B and V.sub.off_OTA.

(175) Basically, the filtering carried out on these quantities thanks to the chopping technique is of a high-pass type; i.e., they will be filtered out in the case where they are d.c. quantities or anyway also in the case where they are quantities that vary at low frequency. It may hence be noted how filtering eliminates not only the mismatches ΔI.sub.B between the two generators but also the low-frequency noise introduced by the two generators I.sub.B, thus also improving the performance of the system from the standpoint of the signal-to-noise ratio.

(176) The same effect of cancellation of the aforesaid non-idealities would not be produced by the same block 216 applied at output to the system of FIG. 2 in so far as, by averaging samples such as those described by Eqs. (40) and (41), the effect of ΔI.sub.B and V.sub.off_OTA would not be filtered out.

(177) Appearing in FIG. 6 is the scheme of a third embodiment. As compared to the architecture of FIG. 4, the difference is that the signal of correction of offset (from the current generator) is added directly to the signal produced by the TMOS sensor 10. In particular, in the embodiment considered, the current generator 52 is connected to the drain terminal of the transistor M.sub.BLIND, and the current generator 528 is connected to the drain terminal of the transistor M.sub.EXP.

(178) In this case, just the chopper circuit 210 may be sufficient. The resulting output signal of the embodiment shown in FIG. 6 is altogether the same as the one presented for the embodiment of FIG. 4; hence, the foregoing description applies also here.

(179) Represented in FIG. 7 is the diagram of a fourth circuit architecture proposed by the present invention. As compared to the architecture of FIG. 4 (but a similar modification could be made in the embodiment represented in FIG. 6), the difference is that the chopper circuit 212 has been moved downstream of the A/D converter 30. Consequently, in the embodiment considered, a chopper circuit or module 212′ of a digital type is used, for example implemented by means of a digital circuit module of the processing circuit 40. This circuit or module is hence configured for supplying to the circuit 216, as a function of the signals C1 and C2, the value of the digital sample supplied by the A/D converter 30 or the value of the digital sample supplied by the A/D converter 30 multiplied by −1.

(180) Consequently, in various embodiments, the approaches proposed enable amplification of the signal generated by TMOS transistors, without being affected by the technological process spread that affects the resistances and capacitances.

(181) In various embodiments, this has been obtained thanks to the architecture proposed, in addition to an appropriate choice of the bias current I.sub.B and of the reference clock frequency f.sub.osc.

(182) In various embodiments, the approach proposed enables correction of the offset and of the variation of the offset as a function of temperature.

(183) In addition, in various embodiments, the approach proposed in its second implementation also enables filtering of the non-idealities in the bias current and the offset of the OTA.

(184) In general, the approach proposed is devised for amplifying the signal generated by TMOS transistors, but it may also be used in the case where the transistors M.sub.BLIND and M.sub.EXP are two normal MOS transistors, or in general FETs, and at their input (i.e., the gate terminals of the two transistors) there is a differential signal to be amplified.

(185) Of course, without prejudice to the principles of this disclosure, the details of construction and the embodiments may vary widely with respect to what has been described and illustrated herein purely by way of example, without thereby departing from the scope of the present invention, as defined by the ensuing claims.

(186) The claims form an integral part of the technical teaching of the description provided herein.