Frequency synthesis device with feedback loop

Abstract

A frequency synthesis device includes a servo circuit for controlling an output frequency to an input reference frequency. The circuit includes a first phase accumulator clocked by the reference frequency, a phase comparison block, a loop filter and an oscillator. It further includes a feedback loop connecting the output to the comparison block, having a second phase accumulator clocked by the output frequency. The comparison block includes T phase comparators with logic gates receiving respectively T first logic signals from the servo circuit on T first inputs and T second logic signals from the feedback loop on T second inputs, the T first and second signals having logic levels that continuously depend on values provided by the first and second accumulators according to at least one multi-phase correspondence matrix.

Claims

1. A feedback-loop frequency synthesis device comprising: an input intended to receive an electrical signal oscillating at a reference frequency; an output intended to supply an electrical signal oscillating at an output frequency; a servo circuit for the control of the output frequency by the reference frequency, connecting the input to the output of the device and comprising a first phase accumulator clocked at a frequency linked to the reference frequency, a phase comparison block, a loop filter and a frequency controlled oscillator providing the electrical signal oscillating at the output frequency, the phase comparison block being linked to the loop filter for controlling said frequency controlled oscillator; and a feedback loop connecting the output to the phase comparison block, comprising a second phase accumulator clocked at a frequency linked to the output frequency, the first and second phase accumulators being adapted to provide the same number T of possible phase accumulation discrete values; wherein the servo circuit is configured to provide, to the phase comparison block T first distinct logic signals the logic levels of which depend continuously on the phase accumulation values supplied by the first phase accumulator according to a first multi-phase correspondence matrix between the T possible phase accumulation discrete values and the T first signals; wherein the feedback loop is configured to provide, to the phase comparison block, T second distinct logic signals the logic levels of which depend continuously on the phase accumulation values supplied by second phase accumulator according to a second multi-phase correspondence matrix between the T possible phase accumulation discrete values and the T second signals; and wherein the phase comparison block comprises T phase comparators with logic gates receiving respectively in continuous time the T first logic signals on T first comparison inputs and the T second logic signals on T second comparison inputs.

2. The frequency synthesis device according to claim 1, wherein: the servo circuit comprises a first multi-phase converter between the first phase accumulator and the phase comparison block, configured to implement the first multi-phase correspondence matrix; and the feedback loop comprises a second multi-phase converter between the second phase accumulator and the phase comparison block, configured to implement the second multi-phase correspondence matrix.

3. The frequency synthesis device according to claim 2, wherein each of the first and second multi-phase converters implements its multi-phase correspondence matrix in the form a set of logic gates receiving as input a current value of phase accumulation binary coded on ln(T)/ln(2) bits, where ln(.) is the natural logarithm function, and providing at output T current values of logic levels.

4. The frequency synthesis device according to claim 1, wherein each coefficient of each of the first and second multi-phase correspondence matrices is either at a first binary value indicative of a first logic level of logic signal, or at a second binary value indicative of a second logic level of logic signal.

5. The frequency synthesis device according to claim 4, wherein each row or column of each of the first and second multi-phase correspondence matrices, when this row or column indicates the logic levels that must be taken by one of the T first or second logic signals for the T possible phase accumulation discrete values, circularly presents by modulo T only a single transition from the first binary value to the second binary value for a first half of the T possible phase accumulation discrete values and only a single transition from the second binary value to the first binary value for a second half of the T possible phase accumulation discrete values.

6. The frequency synthesis device according to claim 4, wherein each row or column of each of the first and second multi-phase correspondence matrices, when this row or column indicates the logic levels that must be taken by one of the first T or second logic signals for the T possible phase accumulation discrete values, differs from that which precedes or from that which follows only by a shift of a column or respectively a line modulo T of the coefficient values it contains, this shift remaining in the same direction from the first to the last row or column.

7. The frequency synthesis device according to claim 1, wherein each of the first and second correspondence matrices is symmetrical.

8. The frequency synthesis device according to claim 1, wherein the first and second correspondence matrices are identical.

9. The frequency synthesis device according to claim 1, wherein the phase comparison block comprises T charge pumps receiving respectively in continuous time T pairs of pulse signals supplied by the T phase comparators and supplying T output currents in continuous time respectively.

10. The frequency synthesis device according to claim 9, wherein the phase comparison block comprises a current summator receiving in parallel the T output currents supplied by the T charge pumps for supplying a single summed current at the output of the phase comparison block.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The invention will be better understood with the aid of the following description, given solely by way of example and made with reference to the appended drawings wherein:

(2) FIG. 1 schematically represents the general structure of a feedback-loop frequency synthesis device, according to a first embodiment of the invention,

(3) FIG. 2 is a timing diagram illustrating the changes in phase accumulation values obtained using the device of FIG. 1,

(4) FIG. 3 is a timing diagram illustrating the changes in T first or second logic signals provided by the device in FIG. 1, depending on phase accumulation values obtained by unit jumps,

(5) FIG. 4 is a timing diagram illustrating the changes in T first or second logic signals provided by the device in FIG. 1, depending on the phase accumulation values obtained by jumps of three units,

(6) FIG. 5 is a spectrum on a logarithmic scale of frequencies illustrating the characteristics of a signal obtained using the device of FIG. 1,

(7) FIG. 6 is a spectrum on a logarithmic scale of frequencies illustrating the characteristics of another signal obtained using the device of FIG. 1,

(8) FIG. 7 is a diagram indicating a change in frequency resolution of the device in FIG. 1 as a function of a number n of bits coding T possible phase accumulation values,

(9) FIG. 8 schematically represents the general structure of a feedback-loop frequency synthesis device, according to a second embodiment of the invention,

(10) FIG. 9 schematically represents the general structure of a feedback-loop frequency synthesis device, according to a third embodiment of the invention,

(11) FIG. 10 is a spectrum on a logarithmic scale of frequencies illustrating the characteristics of a signal obtained using the device of FIG. 9,

(12) FIG. 11 is a set of three timing diagrams illustrating the evolutions of different quantities of the device of FIG. 1 in startup transient mode,

(13) FIG. 12 is a set of three timing diagrams illustrating the evolutions of different quantities of the device in FIG. 1 in established operating mode,

(14) FIG. 13 represents an example of a loop filter for one or other of the devices in FIGS. 1 and 8,

(15) FIG. 14 represents another example of a loop filter for any of the devices in FIGS. 1, 8 and 9,

(16) FIG. 15 schematically represents the architecture of an example of a phase comparator for any of the frequency synthesis devices of FIGS. 1, 8 and 9,

(17) FIG. 16 is a set of four timing diagrams illustrating the evolutions in the logic signals at the input and at the output of the phase comparator of FIG. 15,

(18) FIG. 17 schematically represents the architecture of an example of a charge pump for any of the frequency synthesis devices of FIGS. 1, 8 and 9,

(19) FIG. 18 schematically represents the architecture of an example of a phase accumulator adapted for the frequency synthesis device of FIG. 1 or 8,

(20) FIG. 19 schematically represents the architecture of an example of a dynamic reduction by Delta-Sigma modulation phase accumulator adapted for the frequency synthesis device of FIG. 9, and

(21) FIG. 20 schematically represents the architecture of an example of a multi-phase converter for any of the frequency synthesis devices of FIGS. 1, 8 and 9.

DETAILED DESCRIPTION

(22) FIG. 1 schematically represents a device 100 for frequency synthesis of the PLL type, according to a first embodiment of the invention. This device 100 has an input intended to receive a periodic signal oscillating at a reference frequency F.sub.ref and an output intended to provide a periodic signal oscillating at an output frequency F.sub.c.

(23) It further comprises a servo circuit 102 for controlling the output frequency F.sub.c by the reference frequency F.sub.ref and a feedback loop 104 for supplying information from the periodic output signal to the servo circuit 102.

(24) More specifically, the servo circuit 102 connects the input to the output of the device 100 and comprises: a first phase accumulator 106 clocked at a frequency linked to the reference frequency F.sub.ref: in the example of FIG. 1, the clock is directly that of the frequency F.sub.ref and the phase accumulator 106 has an integer value phase increment denoted N in an ordered set of T possible phase accumulation discrete values; a first multi-phase converter 108 disposed at the output of the first phase accumulator 106, receiving an encoded value of accumulated phase φ.sub.ref provided by the first phase accumulator 106 and providing T first logic signals whose logic levels depend in continuous time of this phase value φ.sub.ref according to a first multi-phase correspondence matrix between the T possible phase accumulation discrete values and the T first signals: according to a simple and preferred embodiment, T is a power of 2, T=2.sup.n, and the accumulated phase value φ.sub.ref supplied by the first phase accumulator 106 is coded from 1 to T on n bits as illustrated in FIG. 1; a phase comparison block 110 comprising: T phase comparators 112 with logic gates respectively receiving in continuous time the first T logic signals on T first comparison inputs and respectively providing in continuous time T signal pairs “up” and “down”; T charge pumps 114 receiving respectively in continuous time the T pairs of “up” and “down” signals supplied by the T phase comparators 112 and respectively providing in continuous time T output currents; and a current summator 116 receiving in parallel the T output currents supplied by the T charge pumps 114 to supply a single summed current at the output of the phase comparison block 110; a loop filter 118 disposed at the output of the phase comparison block 110 for receiving the summed current: in the example of FIG. 1, it is an analog filter; and a frequency-controlled oscillator 120 arranged at the output of the loop filter 118 and providing the periodic signal that oscillates at the output frequency: in the example of FIG. 1, the oscillator 120 is of VCO type, that is to say controlled by analog voltage supplied by the loop filter 118.

(25) More specifically also, the feedback loop 104 recovers the periodic signal supplied by the oscillator 120 to supply it at the input of a second phase accumulator 122 clocked at a frequency linked to the output frequency F.sub.c: in the example of FIG. 1, the clock is directly that of the frequency F.sub.c and the phase accumulator 122 has an integer value of phase increment denoted D in the aforementioned ordered set of T possible phase accumulation discrete values. The feedback loop 104 further comprises a second multi-phase converter 124 disposed at the output of the second phase accumulator 122, receiving an encoded value of accumulated phase φ.sub.c supplied by the second phase accumulator 122 and supplying T second logic signals whose logic levels depend in continuous time on this phase value φ.sub.c according to a second multi-phase correspondence matrix between the T possible phase accumulation discrete values and the T second signals: according to the simple and preferred implementation mentioned previously, the accumulated phase value φ.sub.c supplied by the second phase accumulator 122 is coded from 1 to T on n bits as illustrated in FIG. 1.

(26) The T second logic signals provided at the output of the second multi-phase converter 124 are respectively received on T second comparator inputs of the phase comparators 112.

(27) In the nonlimiting example of FIG. 1, the multi-phase converters 108 and 124 are shown as devices different from the phase accumulators 106 and 122. But they could alternatively be incorporated in the accumulators, which would then directly supply the T first and second logic signals to the phase comparison block 110.

(28) In practice, it will also be noted that the current summator 116 can be implemented in the simple form of an electrical connection of the T charge pump outputs 114.

(29) A phase accumulator is, in general, a device clocked according to a predetermined clock frequency for incrementing, by a predetermined phase increment value, a digital value supplied at output at each rising or falling edge of the clock.

(30) Thus, as illustrated in FIG. 2 by the dashed line curve for the first phase accumulator 106 (clocked by F.sub.ref and with a phase increment value N), the digital accumulated phase value φ.sub.ref is proportional to a theoretical rectilinear time ramp of slope 2π.Math.N.Math.F.sub.ref. In reality, it is sampled at the frequency F.sub.ref and takes successive digital values N.Math.i at successive times t.sub.j where i is the index of the successive samples.

(31) Thus also, as illustrated in FIG. 2 by the solid line curve for the second phase accumulator 122 (clocked by F.sub.c and with a phase increment value D), the digital accumulated phase value φ.sub.c is proportional to a theoretical rectilinear time ramp of slope 2π.Math.D.Math.F.sub.c. In reality, it is sampled at the frequency F.sub.c and takes successive digital values D.Math.j at successive times t.sub.j where j is the index of the successive samples.

(32) In theory, at each instant t:
[(φ.sub.ref−φ.sub.c](t)=2π.Math.t.Math.(N.Math.F.sub.ref−D.Math.F.sub.c).  [Math. 1]

(33) Using the phase comparison block 110, when the PLL is locked, the relationship F.sub.c=α.Math.F.sub.ref=N/D.Math.F.sub.ref is found theoretically.

(34) But in practice, the instants t and t are not synchronized with one another and do not allow a direct comparison of the samples of accumulated phases.

(35) It is therefore advantageous and clever to: continuously convert the accumulated phase digital value φ.sub.ref into T first distinct logic signals using the first multi-phase converter 108 (or directly in the phase accumulator 106), continuously convert the accumulated phase digital value φ.sub.c into T second distinct logic signals using the second multi-phase converter 124 (or directly in the phase accumulator 122), and compare the 2T resulting logic signals two by two using the phase comparison block 110 with T logic comparators in continuous time and T charge pumps whose outputs are summed.

(36) Indeed, by proceeding in this way by multi-phase conversions rather than by an attempt to resynchronize samples of accumulated phases, or rather than by a direct comparison of phases of analog signals without prior calculation of these phases, a phase comparison completely independent of the update frequencies of the phase accumulation values to be compared is obtained. It therefore becomes possible to design a frequency synthesis device with a multiplying factor α=N/D with a high value for D, therefore with high frequency resolution, without detrimental consequences on the establishment of the operating mode and on the phase noises or others.

(37) According to the embodiment detailed above, the digital values of accumulated phases φ.sub.ref and φ.sub.c are respectively incremented with values N and D for each rising or falling edge of the corresponding clock, that is to say at instants t.sub.j for the digital value representing the accumulated phase φ.sub.ref and at instants t.sub.j for the digital value representing the accumulated phase φ.sub.c. If nothing else was planned, these numerical values would be destined to grow indefinitely, which would then raise a problem of saturation of the accumulators. But the coding of values φ.sub.ref and φ.sub.c on a limited number n of bits and the multi-phase conversion carried out using a correspondence matrix with limited number T of rows and columns allow implicitly to realize a circular increment at modulo T of the values N and D according to which as soon as the T-th phase value is reached among the T possible values, one returns automatically to the first.

(38) An example of multi-phase conversion for T=10 is illustrated by FIGS. 3 and 4 according to the following correspondence matrix, for example common to the first and second multi-phase converters:

(39) TABLE-US-00001 TABLE 1 φ s <9:0> 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 2 1 1 1 0 0 0 0 0 1 1 3 1 1 0 0 0 0 0 1 1 1 4 1 0 0 0 0 0 1 1 1 1 5 0 0 0 0 0 1 1 1 1 1 6 0 0 0 0 1 1 1 1 1 0 7 0 0 0 1 1 1 1 1 0 0 8 0 0 1 1 1 1 1 0 0 0 9 0 1 1 1 1 1 0 0 0 0

(40) T=10 phase accumulation discrete values are possible and encoded from 0 to 9. For each of these encoded values, the corresponding line of the correspondence matrix above indicates a logic level for each of the T logic signals constituting the digital signal s<9:0>, ordered in columns from s<9> to s<0>. In an advantageous embodiment, this logic level is binary, the logic signal being either at a first level denoted “0”, or at a second level denoted “1”.

(41) FIG. 3 is thus a timing diagram illustrating the time trends of the T first or second logic signals s<0> to s<9> provided by the first or second multi-phase converter 108 or 124 using the correspondence matrix above, depending on phase accumulation values φ=φ.sub.ref or φ.sub.c successively obtained by unitary jumps, that is to say for N or D equal to 1. More precisely, in this timing diagram φ successively takes the values 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1, . . . .

(42) FIG. 4 is a timing diagram illustrating the time trends of the T first or second logic signals s<0> to s<9> supplied by the first or second multi-phase converter 108 or 124 using the same correspondence matrix above, depending on phase accumulation values φ=φ.sub.ref or φ.sub.c successively obtained by jumps of three units, that is to say for N or D equal to 3. More precisely, in this chronogram φ successively takes the values 0, 3, 6, 9, 2, 5, 8, 1, 4, 7, 0, . . . .

(43) More generally and by convention, each multi-phase correspondence matrix comprises T lines representative of the T possible phase accumulation discrete values and T columns representative of the T logic signals. According to another convention, it could comprise T columns representative of the T possible phase accumulation discrete values and T rows representative of the T logic signals. Advantageously, it is symmetrical, so that this convention is completely indifferent.

(44) As shown in FIGS. 3 and 4, in order to have the logic signals resulting from multi-phase conversions fully relevant to compare two by two, it is advantageous that each column of each multi-phase correspondence matrix, each column indicating by convention the logic levels which one of the T resulting logic signals must take for the T possible phase accumulation discrete values, presents circularly by modulo T only a single transition from the first binary logic value to the second binary logic value for a first half of the T possible phase accumulation discrete values and only a single transition from the second binary logic value to the first binary logic value for a second half of the T possible phase accumulation discrete values. It is also advantageous that each column differs from the one preceding or from that which follows only by a shift of a line modulo T of the coefficient values that it contains, this shift remaining in the same direction from the first to the last column.

(45) On a spectral point of view, before the multi-phase conversion of the phase accumulation values provided by the two phase accumulators 106 and 122, the two digital signals received by the phase comparators 112 of phase comparison block 110 have a frequency response very close to a straight line which starts from the zero frequency and which decreases with the frequency.

(46) In this regard, FIG. 5 illustrates, on a logarithmic frequency scale, the frequency response of one of the digital signals resulting from the accumulation of a phase ramp generated by a phase accumulator sampled by a clock signal of frequency F.sub.H equal to 1 MHz. The spectrum illustrated in this figure is thus parasitized by the frequency F.sub.H and its harmonics, a phenomenon which is well known to those skilled in the art. However, the equivalent sampling carried out by the phase accumulator does not generate spectrum aliasing or quantization noise because it is applied identically to each rising or falling edge of the clock.

(47) Furthermore, as the logic comparison carried out by each phase comparator 112 is a linear operation in continuous time, the spectrum of the result of this operation is a subtraction of the spectra of the two digital signals resulting from the phase accumulation values φ.sub.ref and φ.sub.c without adding additional noise.

(48) FIG. 6 thus illustrates, on a logarithmic scale of frequencies, the resulting spectrum at the output of the current summator 116 for the experimental values of FIG. 5. When the PLL loop stabilizes, the straight lines of the frequency responses tend to compensate each other (here at −140 dB). Only the parasitic peaks of the fundamental frequencies F.sub.ref, F.sub.c and their harmonics emerge. When the multiplying factor α is greater than 1, the first parasitic peak is at the frequency F.sub.ref while in a conventional frequency synthesis device with integer division and frequency dividers, it would be at the frequency F.sub.ref/D. This is an important improvement which makes it possible either to increase the cut-off frequency of the frequency synthesis device under the condition of stability by thereby improving the time Δt for establishing its operating mode, or to much better attenuate interference and phase noise without deteriorating this time Δt.

(49) It also clearly appears that the frequency synthesis device 100 as described above makes it possible to obtain a multiplying factor α=N/D with a high value for D and therefore with high frequency resolution. Indeed, the phase accumulators 106 and 122 can easily be implemented with means for storing numbers encoded in binary form, in particular for positive integer values such as N and D. They must therefore just provide a sufficient number of bits for performing the arithmetic operations of accumulation of N and D in the set of T possible phase accumulation values. This number n must be greater than or equal to the number of bits necessary to represent, not only N and D, but also T.

(50) As a conclusion, the minimum number of bits necessary at the output of accumulators 106 and 122 can be defined by the following relation, an additional bit being necessary because of the multi-phase conversion:
n=ENT[log.sub.2(MAX(N−1,D−1))]+2,  [Math. 2]
where ENT[ ] is the Floor Part function, ENT[ ]+1 then representing the Ceiling Part function, and where MAX ( ) is the function which returns the maximum between two values.

(51) In accordance with these calculations, the possibilities for choosing the values of D and N for given values of α and F.sub.ref only depend on n. For n=32 for example, D can go up to 2.sup.31−1 (ditto for N), where a conventional integer frequency synthesis device has values of D limited to 100 or 1000. As shown by FIG. 7, which illustrates the frequency resolution as a function of the number of bits of D for F.sub.ref=20 MHz, this is a significant increase in the frequency resolution of the possible variations F.sub.ref/D of the multiplying factor α that a device according to the invention can reach as a function of n. The resolution of a fractional steps frequency synthesis device may even be exceeded. For example, for a 10 MHz reference signal and n=32, the resolution in frequency is better than 0.005 Hz.

(52) Conversely, for a given frequency resolution, since it is equal to F.sub.ref/D, it is possible to increase F.sub.ref with D. This is useful for lowering the contribution of the reference signal to the phase noise at the output in the bandwidth of the frequency synthesis device. Indeed in such a device, this contribution is directly due to the function of multiplying the reference frequency by the multiplying factor α. More precisely, in the bandwidth, the contribution of the phase noise of the reference signal is increased by 20.Math.log (α) in decibels. It is then advantageous to decrease a and therefore to increase F.sub.ref for a given F.sub.c.

(53) FIG. 8 diagrammatically represents a frequency synthesis device 200 of the PLL type, according to a second embodiment of the invention. This device 200 differs from device 100 in that it includes a frequency divider 202, disposed in the feedback loop 104 between the output and the second phase accumulator 122, and in that the phase increment value of the first phase accumulator 106 is adapted as a function of the value of the division factor of this frequency divider 202 for a desired servo factor of the output frequency F.sub.c by the reference frequency F.sub.ref. More precisely, the value N is split into a product of two values N.sub.a and N.sub.d, N=N.sub.a.Math.N.sub.d, N.sub.a representing the value of phase increment of the first phase accumulator 106 and N.sub.d the dividing factor of the frequency divider 202. We thus keep the relation F.sub.c=α.Math.F.sub.ref=N/D.Math.F.sub.ref=N.sub.a. N.sub.d/D.Math.F.sub.ref. Finally, it will be noted that the device 200 also differs from the device 100 in that the second phase accumulator 122 is no longer directly clocked at the output frequency F.sub.c, but at the reduced frequency F.sub.c/N.sub.d which however remains linked to F.sub.c.

(54) The advantage of this second embodiment compared to the previous one is to avoid too great a difference between the phase increment values of the two phase accumulators 106 and 122 by splitting the value of N into two integer factors. Indeed, knowing that it is often desired to have a multiplying factor α much greater than 1, the value of N is often much greater than that of D, so that, according to the calculation carried out previously with reference to the first two embodiment of FIGS. 1 and 3, the minimum number n=ENT[log.sub.2(MAX(N−1,D−1))]+2 is still dominated by the value of N and not by that of D. In this way, a certain number of bits for implementing the value D remain useless, all the more so when the factor α is large. However, useless implementation bits mean as many logic gates which consume power unnecessarily.

(55) In the second embodiment of FIG. 8, the calculation of n becomes:
n=ENT [log.sub.2(MAX(N.sub.a−1,D−1))]+2.  [Math. 3]

(56) Since N.sub.a is less than N, the number of useless implementation bits is reduced. Advantageously, the division factor N.sub.d can even be chosen so that, for a desired servo factor of the output frequency by the reference frequency α=N/D, the phase increment value D of the second phase accumulator 122 can be chosen as close as possible to the phase increment value N.sub.a of the first phase accumulator 106 while remaining less than or equal to the latter. In this case, few implementation bits are useless and the architecture is optimized in terms of power consumption. The clock frequencies F.sub.ref and F.sub.c/N.sub.d of the two phase accumulators 106 and 122 also become close to each other, that of the second phase accumulator 122 being slowed down so as to further reduce consumption. This reduction is also not offset by the addition of the frequency divider 202. The optimum is reached for ENT[log.sub.2(N.sub.a−1)]=ENT[log.sub.2(D−1)]=n−2. However, it is not interesting that the value N.sub.a is less than D, because in this case the first parasitic frequency in the output spectrum would no longer be F.sub.ref but F.sub.c/N.sub.d. This would then result in either a degradation of the time Δt for establishing the operating mode, or a degradation of the attenuation of the parasitic frequencies, depending on the cutoff frequency chosen for the loop filter 118.

(57) The counterpart of this improvement in consumption is a frequency resolution loss which becomes F.sub.ref.Math.N.sub.d/D rather than F.sub.ref/D. It is therefore degraded by a factor N.sub.d.

(58) FIG. 9 schematically represents a device frequency synthesis 300 of the PLL type, according to a third embodiment of the invention. This device 300 differs from device 200 in that each multi-phase converter 108 or 124 is preceded by a dynamic reduction device by quantization. More precisely, this reduction in dynamics is for example carried out using a quantizer with Delta-Sigma modulation. Thus, a first Delta-Sigma modulation quantizer 302 is disposed between the first phase accumulator 106 and the first multi-phase converter 108. Similarly, a second Delta-Sigma modulation quantizer 304 is disposed between the second phase accumulator 122 and the second multi-phase converter 124.

(59) This embodiment has the advantage of facilitating the implementation of the phase comparison block 110 by reducing the number of logic signals to be processed. Indeed, without reduction of dynamic range by quantization, for accumulated phase values coded on n bits at the output of the phase accumulators, the number of phase comparators 112 and charge pumps 114 is T=2.sup.n to process the 2T=2.sup.n+1 signals from the multi-stage converters 108 and 124. This number can become very large when n increases, that is to say when the frequency resolution is large.

(60) Thus, the reduction in dynamics allows a reduction in the number of bits taken into account in the multi-phase converters, making the number of logic signals which they produce lower and the phase comparison block 110 which receives them simpler to make.

(61) In general, to reduce the number of bits supplied at the input of multi-phase converters, the simplest solution consists in truncating the values to be converted on a number of bits n′ less than n by removing the least significant bits. This truncation is mathematically equivalent to a new quantization of digital data. This quantization produces an error which is generally assimilated to noise, known as quantization noise. This noise has a fairly random spectrum but is often approached by a flat spectrum of white noise. The multi-phase converters then only need to convert n′ bits into 2.sup.n′ logic signals at the cost of interferences which can be assimilated to additional noise in the output spectrum of the frequency synthesis device. Due to frequency control, this noise is mainly found around the cutoff frequency of the device, its standard deviation decreasing when n′ increases.

(62) The advantage of using a Delta-Sigma modulation quantizer to achieve dynamic reduction is to reduce this quantization noise, since the phase comparison block 110 is followed by a low-pass filter, in this case the loop filter 118. Indeed, the Delta-Sigma modulation function distorts the spectrum of quantization noise by generating less noise at low frequency and more noise at high frequency close to F.sub.ref and F.sub.c/N.sub.d. This noise is then better filtered by the loop filter 118 if the frequencies F.sub.ref and F.sub.c/N.sub.d are sufficiently large compared to the cut-off frequency of the device. It will be noted that in practice the order of the filter must be strictly greater than that of the Delta-Sigma modulation. In this third embodiment, the loop filter 118 is therefore at least of order 2, knowing that in addition it cannot be of too high order, that is to say that it advantageously remains of order less than or equal to 3.

(63) By way of nonlimiting example, a Delta-Sigma modulation quantizer of order 1 is very simple to implement because it is always stable. It can consist of an adder followed by a register of n bits, the output of which is truncated by taking the n′ most significant bits while the (n−n′) remaining least significant bits are completed by 0s in most significant bits to obtain new data on n bits at the input. The value of the new data thus created represents the fraction which has been truncated at the output of the register. This value is added to the current input data item on n bits and the result is recorded in the register for the next cycle. This is how the delta-sigma modulation quantizer never erases the quantization error, but defers it in time

(64) FIG. 10 illustrates, on a logarithmic frequency scale, the frequency response of a digital signal resulting from: a phase ramp generated by a phase accumulator subjected to a clock signal of frequency F.sub.H equal to 1 MHz, and a reduction in dynamic range by quantization performed at the output of the accumulator using a Delta-Sigma modulation quantizer.

(65) In addition to be parasitized by the frequency F.sub.H and its harmonics, the spectrum shown in this figure shows a quantization noise carried mainly around its parasite frequencies, without substantial change at low frequencies when compared to the spectrum of FIG. 5. This noise is intended to be filtered by the loop filter 118, and this all the better for F.sub.ref is large relative to the cut-off frequency of the device. Since a frequency synthesis device according to the invention makes it possible to easily increase the reference frequency with a constant multiplying factor α, it also stands out from the point of view of the use of a Delta-Sigma modulation, of a fractional step frequency synthesis device in which this reference frequency is more difficult to increase.

(66) FIG. 11 illustrates three timing diagrams of a transient mode startup of the frequency synthesis device 100, that is to say without frequency divider 202 and without Delta-Sigma modulation quantizer 302 or 304, for a ratio α=3/2, a loop filter of order 2 and T=16. The first timing diagram shows the evolution of the phase accumulation values φ.sub.ref and φ.sub.c whose ramps end up synchronizing before 3.Math.10.sup.−5 seconds. The second timing diagram shows the stabilization of the summed current ΣI at the output of the current summator 116 at the same time. The third timing diagram shows the convergence of the analog voltage V supplied by the loop filter 118 to the VCO oscillator 120 towards a stabilization value at the same time. The voltage V.sub.0 is an internal voltage of the loop filter 118 which is indicated in FIG. 14.

(67) FIG. 12 illustrates the same three chronograms in steady state of the frequency synthesis device 100, that is to say from 3.Math.10.sup.−5 seconds, according to a finer time scale. It can be noticed more clearly the synchronization of the phase ramps φ.sub.ref and φ.sub.c, as well as the stabilized convergence of ΣI and V. The small remaining variations correspond to the residual interferences of the clock frequencies F.sub.ref and F.sub.c after filtering by the filter loop 118.

(68) It clearly appears that a frequency synthesis device such as one of those described above has at least some of the following advantages, that of the third embodiment detailed above combining them all: high resolution in frequency for setting the output signal can be achieved and is practically not dependent on the reference frequency, contrary to fractional steps frequency synthesis devices, this high resolution in frequency is not obtained at the expense of a phase noise injected into the output signa, it behaves like a conventional integer-division frequency synthesis device with a very similar transfer function, so that its study is simplified, The frequency F.sub.ref of the reference signal may be as large as desired, its contribution to the total phase noise at the output, 20.Math.log(α), being reduced accordingly for a given output frequency F.sub.c, the spurious signals present in the output spectrum are shifted towards the high frequencies, so that they are better filtered by the loop filter, its cut-off frequency can be increased within the limits of stability, so that the time to establish its operating mode can be reduced, the frequency resolution does not depend on the number T of phase comparators 112 and charge pumps 114 used in the phase comparison block 110, and no subtraction of modulo value and/or synchronization between the phase accumulators 106 and 122 is necessary.

(69) In terms of industrial application, any of the devices described above can be integrated into any device requiring frequency synthesis, such as for example a radio frequency receiver or transmitter, a clock for clocking digital, analog or mixed (i.e. analog and digital) circuits, a clocked measurement system, a time base, etc.

(70) Concrete examples of electronic architectures for each of the functional elements constituting the frequency synthesis devices described above will now be given.

(71) FIG. 13 illustrates an example of order 1 filter which can be chosen to produce the loop filter 118 of one or other of the frequency synthesis devices of FIGS. 1 and 8. This order 1 filter receives the summed analog current ΣI from the phase comparison block 110 as input and supplies the analog control voltage V to the VCO oscillator 120 as output. It further comprises a first capacitive circuit C.sub.0 connecting the input to ground to perform an integration function by inserting a pole at zero frequency (PLL type II). It further comprises a second resistive and capacitive circuit R.sub.1, C.sub.1 connecting the output to ground to create a phase margin by inserting a zero at low frequency. This order 1 filter cannot be used in the frequency synthesis device of FIG. 9 since it cannot be of order strictly higher than that of the Delta-Sigma quantizers 302 and 304.

(72) FIG. 14 illustrates an example of order 2 filter which can be chosen to make the loop filter 118 of any of the frequency synthesis devices of FIGS. 1, 8 and 9. This order 2 filter differs from the filter of FIG. 13 in that a third resistive circuit R.sub.2 is interposed between the second circuit R.sub.1, C.sub.1 and the output, and in that a fourth capacitive circuit C.sub.2 connects the output to ground. These two additional circuits add a pole beyond the cut-off frequency of the filter.

(73) FIG. 15 schematically represents the general architecture, in terms of logic gates, of an example of phase comparator 112 adapted for the frequency synthesis device of FIG. 1, 8 or 9.

(74) This phase comparator has a first comparison input which receives one of the T first logic signals supplied by the first multi-phase converter 108. This signal is denoted s.sub.ref(i), with 0≤i<T, and its logic level is updated at the frequency F.sub.ref. The comparator has a second comparison input which receives one of the T second logic signals supplied by the second multi-phase converter 124, more precisely that of the same index as s.sub.ref(i). This signal is noted s.sub.c(i) and its logic level is updated at the frequency F.sub.c (or F.sub.c/N.sub.d).

(75) The first logic signal s.sub.ref(i) is received at the input of a NAND logic gate 400 whose output is supplied at the input of a NAND logic gate 402 of a first RS flip-flop having two NAND logic gates 402 and 404. The output of NAND logic gate 402 provides the “up” signal of the phase comparator 112 and is further returned to the input of NAND logic gate 404. The output of the NAND logic gate 404 is supplied at the input of a NAND logic gate 406 of a second RS flip-flop having two NAND logic gates 406 and 408 and is further returned to the input of the NAND logic gate 402. The output of the NAND logic gate 406 is returned to the input of the NAND logic gate 408. The output of the NAND logic gate 408 is returned to the input of the NAND logic gate 406 and is further supplied at the input of the NAND logic gate 400. Finally, the first logic signal s.sub.ref(i) is also received at the input of the NAND logic gate 408.

(76) The second logic signal s.sub.c(i) is received at the input of a NAND logic gate 410 whose output is supplied at the input of a NAND logic gate 412 of a third flip-flop RS having two NAND logic gates 412 and 414. The output of NAND logic gate 412 provides the “down” signal of the phase comparator 112 and is further returned to the input of NAND logic gate 414 The output of the NAND logic gate 414 is supplied at the input of a NAND logic gate 416 of a fourth flip-flop RS having two NAND logic gates 416 and 418 and is further returned to the input of the NAND logic gate 412. The output of the NAND logic gate 416 is returned to the input of the NAND logic gate 418. The output of the NAND logic gate 418 is returned to the input of the NAND logic gate 416 and is further supplied at the input of the NAND logic gate 410. Finally, the second logic signal s.sub.c(i) is also received at the input of the NAND logic gate 418.

(77) The “up” and “down” signals are further supplied at the input of a NAND logic gate 420, the output of which is supplied at the inputs of the NAND logic gates 404 and 414 via a YES logic gate 422 (equivalent to a double NO logic gate).

(78) FIG. 16 illustrates an example of a resulting timing diagram in which F.sub.ref=25 MHz and F.sub.c=30 MHz. In this type of comparator, the measured phase error is proportional to the width of the pulses generated on the “up” and “down” signals.

(79) FIG. 17 schematically represents the general architecture of an example of a charge pump 114 adapted for the frequency synthesis device of FIG. 1, 8 or 9.

(80) It receives the “up” signal at the input of a YES logic gate 500, the “down” signal at the input of a NO logic gate 502 and is biased by a current generator I.sub.CP 504. This current generator I.sub.CP 504 supplies a first current mirror 506 having two n-MOS transistors which copies the current I.sub.CP on a n-MOS output transistor 508. It also feeds a second current mirror 510 with two p-MOS transistors, one of which, called the output, is connected by its drain to the output of the YES logic gate 500. The drain of the n-MOS output transistor 508 is connected to the output of the NO logic gate 502. The output current I is taken between the output n-MOS transistor 508 and the output p-MOS transistor of the second current mirror 510.

(81) In operation, the current I.sub.CP is copied by the first current mirror 506 on the output n-MOS transistor 508 when it is activated, that is to say when the “down” signal is at level “1”, and on the output p-MOS transistor of the second current mirror 510 when it is activated, that is to say when the signal “up” is at level “1”. When the signals “up” and “down” are both at level “1” at the same time, the currents of the output n-MOS and p-MOS transistors cancel each other at output I.

(82) FIG. 18 schematically represents the general architecture of an example of phase accumulator 106 or 122 adapted for the frequency synthesis device of FIG. 1 or 8. This example is in particular adapted to a specific case according to which the values of phase increments N (or N.sub.a) and D are coded on 4 bits and the registers In, Out occupy 4 bits of memory. The input register In stores the configuration value N (or N.sub.a) for the phase accumulator 106 and the configuration value D for the phase accumulator 122.

(83) This architecture includes a storage register 600 with four synchronous flip-flops clocked by the clock frequency F.sub.H (F.sub.ref for the phase accumulator 106 and F.sub.c for the phase accumulator 122). The four binary outputs of this register 600 feed the four bits Out<0>, Out<1>, Out<2>, Out<3> of the output register Out. The four binary inputs of this register 600 are supplied by a 4-bit adder 602 with four binary addition modules connected together in a conventional manner to carry out a 4-bit addition. The four bits In<0>, In<1>, In<2>, In<3> of the input register In feed four respective inputs of the binary addition modules of the adder 602, which also receive the four binary outputs of the storage register 600 to carry out the accumulation operation. The outputs of the four binary addition modules are supplied to the respective inputs of the four synchronous flip-flops of the storage register 600. It is noted that the modulo function of each phase accumulator 106, 122 is implicitly carried out by not using the carry of the most significant adder.

(84) The architecture of each phase accumulator 106 or 122 is thus greatly simplified compared to that which must be envisaged in the patent document U.S. Pat. No. 9,509,320 B2.

(85) FIG. 19 schematically represents the general architecture of an example of phase accumulator 106 or 122 combined with a Delta-Sigma quantizer 302 or 304, adapted for the frequency synthesis device of FIG. 9. This example is in particular adapted to the specific case according to which the values of phase increments N (or N.sub.a) and D are coded on 4 bits and the register In occupies 4 bits of memory. The input register In stores the configuration value N (or N.sub.a) for the phase accumulator 106 and the configuration value D for the phase accumulator 122.

(86) In accordance with this example, the phase accumulation function is performed by the storage register 600 and the 4-bit adder 602, arranged as previously in the example of FIG. 18. The dynamic reduction function using a Delta-Sigma modulation quantizer is performed by an additional 4-bit adder 700 and by an additional storage register 702, these two modules being interposed between the storage register 600 and the output Out reduced to 2 bits.

(87) More specifically, the additional adder 700 comprises four binary addition modules connected together in a conventional manner to perform an addition on 4 bits. The four output bits of the adder 602 feed four respective inputs of the binary addition modules of the additional adder 700, which also receive either 0s or outputs from the additional storage register 702 as a function of the desired reduction in dynamics.

(88) For example, to obtain the output register Out on 2 bits Out<0>, Out<1>, the additional storage register 702 comprises four synchronous flip-flops clocked by the clock frequency F.sub.H, among which: the first two synchronous flip-flops relating to the two least significant bits receive the respective outputs of the two binary addition modules of these two bits in order to supply them again with these input values at the next clock pulse, and both of the following synchronous flip-flops relating to the two most significant bits receive the respective outputs of the two binary addition modules of these two bits for outputting values for the register Out.

(89) The two binary addition modules relating to the two most significant bits receive 0s.

(90) The bit Out<1> is determined by the output of the fourth synchronous flip-flop of the additional storage register 702.

(91) Finally, the bit Out<0> is determined by the output of the third synchronous flip-flop of the additional storage register 702.

(92) Thus, an always stable quantizer on 2 bits with order 1 Delta-Sigma modulation is obtained. The two most significant bits which have been truncated represent the rounded output and are replaced by zeros on the corresponding inputs of the additional adder 700. For these bits, the addition thus only consists in adding and propagating the carry of the least significant bit. In this way the result is the sum of the current accumulated phase value over 4 bits and the fraction over 2 bits subtracted from the previous result delayed by a clock period. It is indeed the full amount of the quantization error, which is the principle of a Delta-Sigma modulation. When using such an architecture to implement the Sigma-Delta modulation quantizers 302 and 304, it is advantageous to use the architecture of FIG. 14 to implement the loop filter 118.

(93) FIG. 20 schematically represents the general architecture, in terms of logic gates, of an example of multi-phase converter 108 or 124 adapted for the frequency synthesis device of FIG. 1, 8 or 9. This example is in particular adapted to the specific case according to which the phase accumulation values are coded on n or n′=5 bits for a number T=2.sup.5=32 of logic signals at the output of the converter, according to the following correspondence matrix:

(94) TABLE-US-00002 TABLE 2 φ s <31:0> 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 3 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 4 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 5 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 6 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 7 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 8 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 9 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 10 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 11 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 12 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 13 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 14 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 15 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 19 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 20 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 21 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 22 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 23 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 24 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 25 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 26 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 27 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 28 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 29 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 30 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

(95) Let us note φ<4:0> one of the T=32 possible phase accumulation values binary coded on ln(T)/ln(2)=5 bits φ<0> to φ<4> and s<31:0> the 32 resulting logic signals.

(96) At a first level N1 of the multi-phase converter 108 or 124, a NOR logic gate 800 receives the bits φ<0> and φ<1> to supply a logic value of an intermediate logic signal s.sub.A<0>. A NON logic gate 802 receives the bit φ<1> to supply a logic value of an intermediate logic signal s.sub.A<1>. A NAND logic gate 804 receives the bits φ<0> and φ<1> to supply a logic value of an intermediate logic signal s.sub.A<2>. A logic value of an intermediate logic signal s.sub.A<3> is set to “1”. A NON logic gate 806 receives the bit φ<2>.

(97) At a second level N2 of the multi-phase converter 108 or 124, four NAND logic gates 808 respectively receive the four logic values of the four intermediate logic signals s.sub.A<3:0> and the output of the NO gate logic 806 to respectively supply four logic values of four intermediate logic signals s.sub.B<3:0>. Four NOR logic gates 810 respectively receive the four logic values of the four intermediate logic signals s.sub.A<3:0> and the output of the NO logic gate 806 to respectively supply four logic values of four intermediate logic signals 5.sub.B<7:4>.

(98) At a third level N3 of the multi-phase converter 108 or 124, eight NOR logic gates 812 respectively receive the eight logic values of the eight intermediate logic signals s.sub.B<7:0> and the bit φ<3> to respectively supply eight logic values of eight intermediate logic signals s.sub.C<7:0>. Eight NAND logic gates 814 respectively receive the eight logic values of the eight intermediate logic signals s.sub.B<7:0> and the bit φ<3> to respectively supply eight logic values of eight intermediate logic signals s.sub.C<15:8>. A NON logic gate 816 receives the bit φ<4>.

(99) Finally, at a fourth level N4 of the multi-phase converter 108 or 124, sixteen XOR logic gates 818 receive respectively the sixteen logic values of the sixteen intermediate logic signals s.sub.C<15:0> and the bit φ<4> to respectively supply the sixteen logic values of sixteen logic signals s<15:0>. Sixteen other XOR logic gates 820 receive respectively the sixteen logic values of the sixteen intermediate logic signals s.sub.C<15:0> and the output of the NO logic gate 816 to supply respectively the sixteen logic values of the sixteen logic signals s<31:16>.

(100) With regard to the general architectures of the frequency-controlled oscillator 120 and the frequency divider 202, these are well known and will not be detailed. The oscillator 120 is for example a voltage-controlled oscillator formed of an inductor placed in parallel with two varactors arranged head to tail and two NMOS transistors whose gates are mounted head to tail so as to generate a sufficient gain to initiate and then maintain the oscillation across the inductor, these transistors being polarized by the current from the power supply of the midpoint of the inductor.

(101) Note also that the invention is not limited to the embodiments described above. It will appear to those skilled in the art that various modifications can be made to the embodiments described above, in the light of the teaching which has just been disclosed to them. In the detailed presentation of the invention which has been made previously, the terms used should not be interpreted as limiting the invention to the embodiments set out in this description, but must be interpreted to include all the equivalents the prediction of which is within the reach of those skilled person by applying their general knowledge to the implementation of the teaching which has just been disclosed to them.