Time measurement circuit, system having a PWM signal generator circuit and a time measurement circuit, and corresponding integrated circuit

Abstract

A time measurement includes a multiphase clock generator and a phase sampling circuit. The multiphase clock generator generates a sequence of a given number n of phase shifted clock phases, wherein one of the phase shifted clock phases represents a reference clock signal. The phase sampling circuit is configured to generate a phase value indicative of a number of fractions 1/n of the clock period of the clock phases elapsed between an edge of the reference clock signal and an instant when an asynchronous event signal is set. The phase sampling circuit includes first through fourth sub-circuits, which respectively generate or determine first through fourth control signals.

Claims

1. A time measurement circuit configured to generate a phase value, the time measurement circuit comprising: a multiphase clock generator configured to generate a sequence of a given number n of phase shifted clock phases having a same clock period and being phase shifted by a time corresponding to a fraction 1/n of said clock period, wherein one of said phase shifted clock phases represents a reference clock signal; a node configured to receive an asynchronous event signal; a phase sampling circuit configured to generate said phase value, said phase value being indicative of a number of said fractions 1/n of said clock period elapsed between an edge of said reference clock signal and an instant when said asynchronous event signal is set.

2. The time measurement circuit according to claim 1, wherein said phase sampling circuit includes: a first sub-circuit including for each of said phase shifted clock phases a respective first flip-flop configured to, in response to said asynchronous event signal, sample the respective phase shifted clock phase, thereby determining a respective first control signal indicating whether the respective clock phase was set to high or low at the instant when said asynchronous event signal was set; a second sub-circuit including for each of said phase shifted clock phases a respective second flip-flop configured to, in response to the respective phase shifted clock phase, sample the respective first control signal, thereby determining a respective second control signal corresponding to a synchronized version of the respective first control signal; a third sub-circuit configured to: associate with each of said phase shifted clock phases a further clock phase, said further clock phase corresponding to the phase shifted clock phase of said sequence of phase shifted clock phases preceding the respective clock phase with said time; determine for each of said phase shifted clock phases a respective third control signal indicating whether: the second control signal associated with the respective phase shifted clock phase indicates that the respective phase shifted clock phase was set to low at the instant when said asynchronous event signal was set, and the second control signal associated with the respective further clock phase indicates that the respective further clock phase was set to high at the instant when said asynchronous event signal was set; and a fourth sub-circuit including for each of said phase shifted clock phases a respective third flip-flop configured to, in response to the respective phase shifted clock phase, sample the respective third control signal, thereby determining a respective fourth control signal corresponding to a synchronized version of the respective third control signal.

3. The time measurement circuit according to claim 2, wherein: each of said first flip-flops is configured to sample the respective phase shifted clock phase in response to a rising edge of said asynchronous event signal; and each of said second flip-flops is configured to sample the respective first control signal in response to a falling edge of the respective phase shifted clock phase.

4. The time measurement circuit according to claim 2, including for each of said phase shifted clock phases a respective logic OR gate configured to receive at input the respective first control signal provided by said respective first flip-flop and the respective second control signal provided by said respective second flip-flop, thereby determining a respective fifth control signal, and wherein each of said second flip-flops is configured to sample the respective fifth control signal, whereby each of said second flip-flops samples the respective first control signal only when the respective first control signal is set to high.

5. The time measurement circuit according to claim 2, wherein said third sub-circuit includes for each of said phase shifted clock phases a respective logic AND gate, each logic AND gate configured to receive at input an inverted version of the second control signal associated with the respective phase shifted clock phase, and the second control signal associated with the respective further clock phase, thereby generating the respective third control signal.

6. The time measurement circuit according to claim 2, wherein: each of said third flip-flops is configured to sample the respective third control signal in response to a rising edge of the respective phase shifted clock phase.

7. The time measurement circuit according to claim 2, wherein said first, second and third flip-flops are configured to be reset via a reset signal.

8. The time measurement circuit according to claim 2, wherein a further flip-flop is connected in cascade with each of said second or said third flip-flops.

9. The time measurement circuit according to claim 2, wherein said fourth control signals represents a one-hot encoding of said phase value.

10. The time measurement circuit according to claim 2, wherein said reference clock signal is selected among said phase shifted clock phases as a function of a selection signal, and wherein said phase value is determined as a function of said fourth control signals and said selection signal.

11. The time measurement circuit according to claim 1, comprising: a counter circuit configured to increase a count value in response to said reference clock signal; and a counter sampling circuit configured to generate a sampled count value by sampling said count value.

12. The time measurement circuit according to claim 11, wherein said counter sampling circuit comprises: a first sampling circuit configured to, in response to a rising edge of said reference clock signal, sample said asynchronous event signal, thereby generating a first synchronized asynchronous event signal; a second sampling circuit configured to, in response to a falling edge of said reference clock signal, sample said asynchronous event signal, thereby generating a second synchronized asynchronous event signal; and a sampling circuit configured to, in response to a rising edge of said reference clock signal, store either the count value of said counter circuit or the count value of said counter circuit decreased by one as a function of said first and said second synchronized asynchronous event signal, thereby generating said sampled count value.

13. A system, comprising: a time measurement circuit, including: a multiphase clock generator configured to generate a sequence of a given number n of phase shifted clock phases having a same clock period and being phase shifted by a time corresponding to a fraction 1/n of said clock period, wherein one of said phase shifted clock phases represents a reference clock signal; a node configured to receive an asynchronous event signal; a phase sampling circuit configured to generate a phase value, said phase value being indicative of a number of said fractions 1/n of said clock period elapsed between an edge of said reference clock signal and an instant when said asynchronous event signal is set; a counter circuit configured to increase a count value in response to said reference clock signal; and a counter sampling circuit configured to generate a sampled count value by sampling said count value; and a Pulse-Width Modulated (PWM) signal generator circuit configured to generate a Pulse Width Modulated signal as a function of the count value of said counter circuit, wherein said sampled count value and said phase value are indicative of a number of clock cycles and the fractions 1/n of said reference clock signal elapsed between an edge of said Pulse-Width Modulated signal and the instant when said asynchronous event signal was set.

14. The system according to claim 13, wherein the phase sampling circuit includes: a first sub-circuit including for each of said phase shifted clock phases a respective first flip-flop configured to, in response to said asynchronous event signal, sample the respective phase shifted clock phase, thereby determining a respective first control signal indicating whether the respective clock phase was set to high or low at the instant when said asynchronous event signal was set; a second sub-circuit including for each of said phase shifted clock phases a respective second flip-flop configured to, in response to the respective phase shifted clock phase, sample the respective first control signal, thereby determining a respective second control signal corresponding to a synchronized version of the respective first control signal; a third sub-circuit configured to: associate with each of said phase shifted clock phases a further clock phase, said further clock phase corresponding to the phase shifted clock phase of said sequence of phase shifted clock phases preceding the respective clock phase with said time; determine for each of said phase shifted clock phases a respective third control signal indicating whether: the second control signal associated with the respective phase shifted clock phase indicates that the respective phase shifted clock phase was set to low at the instant when said asynchronous event signal was set, and the second control signal associated with the respective further clock phase indicates that the respective further clock phase was set to high at the instant when said asynchronous event signal was set; and a fourth sub-circuit including for each of said phase shifted clock phases a respective third flip-flop configured to, in response to the respective phase shifted clock phase, sample the respective third control signal, thereby determining a respective fourth control signal corresponding to a synchronized version of the respective third control signal.

15. The system according to claim 14, wherein the time measurement circuit includes: a respective logic OR gate for each of said phase shifted clock phases, the OR gate configured to receive at input the respective first control signal provided by said respective first flip-flop and the respective second control signal provided by said respective second flip-flop, thereby determining a respective fifth control signal, and wherein each of said second flip-flops is configured to sample the respective fifth control signal, whereby each of said second flip-flops samples the respective first control signal only when the respective first control signal is set to high.

16. The system according to claim 14, wherein the third sub-circuit of the time measurement circuit includes: a respective logic AND gate for each of said phase shifted clock phases, each logic AND gate configured to receive at input an inverted version of the second control signal associated with the respective phase shifted clock phase, and the second control signal associated with the respective further clock phase, thereby generating the respective third control signal.

17. An integrated circuit, comprising: a time measurement circuit, including: a multiphase clock generator configured to generate a sequence of a given number n of phase shifted clock phases having a same clock period and being phase shifted by a time corresponding to a fraction 1/n of said clock period, wherein one of said phase shifted clock phases represents a reference clock signal; a node configured to receive an asynchronous event signal; a phase sampling circuit configured to generate said a phase value, said phase value being indicative of a number of said fractions 1/n of said clock period elapsed between an edge of said reference clock signal and an instant when said asynchronous event signal is set.

18. The integrated circuit according to claim 17, wherein the phase sampling circuit includes: a first sub-circuit including for each of said phase shifted clock phases a respective first flip-flop configured to, in response to said asynchronous event signal, sample the respective phase shifted clock phase, thereby determining a respective first control signal indicating whether the respective clock phase was set to high or low at the instant when said asynchronous event signal was set; a second sub-circuit including for each of said phase shifted clock phases a respective second flip-flop configured to, in response to the respective phase shifted clock phase, sample the respective first control signal, thereby determining a respective second control signal corresponding to a synchronized version of the respective first control signal; a third sub-circuit configured to: associate with each of said phase shifted clock phases a further clock phase, said further clock phase corresponding to the phase shifted clock phase of said sequence of phase shifted clock phases preceding the respective clock phase with said time; determine for each of said phase shifted clock phases a respective third control signal indicating whether: the second control signal associated with the respective phase shifted clock phase indicates that the respective phase shifted clock phase was set to low at the instant when said asynchronous event signal was set, and the second control signal associated with the respective further clock phase indicates that the respective further clock phase was set to high at the instant when said asynchronous event signal was set; and a fourth sub-circuit including for each of said phase shifted clock phases a respective third flip-flop configured to, in response to the respective phase shifted clock phase, sample the respective third control signal, thereby determining a respective fourth control signal corresponding to a synchronized version of the respective third control signal.

19. The integrated circuit of claim 17, wherein the time measurement circuit includes: a counter circuit configured to increase a count value in response to said reference clock signal; and a counter sampling circuit configured to generate a sampled count value by sampling said count value.

20. The integrated circuit of claim 19, further comprising: a Pulse-Width Modulated (PWM) signal generator circuit configured to generate a Pulse-Width Modulated signal as a function of the count value of said counter circuit, wherein said sampled count value and said phase value are indicative of a number of clock cycles and the fractions 1/n of said reference clock signal elapsed between an edge of said Pulse-Width Modulated signal and the instant when said asynchronous event signal was set.

Description

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

(1) The embodiments of the present disclosure will now be described with reference to the drawings, which are provided purely to way of non-limiting example and in which:

(2) FIG. 1 shows an example of a PWM signal;

(3) FIG. 2 shows an example of a circuit generating multi-phase clock signals;

(4) FIG. 3 shows an example of the waveforms of clock phases provided by the circuit of FIG. 2;

(5) FIG. 4 shows an example of the fine tuning of the switch-on duration of a PWM signal by means of multi-phase clock signals;

(6) FIG. 5 shows an embodiment of the fine tuning of both the switch-on duration and the switch-off duration of a PWM signal by means of multi-phase clock signals;

(7) FIGS. 6A and 6B show embodiments of a timer circuit in accordance with the present disclosure;

(8) FIG. 7 shows exemplary waveforms generated by the timer circuits of FIGS. 6A and 6B;

(9) FIG. 8 shows an embodiment of a PWM generator circuit;

(10) FIGS. 9A, 9B, 10A, 10B, 10C, 11A, 11B, 12A, 12B, 12C and 12D show various details of the circuits of FIGS. 6A, 6B and 8;

(11) FIG. 13 shows an embodiment of a timer circuit configured to determine a sampled count value and sampled phase value in response to an asynchronous event;

(12) FIG. 14 shows an embodiment of a count value sampling circuit configured to determine a sampled count value in response to an asynchronous event;

(13) FIGS. 15, 16 and 17 show details of the count value sampling circuit of FIG. 14; and

(14) FIGS. 18, 19 and 20 show an embodiment of a phase value sampling circuit configured to determine a sampled phase value in response to an asynchronous event.

DETAILED DESCRIPTION

(15) In the ensuing description, various specific details are illustrated aimed at enabling an in-depth understanding of the embodiments. The embodiments may be provided without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not shown or described in detail so that various aspects of the embodiments will not be obscured.

(16) Reference to “an embodiment” or “one embodiment” in the framework of this description is meant to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is comprised in at least one embodiment. Hence, phrases such as “in an embodiment,” “in one embodiment,” or the like that may be present in various points of this description do not necessarily refer to one and the same embodiment. Moreover, particular conformations, structures, or characteristics may be combined in any adequate way in one or more embodiments.

(17) The references used herein are only provided for convenience and hence do not define the sphere of protection or the scope of the embodiments.

(18) In FIG. 2 to 20 described below, parts, elements or components that have already been described with reference to FIG. 1 are designated by the same references used previously in these figures. The description of these elements has already been made and will not be repeated in what follows in order not to burden the present detailed description.

(19) As explained in the foregoing, time measurement circuits (chronometers) configured to measure the time elapsed between a first (start) event and a second (stop) event may be useful in a variety of application, such as for measuring the time elapsed between the rising and/or falling edge of a PWM signal (representing a start event) and a given event generated in response to the rising or falling edge of the PWM signal. Generally, the second/stop event may thus be signaled via an asynchronous external signal.

(20) Thus, before discussing embodiments of time measurement circuits, first possible solutions for generating PWM signals will be discussed.

(21) As described with respect to FIG. 1, one of the simplest solutions for generating a PWM signal is based on an oscillator circuit generating a clock signal CLK and a counter configured to increase a count value in response to the clock signal CLK. Thus, by using a comparator circuit the PWM signal may be generated as a function of the count value provided by the counter, e.g., by comparing the count value with given threshold values, e.g., indicative of the switch-on duration T.sub.ON and the switching period T.sub.SW.

(22) However, in such a (digital) implementation, the accuracy and resolution of the PWM signal is limited by the clock period T.sub.CLK (sampling frequency) of the clock signal CLK. Moreover, by increasing the clock frequency F.sub.CLK=1/T.sub.CLK also the switching losses will increase.

(23) However, in many applications, high resolution PWM signals are required or strongly preferred. For example, as mentioned before, PWM signals may be used in many applications to control the average value of a voltage or current, such as for wireless battery chargers, switching mode power converters, motor control and lighting. For example, in such applications a half-bridge or full bridge may be used to drive a resonant tank, usually comprising one or more inductors and capacitors, wherein the electronic switches of the half-bridge or full bridge are driven by means of PWM signals.

(24) In order to miniaturize the equipment, small inductors may be used leading to a high working frequency. Thus, often a high-frequency modulated waveform PWM signal with high precise resolution should be provided in order to keep power consumption at acceptable values. For example, in a switching power supply, the output voltage is often directly proportional to the PWM duty cycle. The smaller is the adjustment to the duty cycle, the smaller is the resulting change to the output, i.e., a more precise control of the output voltage permits to achieve a better accuracy level and system stability. Moreover, minimizing output voltage ripple means reduce noise levels.

(25) An alternative solution for generating a PWM signal, in particular a High Resolution (HR) PWM signal, is based on the use of multiple clock phases, i.e., phase-shifted clock signals having the same frequency.

(26) For example, FIG. 2 shows a possible circuit for generating multiple clock phases ϕ.sub.0..ϕ.sub.n, via a Delay Locked Loop (DLL).

(27) Specifically, in the example considered the clock signal CLK generated by an oscillator OSC is fed to a cascade of a plurality of (identical) delay stages DU.sub.1..DU.sub.n. Specifically, in the example considered, the first phase ϕ.sub.0 corresponds to the clock signal CLK, and the other phases ϕ.sub.1..ϕ.sub.n correspond to the output signals of the delay stages DU.sub.1..DU.sub.n.

(28) In the example considered, each of the delay stages DU.sub.1..DU.sub.n has a delay T.sub.DU being programmable/settable as a function of a (voltage or current) control signal CTRL. For example, such delay stages DU having a variable delay may be implemented with an even number of inverters, wherein one or more of the inverters charges a respective capacitance, such as a parasitic capacitance, connected to the output of the inverter. In this case, the control signal CTRL may be indicative of the current provided by the inverter to charge the respective capacitance, thereby varying the time until the following inverter switches.

(29) In the example considered, the last phase ϕ.sub.n (having a given delay T.sub.D=n.Math.T.sub.DU with respect to the clock signal CLK) and the clock signal CLK is provided to a phase detector PD. The output of the phase detector PD is fed to a regulator CP having at least an I (Integral) component, such as a charge pump, wherein the regulator CP provides at output the control signal CTRL. Optionally the control signal CTRL may be passed through a loop filter LF.

(30) Thus, essentially, the negative feedback loop, implemented by the blocks PD/CP/LF, synchronizes in time the last phase ϕ.sub.n with the clock signal CLK. If the delay cells DU are identical, all the clock phases ϕ.sub.1..ϕ.sub.n will have the same frequency f.sub.CLK, but are phase shifted with respect to the preceding phase by a delay of T.sub.DU=T.sub.CLK/n.

(31) Such multiple clock phases may also be provided by a Phase Locked Loop (PLL) comprising a Voltage Controlled Oscillator (VCO) comprising a ring-oscillator with a plurality of delay stages, wherein the PLL is locked to the frequency of a clock signal CLK. Also in this case, a locking of the PLL may be obtained by varying the delay introduced by the delay stages, e.g., by varying via a bias circuit the current provided by the inverter stages implementing such delay stages, until the oscillator signal at the output of the VCO corresponds to the clock signal CLK. Thus, each delay stage of the VCO may provide a respective clock phase, which is phase shifted by a given fraction of the period of the clock signal CLK.

(32) For example, FIG. 3 shows exemplary waveforms for the phases ϕ.sub.1..ϕ.sub.16 in case n=17, wherein the last phase ϕ.sub.17=ϕ.sub.0=CLK is not shown in the Figure.

(33) Accordingly, as shown in FIG. 4, while a counter and respective comparator circuit may provide a coarse PWM signal (having a plurality k of clock cycles of the clock signal CLK), the additional clock phases ϕ.sub.1..ϕ.sub.n may be used to add a fine tuning to the coarse PWM signal, which essentially permits to add fractions T.sub.DU of the clock signal CLK to the coarse PWM signal. For example, such a solution is described in document U.S. Pat. No. 7,206,343 B2, the content thereof being incorporated herein by reference for this purpose.

(34) For example, the fraction may be added to the coarse PWM signal by: directly combining, e.g., by using one or more logic (e.g., OR) gates, the coarse PWM signal with a given selected clock phase ϕ, or as described in document U.S. Pat. No. 7,206,343 B2, indirectly by passing the coarse PWM signal through additional delay stages and combining the coarse PWM signal with the delayed PWM signal, e.g., via a logic (e.g., OR) gate, wherein the additional delay stages introduce the same delay T.sub.DU as the delay stages DU.sub.1..DU.sub.n, e.g., by biasing the additional delay stages with the same control signal CTRL as the delay stages DU.sub.1..DU.sub.n.

(35) Thus, assuming that the counter (and a respective comparator circuit) provides a coarse PWM signal having a switching period T.sub.SW=i.Math.T.sub.CLK and a switch-on duration of T.sub.ON=k.Math.T.sub.CLK, with 0≤k≤i, the final PWM signal may have a switching period T.sub.SW=i.Math.T.sub.CLK and a switch-on duration T.sub.ON=k.Math.T.sub.CLK+l.Math.T.sub.CLK/n, with 0≤l<n. Thus, the switch-on duration T.sub.ON of the PWM signal may be selected by setting the integer values of the parameters k and l. Thus, essentially the use of an additional DLL or PLL permits to vary the switch-on duration T.sub.ON, or in general the duty cycle D, with a higher precision, while the switching period T.sub.SW remains constant.

(36) However, in various embodiments, the PWM signal generator circuit may also be configured to receive a plurality of clock phases ϕ.sub.0..ϕ.sub.n and generate both the rising and the falling edges of the PWM signal as a function of these clock phases ϕ.sub.0..ϕ.sub.n, thereby controlling both the PWM duty cycle and the PWM frequency with a higher resolution.

(37) FIG. 5 shows the general operation of a first embodiment.

(38) In the embodiment considered, the PWM signal generator circuit receives the first clock phases ϕ.sub.0 (and/or the last clock phase ϕ.sub.n=ϕ.sub.0) and the intermediate clock phases ϕ.sub.1..ϕ.sub.n-1. In some embodiments, the PWM signal generator circuit includes a multiphase clock generator that generates the various clock phases, which may include any multiphase clock generator configured to generate the clock phases described herein. Possible solutions for generating such clock phases are already described in the introduction of the present disclosure, and the relevant description applies in its entirety (see in particular the description of FIG. 2). That is, in some embodiments, the multiphase clock generator circuit of various embodiments of the present disclosure may be as described, for example, with respect to FIG. 2.

(39) Moreover, in the embodiment considered, the PWM signal generator circuit is configured to generate a PWM signal, wherein: the switching duration T.sub.SW may be set to T.sub.SW=i.Math.T.sub.CLK+j.Math.T.sub.CLK/n; and the switch-on time T.sub.ON may be set to T.sub.ON=k.Math.T.sub.CLK+l.Math.T.sub.CLK/U.

(40) In various embodiments, the parameters i, j, k and l integer values, wherein the parameters i, j, k and l may be programmable.

(41) Specifically, in the example shown in FIG. 5, it is assumed that n=17, e.g., the PWM signal generator circuit receives the clock phases ϕ.sub.0..ϕ.sub.16, and the PWM signal generator circuit is configured to generate a PWM signal with:
T.sub.SW=i.Math.T.sub.CLK+10.Math.T.sub.CLK/17=T.sub.i+10.Math.T.sub.CLK/17, a duty cycle of 50% (i.e., T.sub.ON=T.sub.OFF=T.sub.SW/2), i.e., T.sub.ON=T.sub.OFF=T.sub.i/2+5.Math.T.sub.CLK/17.

(42) In the example considered, it will be assumed for simplicity that i is an even number, and k=p=i/2.

(43) Specifically, in the embodiment considered, the PWM signal generator circuit is configured to use during the first switch-on period T.sub.1 the phase ϕ.sub.0 as clock signal for the digital counter counting the time period T.sub.i/2=k.Math.T.sub.CLK, and (as will be described in greater detail in the following) the PWM signal generator circuit adds at the end a fraction of 5/17 of the period T.sub.CLK by using the phase ϕ.sub.5.

(44) However, instead of then tracking the accumulation of the various fractions, the PWM signal generator circuit uses then during the following switch-off period T.sub.2 the phase ϕ.sub.5 (i.e., the phase used to add the fraction) as clock signal for the timer circuit (i.e., the digital counter counting the time period p.Math.T.sub.CLK) Moreover, the PWM signal generator circuit adds at the end again the respective fraction of 5/17 of the period T.sub.CLK by using in this case the phase ϕ.sub.10, insofar as the phase ϕ.sub.10 is shifted by a delay of 5.Math.T.sub.CLK/17 with respect to the phase ϕ.sub.5.

(45) Next, the PWM signal generator circuit use during the second switch-on period T.sub.3 the phase ϕ.sub.10 as clock signal for the digital counter counting the time period k.Math.T.sub.CLK, and the PWM signal generator circuit adds at the end a fraction of 5/17 of the period T.sub.CLK by using this time the phase ϕ.sub.15, insofar as the phase ϕ.sub.15 is shifted by a delay of 5.Math.T.sub.CLK/17 with respect to the phase ϕ.sup.10.

(46) Similarly, the PWM signal generator circuit use during the following switch-off period T.sub.4 the phase ϕ.sub.15 as clock signal for the digital counter counting the time period p.Math.T.sub.CLK, and the PWM signal generator circuit adds at the end a fraction of 5/17 of the period T.sub.CLK by using this time the phase ϕ.sub.3, insofar as the phase ϕ.sub.3 is shifted by a delay of 5.Math.T.sub.CLK/17 with respect to the phase ϕ.sub.15.

(47) This operation continues also for the following switch-on and switch off periods.

(48) In various embodiments, the PWM generator circuit is thus configured to generate a PWM signal, wherein: the switch-on duration corresponds to T.sub.ON=k.Math.T.sub.CLK+l.Math.T.sub.CLK/n; and the switch-off duration corresponds to T.sub.OFF=p.Math.T.sub.CLK+q.Math.T.sub.CLK/n.

(49) In various embodiments, the parameter n (number of delay stages/phase) is fixed at a hardware level. However, the number n could also be programmable, e.g., by using in FIG. 2 a given fixed number of delay stages (e.g., 32) and selecting the n-th phase (and not necessarily the last one) as feedback signal provided to the phase detector PD. In fact, in this way, the control loop will still be locked to the n-th phase ϕ.sub.n, with T.sub.DU=T.sub.CLK/n.

(50) Thus, in various embodiments, the timer circuit of the PWM signal generator circuit (comprising the counter circuit and the comparator circuit) is configured to: during a switch-on period T.sub.ON, increase a count value from a reset value until the count value reaches the integer value k; and during a switch-off period T.sub.OFF, increase a count value from a reset value until the count value reaches the integer value p.

(51) However, in general, the timer circuit may also monitor the switching duration T.sub.SW, i.e., the timer circuit of the PWM signal generator circuit (comprising the counter circuit and the comparator circuit) may be configured to: during a switch-on period, increase a count value from a reset value until the count value reaches the integer value k; and during a switch-off period, increase the count value used during the switch-on period until the count value reaches the integer value i.

(52) Thus, in various embodiments, the PWM signal generator circuit is configured to determine the parameters k/l, and at least one of p/q, and i/j wherein: in case of a switch-on period T.sub.ON, k corresponds to the integer number of clock cycles of the clock signal CLK and l corresponds to the integer number of the fractions 1/n of a clock cycle of the clock signal CLK; in case of a switch-off period T.sub.OFF, p corresponds to the integer number of clock cycles of the clock signal CLK and q corresponds to the integer number of the fractions 1/n of a clock cycle of the clock signal CLK; and in case of a switching period T.sub.SW, i corresponds to the integer number of clock cycles of the clock signal CLK and j corresponds to the integer number of the fractions 1/n of a clock cycle of the clock signal CLK.

(53) Specifically, in view of the above definitions:
T.sub.ONk.Math.T.sub.CLK+l.Math.T.sub.CLK/n  (2)
T.sub.OFFp.Math.T.sub.CLK+q.Math.T.sub.CLK/n  (3)
T.sub.SW=T.sub.ON+T.sub.OFF=i.Math.T.sub.CLK+j.Math.T.sub.CLK/n  (4)
the integer values i and j are related to the integer values k, l, p and q according to the following equations: in case (l+q)<n (without overflow):
i=k+p;j=l+q;  (5) in case (l+q)>n (with overflow):
i=k+p+1;j=l+q−n.  (6)

(54) Thus, in various embodiments, the PWM generator circuit is configured to receive at least two of the parameters i, k and p, and at least two of the parameters j, l and q. For example, the PWM signal generator circuit may directly receive the parameters k/l and/or p/q and/or i/j, such as: data identifying (e.g., corresponding to) the parameters k/l; and data identifying (e.g., corresponding to) the parameters p/q.

(55) Alternatively, the PWM signal generator circuit may receive other data permitting a calculation of these parameters according to equations (5) and (6), such as: data identifying the switching duration T.sub.SW, such as the above-mentioned parameters i and j, and one of: data identifying (e.g., corresponding to) the parameters k/l; data identifying (e.g., corresponding to) the parameters p/q; or data identifying the duty cycle

(56) As shown in FIG. 6A, in various embodiments, the PWM signal generator circuit comprises a timer circuit 102 comprising a digital counter circuit 104 configured to vary (i.e., increase or decrease) an integer count value CNT in response to a clock signal CLK_TMR and a comparator circuit 106 configured to compare the count value CNT with a respective integer comparison threshold.

(57) As shown in FIG. 6A, the same counter 104 and comparator 106 may be used for both the switch-on period and the switch-off period by selecting, e.g., via a multiplexer 108, the parameter k or p as comparison threshold. Accordingly, by resetting the counter 104 via the signal at the output of the comparator 106, the same counter 104 may be used to monitor the switch-on period and the switch-off period. However, the counter 104 may also be used to monitor the switch-on period and the duration T.sub.SW. For example, in this case, the multiplexer 108 may receive the parameters k and i, and the counter 104 may only be reset when the count value CNT reaches the value i.

(58) Alternatively, as shown in FIG. 6B, a respective counter 104a and 104b and comparator 106a and 106b may be used for the switch-on period and the switch-off period, wherein the comparator 106a compares a count value CNTa provided by the counter 104a with the parameter k and the comparator 106b compares a count value CNTb provided by the counter 104b with the parameter p.

(59) In various embodiments, the timer circuit 102 is configured to generate one or more trigger signal when the output of the comparator indicates that the count value has reached the comparison threshold, e.g., by using a signal EOC_TMR at the output of the comparator 106, or respective signal EOC_TMRa and EOC_TMRb at the outputs of the comparators 106a and 106b.

(60) In the embodiments considered, the signal EOC_TMR (FIG. 6A) or the signals EOC_TMRa and EOC_TMRb (FIG. 6B) are provided to a control circuit 110 with selects the clock signal CLK_TMR for timer circuit 102, in particular the counter 104 (104a/104b), as a function of: during a switch-on period, the parameter l; and during a switch-off period, the parameter q.

(61) Specifically, even when monitoring the end of the switching duration T.sub.SW, it is preferably to obtain, e.g., calculate according to equations (5) and (6), the parameter q, because this parameter indicates the additional fractions which have to be added with respect to the previous switch-on period.

(62) For example, the control circuit 110 may select the clock signal CLK_TMR by driving via a selection signal SEL1 a multiplexer 100 receiving at input the clock phases ϕ.sub.0..ϕ.sub.n-1. Similarly, the control signal may drive via a selection signal SEL2 a multiplexer 112 in order to select either the parameter l or the parameter q, i.e., the selection signal indicates whether the current period is a switch-on period or a switch-off period, and may thus also be used to drive the multiplexer 108.

(63) Specifically, in various embodiments, in response to a trigger in the signal EOC_TMR (FIG. 6A) or the signals EOC_TMRa and EOC_TMRb (FIG. 6B), the control circuit 110 is configured to change the logic value of the selection signal SEL1: during a switch-on period, as a function of the parameter l; and during a switch-off period, as a function of the parameter q.

(64) Specifically, in various embodiments, the control circuit also performs a modulo operation in order to maintain the selection signal SEL1 between 0 and n−1. Accordingly, in response to a trigger in the signal EOC_TMR (FIG. 6A) or the signals EOC_TMRa and EOC_TMRb (FIG. 6B), the control circuit 110 varies the selection signal SEL1: during a switch-on period, SEL1=(SEL1+l) mod n; and during a switch-off period, SEL1=(SEL1+q) mod n.

(65) Thus, essentially, the control circuit 110 implements a phase accumulator circuit, which adds to the currently selected phase either l or q, wherein the parameters q may be calculated, e.g., as shown in equations (5) and (6) as a function of the parameters j and n.

(66) Finally, in various embodiments, the respective period (either a switch-on or switch-off period) is terminated and the following period is started with the next clock pulse (i.e., with the next rising or falling edge based on which type of edge is used by the timer circuit 102) of the selected clock phase.

(67) Thus essentially, during a switch-on period T.sub.ON the trigger signal EOC_TMR (or EOC_TMRa) is generated after a time k.Math.T.sub.CLK, and by changing the clock signal CLK_TMR the switch-on period is terminated, thereby starting the following switch-off period, after an additional time l/n.Math.T.sub.CLK. Similarly, during a switch-off period T.sub.OFF the trigger signal EOC_TMR (or EOC_TMRb) is generated after a time p.Math.T.sub.CLK (which may be obtained, e.g., by resetting the counter 104 and waiting for p cycles or by waiting until the count value reaches i), and by changing the clock signal CLK_TMR the switch-off period is terminated, thereby starting the following switch-on period, after an additional time q/n.Math.T.sub.CLK.

(68) For example, this is shown in FIG. 7, wherein during a switch-on period, the timer circuit uses a clock phase CLK_TMR=ϕ.sub.x, and the trigger signal EOC_TMR is set after, e.g., k=9 periods of the phase ϕ.sub.x, e.g., with the 10.sup.th rising edge. In response to the trigger signal EOC_TMR (EOC_TMRa) the control circuit selects a new phase CLK_TMR=ϕ.sub.y (with y=(x+l) mod n). Moreover, in response to the immediately following (e.g., rising) edge in the signal ϕ.sub.y, the PWM signal generator circuit terminates the switch-on period and starts the following switch-off period, thereby introducing an additional time corresponding a fraction l/n of the clock period.

(69) In the embodiment considered, during the following switch-off period, the timer circuit uses then the clock phase CLK_TMR=ϕ.sub.y, and the trigger signal EOC_TMR is set after, e.g., p=8 periods of the phase ϕ.sub.y, e.g., with the 9.sup.th rising edge. In response to the trigger signal EOC_TMR (EOC_TMRb) the control circuit selects a new phase CLK_TMR=ϕ.sub.z (with z=(y+q) mod n). In response to the immediately following (e.g., rising) edge in the signal ϕ.sub.z, the PWM signal generator circuit terminates the switch-off period and starts the following switch-on period, thereby introducing an additional time corresponding a fraction q/n of the clock period.

(70) In the previous embodiments, the control circuit 110 is configured to drive the selection circuit 100 in order to changes the phase ϕ assigned to the clock signal CLK_TMR from the current phase (t) (e.g., ϕ.sub.0) to the next phase ϕ(t+1) (e.g., ϕ.sub.5) in response to the signal EOC_TMR, thereby adding the fractions (l or q) at the end of the respective switch-on or switch-off period.

(71) However, in various embodiments, the switching from the current phase ϕ(t) to the next phase ϕ(t+1) may occur at any instant during the respective period. In this case, the control unit 110 may also be configured to either increase/decrease sequentially, e.g., in response to the clock signal CLK_TMR, the selection signal SEL1 from the old phase ϕ(t) to the new phase ϕ(t+1) (e.g., ϕ.sub.0, ϕ.sub.1, ϕ.sub.2, ϕ.sub.3, ϕ.sub.4, ϕ.sub.5) or by switching directly to the new phase ϕ(t+1).

(72) Generally, while reference has been made to periods of the clock signal CLK, indeed the phases ϕ.sub.0 . . . ϕ.sub.n-1 may also have a different clock period T.sub.PLL, e.g., the frequency f.sub.PLL=1/T.sub.PLL may be a multiple of the clock frequency f.sub.CLK, e.g., by using a frequency divider in the feedback loop of the phase ϕ.sub.n-1. Accordingly, in general: the switch-on duration corresponds to T.sub.ON=k.Math.T.sub.PLL+l.Math.T.sub.PLL/n; and the switch-off duration corresponds to T.sub.OFF=p.Math.T.sub.PLL+q.Math.T.sub.PLL/n.

(73) FIG. 8 shows a second embodiment of a PWM signal generator circuit.

(74) Specifically, in the embodiment considered, the PWM signal generator circuit comprises again a timer circuit 102, a clock switching circuit 100′ and a control circuit/phase accumulator 110′.

(75) Specifically, with respect to FIGS. 6A and 6B, the clock switching circuit 100′ is not implemented with a mere multiplexer, but with a circuit which directly generates, in response to the trigger signal EOC_TMR provided by the timer circuit 102, the clock signal CLK_TMR for the timer circuit as a function of the selection signal SEL1 provided by the control circuit 110′. Generally, as described in the foregoing, also any other trigger signal may be used to assign to the clock signal CLK_TMR a new clock phase as a function of the selection signal SEL1.

(76) For example, a possible embodiment of the clock switching circuit 100′ is shown in FIGS. 9A and 9B.

(77) In the embodiment considered, the selection signal SEL1 (indicative of the next clock phase), is provided to a series of optional latches 1000 configured to store the value of the signal SEL1 in response to the trigger signal EOC_TMR. Substantially, these latches 1000 ensure that the circuit samples the value of the signal SEL1 only when a trigger in the signal EOC_TMR is generated.

(78) In the embodiment considered, each clock phase ϕ.sub.0 . . . ϕ.sub.n-1 is provided to a respective transmission gate (gated clock cells) 1002.sub.0 . . . 1002.sub.n being enabled as a function of the selections signal SEL1 or optionally the latched selections signal SEL1, thereby generating respective (gated) signals ϕ.sub.0_gtd . . . ϕ.sub.n-1_grtd. For example, in various embodiments, the selection signal comprises (n) bits SEL.sub.0 . . . SEL.sub.n-1 and uses a one-hot encoding, wherein a given bit is associated univocally with a given clock phase ϕ.sub.0 . . . ϕ.sub.n-1, i.e., only one of the bits SEL.sub.0 . . . SEL.sub.n-1 is set and indicates that the respective clock phase ϕ.sub.0 . . . ϕ.sub.n-1 may pass through the respective transmission gate 1002.sub.0 . . . 1002.sub.n-1, while the other clock phases ϕ.sub.0 . . . ϕ.sub.n-1 cannot pass through the respective transmission gates 1002.sub.0 . . . 1002.sub.n-1. In general, also other encoding schemes may be used for the selection signal (such as a binary encoding), and the transmission gates may be driven via a decoder circuit configured to generate the one-hot encoded drive signals for the transmission gates 1002.sub.0 . . . 1002.sub.n-1 as a function of the selection signal SEL1.

(79) As shown in FIG. 9B, the signals ϕ.sub.0_gtd . . . ϕ.sub.n-1_gtd are then provided to a combinational logic circuit 1004 configured to generate at output the clock signal CLK_TMR for the timer circuit 102 by combining the signals ϕ.sub.0_gtd . . . ϕ.sub.n-1_gtd. For example, in various embodiments the signals ϕ.sub.0_gtd . . . ϕ.sub.n-1_gtd are combined via a logic OR operation, e.g., implemented with a cascaded structure of a plurality of OR gates OR1, OR2, OR3, etc.

(80) FIG. 10A shows the operation of the clock switching circuit 100′ at the example of a selection signal SEL1 having in sequence the value k, x and y, thereby activating (in response to the trigger signal EOC_TMR) in sequence the clock phases ϕ.sub.k_gtd, ϕ.sub.x_gtd and ϕ.sub.y_gtd.

(81) Thus, in case the selection signal SEL1 changes, the clock signal CLK_TMR switches from a first clock phase to a second clock phase in response to the selection signal.

(82) Specifically, as shown in FIG. 10B, when the second clock phase (ϕ.sub.x_gtd) goes to high (rising edge), while the first clock phase (ϕ.sub.k_gtd) is still high, the resulting clock signal CLK_TMR will have a single clock pulse with a duration being greater than the clock period T.sub.PLL of the clock phases ϕ.sub.0 . . . ϕ.sub.n-1, thereby essentially losing a clock cycle.

(83) Usually this occurs when the respective fraction l or q is smaller than n/2.

(84) Conversely, as shown in FIG. 10C, when the second clock phase (ϕ.sub.y_gtd) goes to high (rising edge), while the first clock phase (ϕ.sub.x_gtd) is low, the resulting clock signal CLK_TMR will have a single clock pulse, with a duration being smaller than the clock period T.sub.PLL of the clock phases ϕ.sub.0 . . . ϕ.sub.n-1. Usually this occurs when the respective fraction l or q is greater than n/2.

(85) Thus, the lost clock edge (FIG. 10B) should be taken into account in order to correctly determine the duration of the respective time interval. Specifically, in various embodiments, in case a clock cycle is lost, i.e., the respective fraction l or q is smaller than n/2, the PWM signal generator circuit is configured to increase the timer circuit 102 by an additional clock cycle, i.e., the timer 102 is increase by 2 and not only 1 for a single clock cycle.

(86) FIG. 11A shows a possible embodiment of the timer circuit 102.

(87) Specifically, in the embodiment considered, the counter 104 is implemented with an accumulator comprising: a register 1040 providing at an output the count value CNT, wherein the register 1040 is configured to store a signal REG_IN at a respective input in response to the clock signal CLK_TMR; and a digital adder 1042, configured to generate the signal REG_IN at the input of the register 1040 by adding an increment value INC to the count value CNT.

(88) In the embodiment considered, the increment value INC may be set either to “1” or “2,” e.g., via a multiplexer 1044. Specifically, the selection is driven via a selection signal SEL3 provided by the control circuit 110 (or similarly by the control circuit 110′).

(89) Specifically, in the embodiment considered, the control circuit 110 comprises: a digital comparator 1100 configured to determine whether the fraction value l or q of the current switch-on or switch-off period is greater than n/2; and a circuit 1102 configured to generate a selection signal SEL3 as a function of the comparison signal generated by the comparator 1100 and a trigger signal indicating the start of a new switch-on or switch-off period, such as the signal EOC_TMR or, in the general case, as a function of the comparison signal generated by the comparator 1100 and a generic trigger signal whose length is one CLK_TMR cycle and generated in any appropriate instant during the switch-on or switch-off period.

(90) Specifically, in the embodiment considered, the multiplexer 112 already provide the fraction value for the current period, wherein the selection signal SEL2 indicates whether the current period is a switch-on or switch-off period. Accordingly, the comparator 1100 may receive at input the signal provided by the multiplexer 112 and thus generates a comparison signal indicating whether the fraction value l or q is greater than n/2. Specifically, the circuits 110 and 112 are configured: when the signal at the output of the comparator indicates that the fraction l or q (based on the current period) is greater than n/2 or the trigger signal (e.g., EOC_TMR) is not set, drive the multiplexer 1044 via the signal SEL3 in order to selected the value “1,” whereby the accumulator 1040/1042 is increased in response to the clock signal CLK_TMR by “1”; and when the signal at the output of the comparator indicates that the fraction l or q (based on the current period) is smaller than n/2 and the trigger signal (e.g., EOC_TMR) is set, drive the multiplexer 1044 via the signal SEL3 in order to selected the value “2,” whereby the accumulator 1040/1042 is increased in response to the clock signal CLK_TMR by “2.”

(91) Accordingly, substantially, the timer circuit 104 is configured to increase for one clock cycle of the signal CLK_TMR (i.e., a single cycle for each switch-on or switch-off period) the count value by two (“2”) when the fraction l or q (based on the current period) is smaller than n/2.

(92) Conversely, FIG. 11B shows that a similar result may be obtained by adapting directly the threshold value used by the comparator 106.

(93) Specifically, in the embodiment considered, the increment value INC is always set to “1,” and an additional digital subtractor is provided which is configured, e.g., via a multiplexer 1048, to: subtract the value “1” from the current threshold selected by the multiplexer 108 (k or p); or maintain the threshold value, e.g., by subtracting the value “0” from the current threshold selected by the multiplexer 108 (k or p).

(94) In general, the embodiments may also be combined, i.e., during a switch-on duration may be implemented either the “plus-two” mechanism (FIG. 11A) or the adaption of the threshold k (FIG. 11), and during a switch-off duration may be implemented either the “plus-two” mechanism or the adaption of the threshold p.

(95) Accordingly, in the embodiments considered, the circuits 1100/1102 inform the timer circuit 102 that a counting edge has been missed or will be missed due to clock combination shown in FIG. 9B. This missing edge information (i.e., the signal SEL3) can be computed by the control circuit/phase accumulator machine 110/110′ that controls the fine delay selection and generates the phase selection change SEL1 (indicative of the next clock phase to be used for fine tuning of PWM signal). In fact, if the new phase selection selects a clock having its rising edge appearing during the on-time of the running clock, the combined CLK_TMR will have a longer on-time and the edge of the next selected clock phase, used in the clock combination circuitry of FIG. 9B, will be missed. This happens if the phase selection change is smaller than the half of number of available phases i.e., this occurs when the respective fraction l or q is smaller than n/2 (e.g., └17/2┘=8).

(96) Using this clock change property, the timer may be incremented by “1” or “2,” or the threshold of the comparator 106 may be adapted with respect to this internal flag generated as shown in FIG. 11A or 11B.

(97) In various embodiments, the PWM signal is switched in response to the next rising edge of the new clock phase, i.e., the selected clock phase ϕ.sub.0_gtd . . . ϕ.sub.n-1_gtd of the following switch-on or switch-off period. However, the PWM signal may also be changed in response to the rising edge of the trigger signal EOC_TMR in the case of a SEL1 signal generated in any appropriate instant during the given time slot/period.

(98) For example, as shown in FIG. 8, the PWM signal generator circuit may comprise a toggle circuit 114 configured to generate the PWM signal as a function of the signals ϕ.sub.0_gtd . . . ϕ.sub.n-1_gtd and the trigger signal EOC_TMR.

(99) Generally, any suitable circuit may be used to toggle the level of the PWM signal in response to the signal EOC_TMR (or EOC_TMRa and EOC_TMRb) and the new clock phase.

(100) For example, FIG. 12A shows an embodiment of the toggle circuit 114. Specifically, the toggle circuit 114 comprise arising edged detector circuit. Specifically, in the embodiment considered, the toggle circuit comprises for each of the signals ϕ.sub.0_gtd . . . ϕ.sub.n-1_gtd a respective rising edge detector 1140.sub.0..1140.sub.n-1, which is enabled as a function of the signal EOC_TMR.

(101) Specifically, as shown in FIGS. 12B, 12C and 12D, in response to the rising edge of the current clock phase (e.g., ϕ.sub.k_gtd in FIG. 12C), the signal EOC_TMR will be set after a brief delay. In response to the trigger in the signal EOC_TMR, the circuit 100′ will switch to the new clock phase (e.g., ϕ.sub.x_gtd in FIG. 12C). Thus, no additional rising edge of the old clock signal (e.g., ϕ.sub.k_gtd in FIG. 12C) occurs. Thus, in response to the following rising edge in the new clock phase (e.g., ϕ.sub.x_gtd in FIG. 12C) the respective edge detector 1140 will set its output (e.g., to high), because also the signal EOC_TMR is still set.

(102) Accordingly, in the embodiment considered, the output of the various rising edge detector 1140.sub.0..1140.sub.n-1 may be connected to a combinational logic circuit, e.g., implementing a logic OR function (FIG. 12A shows schematically a logic OR gate OR4, that may correspond to the last OR gate of a chain of OR gates, e.g., comprising in cascade 6 OR gates having three inputs, 2 OR gates having 2 inputs and the OR gate OR4) for this purpose but, generally speaking, it can be implemented with a different number and topology of gates as a result of a different balancing process with respect to speed and to the number of clock phases), which generates at output a trigger signal TRIG indicating that the logic level of the PWM signal has to change.

(103) Accordingly, in the embodiment considered, the signal TRIG may be used to drive a flip-flop FF1 in order to invert the output of the flip-flop FF1, wherein the PWM signal is generated as a function (and preferably corresponds to) the signal at the output of the flip-flop FF1.

(104) For example, in the embodiment considered, the flip-flop FF1 is implemented with a D-type flip-flop, receiving at the data terminal D via an inverter INV1 the inverted output signal of the flip-flop FF1, thereby inverting the output of the flip-flop FF1 in response to the trigger signal TRIG.

(105) The inventor has observed that the above described clock signal CLK_TMR may also be used to implement a (high resolution) chronometer, i.e., a timer circuit configured to generate a signal indicative of the time elapsed between a start event and a stop event.

(106) Specifically, as described in the foregoing, PWM signals are often used to control the average value of a voltage or current. For example, PWM signals are often used in wireless battery chargers, switched mode power supplies (electronic converters), motor control and lighting. For example, a chronometer may be useful when the PWM signal is used to drive (e.g., via a half or full bridge) a resonant circuit comprising one or more inductances and capacitances, e.g., a LC resonant tank. For example, a typical application may be a wireless power transmitter, or an electronic converter. For example, in this application it may be useful to measure the time elapsed between the rising and/or falling edge of the PWM signal and a given event (generated in response to the rising or falling edge of the PWM signal). For example, the chronometer may measure the time elapsed between the rising edge of the PWM signal and the instant when a current flowing through a given component of the resonant tank or the voltage at a given component or node of the resonant tank reaches a given threshold value, e.g., the current flowing through or the voltage at one of the components of the LC resonant tank, such as the voltage at a ringing node of the LC resonant tank.

(107) The inventor has observed that the above described coarse counter(s) 104 or 104a/104b and the phase signals ϕ.sub.0 . . . ϕ.sub.n-1 may be used to capture, in response to a given asynchronous event, with high resolution the time information of the PWM signal generator circuit.

(108) Specifically, in various embodiments, the chronometer circuit is configured to store, in response to such an asynchronous event, the time and/or the phase information in a coherent way (e.g., with respect to the rising or falling edge of the PWM signal and the n phases outgoing from the PLL), with high resolution, minimum latency and without metastability issues.

(109) Specifically, in the previous embodiments, the counter(s) 104 or 104a/104b are controlled by an adaptive clock CLK_TMR corresponding to a single selected clock phase, and a different clock phase may be used for the next interval T.sub.ON or T.sub.OFF, thereby applying a fine tuning. Thus, the chronometer should sample the time, e.g., in terms of number of clock cycles and the phase information.

(110) FIG. 13 shows a first embodiment of a circuit 30 configured to determine a count value CV and a phase value PV in response to an asynchronous event, e.g., a rising (and/or falling) edge in a signal AE.

(111) As mentioned before, such an asynchronous event signal AE may be generated via a comparator circuit 300 configured to compare an analog (voltage or current) signal with a respective threshold value TH.

(112) Specifically, in the embodiment considered, the circuit 30 receives a plurality of phase signals ϕ.sub.0 . . . ϕ.sub.n-1 and a count value CNT from a counter 104.

(113) In the embodiment considered, the asynchronous event signal AE is sampled via a synchronization chain, e.g., implemented with two (or more) flip-flops FFa and FFb connected in cascade. Specifically, in the embodiment considered, the asynchronous event signal AE is sampled/synchronized with each of the phase signals ϕ.sub.0 . . . ϕ.sub.n-1, i.e., the circuit 30 comprises for each phase signal ϕ.sub.0 . . . ϕ.sub.n-1 a respective synchronization chain FFa.sub.0/FFb.sub.0, FFa.sub.1/FFb.sub.1, . . . configured to sample the asynchronous event signal AE in response to a respective phase signal ϕ.sub.0 . . . ϕ.sub.n-1, thereby generating respective sampled/synchronized versions AE.sub.0, AE.sub.1, . . . of the asynchronous event signal AE.

(114) In the embodiment considered, one of the synchronized signals AE.sub.0, AE.sub.1, . . . (e.g., the signal AE.sub.0) is provided to a register 301 in order to store the count value CNT of the counter 104 (or similarly the count value CNTa of the counter 104a or the count value CNTb of the counter 104b), thereby providing at output the count value CV.

(115) Moreover, the various synchronized versions AE.sub.0, AE.sub.1, . . . are provided to a circuit 302, preferably a combinational logic circuit, which is configured to generate the phase value PV as a function of the (instantaneous) logic values of the synchronized signals AE.sub.0, AE.sub.1, . . . .

(116) However, the inventor has observed that storing separately the counter value CNT and the phase state (as indicated by the signals AE.sub.0, AE.sub.1, . . . ) may result in incorrect counter and phase pairing, e.g., due to metastability and different path timing. For example, even when using synchronization chains, the signals AE.sub.0, AE.sub.1, . . . have to be combined and the operation should be synchronized also with the clock signal CLK_TMR of the counter 104.

(117) FIGS. 14 and 19 shows a second embodiment of a circuit configured to determine the count value CV and/or the phase value PV in response to an asynchronous event signal AE.

(118) Specifically, FIG. 14 shows an embodiment of a circuit 30a configured to determine the count value CV.

(119) Specifically, in the embodiment considered, the circuit 30a comprises two synchronization stages 304 and 306. For example, each of the synchronization stages 304 and 306 may be implemented with one or more flip-flops.

(120) Specifically, in the embodiment considered, the synchronization stage/flip-flop 306 is configured to sample the asynchronous event signal AE at each rising edge of the clock signal CLK_TMR, e.g., the clock signal CLK_TMR is connected to the clock input of the synchronization stage/flip-flop 306, thereby generating a first synchronized event signal AE_rs, and the synchronization stage/flip-flop 304 is configured to sample the asynchronous event signal AE at each falling edge of the clock signal CLK_TMR, which is schematically shown by a inverter INV providing an inverted version of the clock signal CLK_TMR to the clock input of the synchronization stage/flip-flop 304, thereby generating a second synchronized event signal AE_fl.

(121) For example, FIG. 16 shows an embodiment of a VHDL code of the two synchronization circuits 304 and 306.

(122) Specifically, a process “p_async_fllng” models the behavior of the circuit 304 and a process “p_async_rsng” models the behavior of the circuit 304.

(123) Generally, the process “p_async_fllng” is configured to assign to a signal ASYNCH_evnt_ret_fl (representing the signal AE_fl at the output of the circuit 304) the value of the signal CMP_ASYNCH_evnt (corresponding to the asynchronous event signal AE) in response to a falling edge of the clock signal CLK_TMR (indicated by the condition CLK_TMR′event and CLK_TMR=‘0’). Similarly, the process “p_async_rsng” is configured to assign to a signal ASYNCH_evnt_ret_rs (representing the signal AE_rs at the output of the circuit 306) the value of the signal CMP_ASYNCH_evnt (corresponding to the asynchronous event signal AE) in response to a rising edge of the clock signal CLK_TMR (indicated by the condition CLK_TMR′event and CLK_TMR=‘1’).

(124) In various embodiments, the circuits 304 and 306 may also support a reset operation. For example, in FIG. 16, the process “p_async_fllng” is configured to reset the signal ASYNCH_evnt_ret_fl when a signal s_rst_dump (representing the reset signal) is set. Similarly, the process “p_async_rsng” may be configured to reset the signal ASYNCH_evnt_ret_rs when the signal s_rst_dump is set.

(125) In the embodiment shown in FIG. 14, the signals at the output of the synchronization stages/flip-flops 304 and 306 are provided to a sampling circuit 308 configured to store the count value CNT (or similarly CNTa/CNTb) of the counter 104 in response to the clock signal CLK_TMR also taking into account the logic values of the signals AE_rs/ASYNCH_evnt_ret_rs and AE_fl/ASYNCH_evnt_ret_fl.

(126) In the embodiment considered, at least one of the signals AE_rs/ASYNCH_evnt_ret_rs and AE_fl/ASYNCH_evnt_ret_fl will be set by the circuits 304/306 when an asynchronous event AE is signaled.

(127) Specifically, as shown in FIG. 15, when the counter value CNT is increased at each rising edge of the clock signal CLK_TMR, a given delay exists until the counter value CNT changes.

(128) Thus, when an asynchronous event AE occurs while the clock signal CLK_TMR is high (e.g., instant t.sub.2 in FIG. 14), the signal AE_fl/ASYNCH_evnt_ret_fl will be set to high with the next falling edge of the clock signal CLK_TMR. Thus, when sampling the count value CNT at the next rising edge of the clock signal CLK_TMR, the signal AE_rs/ASYNCH_evnt_ret_rs will still be set to low (due to the intrinsic propagation delays).

(129) Conversely, when an asynchronous reset AE occurs while the clock signal CLK_TMR is low (e.g., instant t.sub.1 in FIG. 14), indeed the event occurs at a count value CNT−1 with respect to the instant t.sub.3 when the count value is sampled. However, in this case, the signal AE_rs/ASYNCH_evnt_ret_rs will be set to high with the next rising edge of the clock signal CLK_TMR and the signal AE_fl/ASYNCH_evnt_ret_fl will be set to high with the next falling edge of the clock signal CLK_TMR. Thus, when sampling the count value CNT at the next rising edge of the clock signal CLK_TMR, the circuit 30a should indeed sample the value CNT−1.

(130) Thus, in various embodiments, the circuit 30a is configured to: when the signal AE_rs/ASYNCH_evnt_ret_rs is low and the signal AE_fl/ASYNCH_evnt_ret_fl is high, sample the count value CNT, in response to the rising edge of the clock signal CLK_TMR; and when the signal AE_rs/ASYNCH_evnt_ret_rs is high and the signal AE_fl/ASYNCH_evnt_ret_fl is high, sample the count value CNT−1, in response to the rising edge of the clock signal CLK_TMR.

(131) For example, FIG. 17 shows an embodiment of a VHDL code of the circuit 308, wherein a process “p_counter_dump” models the respective behavior.

(132) For example, in the embodiment considered, in response to rising edge of the clock signal CLK_TMR (indicated by the condition CLK_TMR′event and CLK_TMR=‘1’) the circuit 310 verifies the logic values of the signals ASYNCH_evnt_ret_rs (AE_rs) and ASYNCH_evnt_ret_fl (AE_fl). In case, the signals ASYNCH_evnt_ret_rs (AE_rs) and ASYNCH_evnt_ret_fl (AE_fl) are high, the circuit stores to a signal s_tmrcnt_dmp (representing the count value CT) the value TMR_CRS−1 (representing the value CNT−1). Conversely, the signal ASYNCH_evnt_ret_rs (AE_rs) is low and ASYNCH_evnt_ret_fl (AE_fl) is high, the circuit stores to a signal s_tmrcnt_dmp (representing the count value CV) the value TMR_CRS (CNT).

(133) In various embodiments, the circuit 308 may also support a sample enable signal. For example, in FIG. 16, the process “p_counter_dump” is configured to store the value TMR_CRS−1 or TMR_CRS only when a sample enable signal s_end_dump has a given logic level (e.g., low, as indicated by the condition s_end_dump=‘0’). Moreover, once having stored the value TMR_CRS−1 or TMR_CRS, the logic value of this signal is inverted (e.g., high, as indicated by the operation s_end_dump<=‘1’).

(134) In various embodiments, the circuit 308 may be configured to reset the signals s_tmrcnt_dmp and s_end_dump when a signal s_rst_dump (representing again a reset signal) is set.

(135) Thus, in various embodiments, the circuit 30a is configured to receive a clock signal CLK_TMR, such as the clock signal CLK_TMR described with respect to the PWM generator circuit of FIGS. 5 to 12, wherein this clock signal is used to increase a counter 104. A first synchronization circuit 304 is used to synchronize/retime the asynchronous event signal AE in response to a falling edge of clock signal CLK_TMR, thereby generating a first signal AE_fl. A second synchronization circuit 306 is used to synchronize/retime the asynchronous event signal AE in response to a rising edge of clock signal CLK_TMR, thereby generating a first signal AE_rs.

(136) A sampling circuit 308 elaborates the signals AE_fl and AE_rs, e.g., via a combinational logic circuit, to determine: whether an asynchronous event AE occurred; and based on the signals AE_fl and AE_rs, whether the asynchronous event AE occurred while the clock signal CLK_TMR was high or low.

(137) In case, both signals AE_fl and AE_rs are high, the counter value CNT is stored as signal CV, and if only the signal AE_fl is high, the counter value CNT minus one (CNT−1) is stored as signal CV.

(138) As mentioned before, FIG. 19 shows a circuit 30b configured to perform a phase detection/sampling.

(139) In the embodiment considered, the circuit 30b comprises a first level of n flip flops FFa.sub.0..FFa.sub.n-1, wherein each of the flip flops FFa.sub.0..FFa.sub.n-1 is configured to sample a respective clock phase ϕ.sub.0 . . . ϕ.sub.n-1 (i.e., the respective phase ϕ.sub.i, with 0≤i≤(n−1), is applied to the data input of the flip-flop FFa.sub.i) in response to the asynchronous event signal AE (i.e., the asynchronous event signal AE is applied to the clock input of the flip-flop FFa.sub.i).

(140) In the embodiment considered, the circuit 30b comprises a second level of n flip flops FFb.sub.0..FFb.sub.n-1, configured to store the signal at the output of a respective one of the flip-flops FFa.sub.0..FFa.sub.n-1 in response to the falling edge of the respective phase ϕ.sub.0 . . . ϕ.sub.n-1, i.e., the output of a given flip-flop FFa.sub.i is applied/coupled to the data input of a respective flip-flop FFb.sub.i and the inverted version of the respective clock phase ϕi (schematically shown via inverters INV.sub.0..INV.sub.n-1) is applied to the clock input of the flip-flop FFb.sub.1, thereby generating respective signals CMP_PH(0) . . . CMP_PH(n−1) at the output of the flip-flops FFb.sub.0..FFb.sub.n-1.

(141) Specifically, in various embodiments, the flip-flops FFb.sub.0..FFb.sub.n-1 are configured to store only the signal at the output of the respective flip-flop FFa.sub.0..FFa.sub.n-1, when the signal at the output of the respective flip-flop FFa.sub.0 . . . FFa.sub.n-1 is high. Accordingly, once the signal at the output of a flip-flop FFa.sub.i is set to high, the output at the respective flip-flop FFb.sub.i is set to high in response to the next falling edge of the respective phase ϕ.sub.i, and the output of the flip-flop FFb.sub.i remains high also when the signal at the output of a flip-flop FFa.sub.i is set to low. For example, in FIG. 19 is shown schematically for this purpose for each flip-flop FFb.sub.0..FFb.sub.n-1 a respective logic OR gate OR.sub.0..OR.sub.n-1, wherein each logic OR gate OR.sub.i receives at input the signal at the output of the respective flip-flop FFa.sub.i and the signal at the output of the respective flip-flop FFb.sub.i, and the output of the logic OR gate OR.sub.i is connected to the input of the respective flip-flop FFb.sub.i.

(142) In the embodiment considered, the circuit 30b comprises also a third level of n flip flops FFc.sub.0..FFc.sub.n-1, configured to store, in response to a rising edge of a respective phase ϕ.sub.0 . . . ϕ.sub.n-1, the result of the comparison between two adjacent signals CMP_PH(0) . . . CMP_PH(n−1) at the output of the flip-flops FFb.sub.0..FFb.sub.n-1. Specifically, a given flip-flop FFc.sub.i receives at the clock input the respective phase ϕ.sub.i and at the data input a comparison signal, and provides at output a respective signal CMP_PH_FIN(i).

(143) Specifically, in the embodiment considered each comparison signal indicates whether the respective signal CMP_PH(i) is low (with 0≤i≤n−1), i.e., the inverted version INV(CMP_PH(i)) is high, and the respective signal CMP_PH(i−1) is high. Specifically, the first comparison signal is generated as a function of the signals CMP_PH(0) and CMP_PH(n−1). For example, the comparison signals may be generated via logic AND gates AND.sub.0..AND.sub.n-1, each logic and gate AND.sub.i receiving at input the signal CMP_PH(i−1) (or CMP_PH(n−1) when i=0) and the inverted version of the signal CMP_PH(i).

(144) Thus, essentially, the first two stages FFa and FFb generate synchronization trigger signals CMP_PH(0) . . . CMP_PH(n), wherein each flip flop FFA.sub.i samples, in response to a rising edge in the asynchronous event signal AE, a respective clock phase ϕ.sub.i; and each flip flop FFb.sub.i sets it output to high when, in response to a falling edge in the respective clock phase ϕ.sub.i, the signal at the output of the respective flip flop FFA.sub.i of the first stage is high.

(145) Conversely, the third stage FFc determines the phase value PV. Specifically, as shown in FIG. 18, when an asynchronous event AE is generated, there will be only one single set of adjacent clock phases, wherein the previous ϕ.sub.i-1 is high and the following ϕ.sub.i is low. For example, considering the instant t.sub.1, the clock phase ϕ.sub.1 is high and the clock phase ϕ.sub.2 is low. Thus, the third stage verifies for each index i the couple/set of signals CMP_PH(i−1) and CMP_PH(i), wherein the signal CMP_PH(i−1) is high and the signal CMP_PH(i) is low, wherein the value i represents the phase value PV. Specifically, in the embodiment considered, the third phase generates the signals CMP_PH_FIN(0) . . . CMP_PH_FIN(n−1), wherein only one of the signals CMP_PH_FIN(0) . . . CMP_PH_FIN(n−1) is set to high. Thus, essentially, the signals CMP_PH_FIN(0) . . . CMP_PH_FIN(n−1) represent a one-hot-encoding of the index i/phase value PV.

(146) Generally, the first two stages may both introduce metastability, insofar as the asynchronous event signal AE and the clock phases ϕ.sub.0 . . . ϕ.sub.n-1 are not synchronized. However, the comparison mechanism of the third stage is also useful to solve such potential metastability issues. In fact, by construction, only on one single channel CMP_PH(i) may have a metastability. Assuming a structure perfectly balanced, this metastable value is expected to be solved within half phase clock period thus arriving with the same logic value at the input of a pair of AND gates where it is effectively used thus allowing the last flip flop FFc level to store the correct value.

(147) In the embodiment considered, the registers FFb and FFc work as a double edge synchronizer; in general, each of the synchronization chains FFb.sub.i and FFc.sub.i may be implemented also with more flip-flops connected in cascade.

(148) In various embodiments, the registers FFa, FFb and FFc are configured to be reset in response to a reset signal RST, such as the previous mentioned signal s_rst_dump. Generally, such a reset signal RST/s_rst_dump may be generated by any suitable circuit 312, and essentially activates the detection of the next asynchronous event AE. For example, in the embodiment considered, the registers are reset in response to a falling edge of the signal RST.

(149) As mentioned before, in various embodiments, the counter circuit 104 (or similarly 104a and 104b) may use an adaptive clock signal CLK_TMR as described in the foregoing, wherein this clock signal CLK_TMR corresponds (during a given time period, such as the switch-on duration T.sub.ON and/or the switch-off duration T.sub.OFF) to one of the clock phases ϕ.sub.0 . . . ϕ.sub.n-1.

(150) Thus, as shown in FIG. 20, the circuit 30 may comprises a circuit 314 configured to calculate a phase difference value PV′ as a function of the clock phase ϕ.sub.0 . . . ϕ.sub.n-1 used by the counter 104, e.g., as indicated by the selection signal SEL1, and the phase value PV detected by stage FFc.

(151) Of course, without prejudice to the principle of the disclosure, the details of construction and the embodiments may vary widely with respect to what has been described and illustrated herein purely by way of example, without thereby departing from the scope of the present disclosure, as defined by the ensuing claims.

(152) The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.