Driver circuit capable of detecting abnormality of capacitive load

Abstract

A driver circuit driving a plurality of capacitive loads includes: a plurality of output terminals to which the plurality of capacitive loads are to be connected; a plurality of drivers corresponding to the plurality of output terminals, each of the plurality of drivers being configured to generate a drive signal to be applied to each of the plurality of capacitive loads respectively corresponding to the plurality of drivers; and a capacitance detection circuit configured to detect a capacitance associated with each of the plurality of output terminals.

Claims

1. A driver circuit that drives a plurality of capacitive loads, comprising: a plurality of output terminals to which the plurality of capacitive loads are to be connected; a plurality of drivers that corresponds to the plurality of output terminals, respectively, and is configured to generate drive signals to be applied to the plurality of capacitive loads, respectively; a capacitance detection circuit configured to detect a plurality of capacitances associated with the plurality of output terminals, respectively; and a signal processing part configured to detect abnormality based on the plurality of capacitances associated with the plurality of output terminals, wherein if the signal processing part detects an abnormality that a capacitance of a first capacitive load among the plurality of capacitive loads, which is associated with a first driver among the plurality of drivers, increases, the first driver is configured to adjust a driving capability of the first driver to increase according to a degree of increase of the capacitance of the first capacitive load, wherein if the signal processing part detects an abnormality that the capacitance of the first capacitive load decreases, the first driver is configured to adjust the driving capability of the first driver to decrease according to a degree of decrease of the capacitance of the first capacitive load, wherein the capacitance detection circuit is configured to be turned off while the driver circuit drives the plurality of capacitive loads, and to be turned on immediately after the driver circuit is started, and wherein outputs of the plurality of drivers are set to a high impedance state while the capacitance detection circuit is in an ON state.

2. The driver circuit of claim 1, wherein the capacitance detection circuit includes: an electrostatic capacitance sensor; and a selector configured to connect the electrostatic capacitance sensor to one of the plurality of output terminals according to a control signal.

3. The driver circuit of claim 1, further comprising: a plurality of switches corresponding to the plurality of output terminals and installed between outputs of the drivers respectively corresponding to the switches and the output terminals respectively corresponding to the switches.

4. The driver circuit of claim 1, wherein the signal processing part is further configured to monitor an aging change of each of the plurality of capacitances associated with the plurality of output terminals, respectively.

5. The driver circuit of claim 1, wherein the signal processing part is further configured to detect a degree of deterioration or abnormality based on an aging change of the plurality of capacitances associated with the plurality of output terminals, respectively.

6. The driver circuit of claim 1, wherein the signal processing part is further configured to detect abnormality based on a relative relationship between the plurality of capacitances respectively associated with the plurality of output terminals.

7. The driver circuit of claim 6, wherein the signal processing part is further configured to determine that a first abnormality has occurred in a first output terminal among the plurality of output terminals when a capacitance associated with the first output terminal is larger than a capacitance associated with another output terminal among the plurality of output terminals.

8. The driver circuit of claim 6, wherein the signal processing part is further configured to determine that a second abnormality has occurred in second output terminals, which are adjacent to each other, among the plurality of output terminals when capacitances associated with the second output terminals are larger than a capacitance associated with another output terminal among the plurality of output terminals.

9. The driver circuit of claim 6, wherein the signal processing part is further configured to determine that a third abnormality has occurred in a third output terminal among the plurality of output terminals when the third output terminal is detected to be in an open state according to a capacitance associated with the third output terminal.

10. The driver circuit of claim 1, wherein the driver circuit is configured to be capable of notifying a degree of deterioration or an abnormality to outside of the driver circuit.

11. The driver circuit of claim 1, wherein the driver circuit is configured to drive a matrix type display panel.

12. The driver circuit of claim 1, wherein the driver circuit is configured to drive a printer head.

Description

BRIEF DESCRIPTION OF DRAWINGS

(1) FIG. 1 is a block diagram of a display system.

(2) FIG. 2A to FIG. 2C are waveform diagrams of a source drive voltage V.sub.S generated by a source driver.

(3) FIG. 3A to FIG. 3C are waveform diagrams of a gate drive voltage V.sub.G generated by a gate driver.

(4) FIG. 4 is a circuit diagram of a driver circuit according to an embodiment of the present disclosure.

(5) FIG. 5A is an equivalent circuit diagram of a portion of the system that does not contain an unintended parasitic capacitance, and FIG. 5B to FIG. 5D are equivalent circuit diagrams of portions of the system that contain an unintended parasitic capacitance.

(6) FIG. 6A to FIG. 6C are waveform diagrams of an output voltage Vo when first to third abnormal modes occur.

(7) FIG. 7 is a graph showing an aging change of a capacitance Cs.

(8) FIG. 8A to FIG. 8D are graphs showing capacitance distributions of a plurality of channels.

(9) FIG. 9 is a circuit diagram of a driver circuit according to an embodiment of the present disclosure.

(10) FIG. 10A and FIG. 10B are operation waveform diagrams of the driver circuit of FIG. 9.

(11) FIG. 11 is a block diagram of a display system according to an embodiment of the present disclosure.

(12) FIG. 12 is a block diagram of a printer system.

DETAILED DESCRIPTION

(13) Embodiments of the present disclosure will be now described in detail with reference to the drawings. Like or equivalent components, members, and processes illustrated in each drawing are given like reference numerals, and a repeated description thereof will be properly omitted. Further, the embodiments are presented by way of example only, and are not intended to limit the present disclosure, and any feature or combination thereof described in the embodiments may not necessarily be essential to the present disclosure.

(14) In the present disclosure, “a state where a member A is connected to a member B” includes a case where the member A and the member B are physically directly connected or even a case where the member A and the member B are indirectly connected through other member that does not affect an electrical connection state between the members A and B. Similarly, “a state where a member C is installed between a member A and a member B” includes a case where the member A and the member C or the member B and the member C are indirectly connected through other member that does not affect an electrical connection state between the members A and C or the members B and C, in addition to a case where the member A and the member C or the member B and the member C are directly connected.

(15) FIG. 4 is a circuit diagram of a driver circuit 200 according to an embodiment of the present disclosure. The driver circuit 200 is configured with N channels having a plurality of N outputs, and is configured to be able to drive a plurality of N capacitive load elements (hereinafter simply referred to as load elements) Z.sub.1 to Z.sub.N. The driver circuit 200 includes a plurality of output terminals Po.sub.1 to Po.sub.N, a plurality of drivers Dr.sub.1 to Dr.sub.N, a capacitance detection circuit 210, a signal processing part 220, and an interface circuit 230, and is a functional IC (Integrated Circuit) integrated on a single semiconductor substrate.

(16) The driver circuit 200 constitutes a system 300 together with a load circuit 310 and a host processor 320. The host processor 320 can generally control the entire system 300, and is constituted by, for example, a microcontroller.

(17) The load circuit 310 includes the plurality of N load elements Z.sub.1 to Z.sub.N. In FIG. 4, a load element Z is indicated by a capacitor symbol. However, the capacitor symbol does not limit a type of the load element Z, but it merely shows an equivalent capacitance component CL when the load element Z is viewed from an output terminal P.sub.O. For example, the load element Z is a transistor, a piezo element, a light emitting diode (LED), a thermal head, or the like.

(18) The load elements Z.sub.1 to Z.sub.N are connected to the output terminals Po.sub.1 to Po.sub.N, respectively. The drivers Dr.sub.1 to Dr.sub.N correspond to the output terminals Po.sub.1 to Po.sub.N, respectively. The output of the driver Dr.sub.# (#=1 to N) is connected to the corresponding load element Z.sub.# via the corresponding output terminal Po.sub.#. In response to a control signal CTRL.sub.#, the driver Dr.sub.# generates a drive voltage Vo.sub.# to be applied to the corresponding capacitive load element Z.sub.# and outputs it from the output terminal Po.sub.#. Control signals CTRL.sub.1 to CTRL.sub.N may be generated within the driver circuit 200 or may be provided from outside the driver circuit 200.

(19) The capacitance detection circuit 210 can be switched between on and off, and generates detection signals Ds.sub.1 to Ds.sub.N indicating electrostatic capacitances (simply referred to as capacitances) Cs.sub.1 to Cs.sub.N associated with the output terminals Po.sub.1 to Po.sub.#, respectively, in the on state. The capacitance detection circuit 210 is scheduled to be turned off during a normal operation in which the driver circuit 200 drives the load elements Z.sub.1 to Z.sub.N, and automatically turned on during the operation other than the normal operation, for example, immediately after the driver circuit 200 is started. Alternatively, the driver circuit 200 may be turned on in response to a command from an external microcontroller. During capacitance measurement by the capacitance detection circuit 210, the outputs of the drivers Dr.sub.1 to Dr.sub.N are set to a high impedance state.

(20) In the present embodiment, the detection signals Ds.sub.1 to Ds.sub.N are digital signals. The signal processing part 220 performs digital signal processing on the detection signals Ds.sub.1 to Ds.sub.N, and detects an abnormality or aging change (deterioration) of the load circuit 310.

(21) The interface circuit 230 is configured to be able to exchange data and control signals with the host processor 320. The interface circuit 230 may employ, for example, an I.sup.2C (Inter IC) interface or an SPI (Serial Peripheral Interface). For example, the interface circuit 230 is connected to a register 240, and the host processor 320 may read or write necessary data by designating an address and accessing the register.

(22) The above is a configuration of the driver circuit 200 and the system 300 including the driver circuit 200. Next, the operation of the driver circuit 200 will be described.

(23) As a result of studying the conventional driver circuit, the present inventors came to recognize that disturbance of the waveform of the output signal (drive voltage) of the driver circuit shown in FIG. 2A to FIG. 2C and FIG. 3A to FIG. 3C is based on an unintended parasitic capacitance included in the load circuit 310. It should be noted that this recognition is not a general recognition of those skilled in the art at the time of the present disclosure.

(24) FIG. 5A is an equivalent circuit diagram of a portion of the system 300 that does not include an unintended parasitic capacitance, and FIG. 5B to FIG. 5D are equivalent circuit diagrams of portions of the system 300 that include an unintended parasitic capacitance.

(25) In FIG. 5B, an unintended parasitic capacitance Cp is introduced in parallel with the load element Z.sub.#, which is hereinafter referred to as a first abnormal mode.

(26) In FIG. 5C, an unintended parasitic capacitance Cp is introduced between the load elements Z.sub.# and Z.sub.#+1 of two adjacent channels, which is hereinafter referred to as a second abnormal mode. The second abnormal mode is understood as an AC short circuit.

(27) Furthermore, the present inventors have recognized that the capacitance CL of the load element Z may be smaller than that of an initial design according to an aging change in the load circuit 310, which is referred to as a third abnormal mode.

(28) FIG. 5D shows an open abnormality in which a wiring is disconnected. When the open abnormality occurs, the capacitance on the load Z.sub.# side viewed from the output terminal Po.sub.# becomes small (a fourth abnormal mode). The open abnormality may occur due to an initial failure in the manufacturing stage, or may gradually become apparent due to the aging deterioration. The open abnormality may also be understood as an aspect of fluctuation of the capacitance and causes a waveform disturbance of the output voltage Vo.

(29) FIG. 6A to FIG. 6C are waveform diagrams of the output voltage Vo when the first to third abnormal modes occur. For comparison, a waveform at normal is indicated by a broken line.

(30) Referring to FIG. 6A, a driving capability of the driver Dr is optimized in a state where there is no parasitic capacitance. In the first abnormal mode, since the load (capacitance) of the driver Dr.sub.# is larger than that at normal, the waveform of the output voltage Vo.sub.# is rounded.

(31) Referring to FIG. 6B, in the second abnormal mode, two adjacent channels are coupled by the parasitic capacitance Cp, and the high frequency component of the output voltage Vo of one channel is superimposed as spike noise on the output voltage Vo of the other channel.

(32) Referring to FIG. 6C, in the third abnormal mode, since the load (capacitance) of the driver Dr.sub.# is smaller than that at normal, driving capability of the driver Dr.sub.# becomes excessive, and overshoot, undershoot, and subsequent ringing of the output voltage Vo.sub.# occur.

(33) In this way, the waveform disturbance of the output voltage Vo occurs due to the fluctuation of the capacitance. With the driver circuit 200 according to the embodiment, it is possible to preferably detect that some abnormality has occurred, by measuring the capacitance of each channel by the capacitance detection circuit 210.

(34) In one embodiment, the signal processing part 220 monitors aging changes of the capacitances Cs.sub.1 to Cs.sub.N of the output terminals Po.sub.1 to Po.sub.N. FIG. 7 is a graph showing an aging change of the capacitance Cs. In the graph, the horizontal axis represents time (date), and the vertical axis represents the average value (or typical value) of measured capacitance. The capacitance Cs is normalized with the initial value C.sub.INIT being 1. In this example, the capacitance Cs decreases with time. The signal processing part 220 may hold the history of the measured capacitance Cs in the register 240. Then, when a rate of change from the initial capacitance C.sub.INIT deviates from a reference range, an alert indicating aging deterioration may be generated. In this example, when the rate of change based on the initial capacitance C.sub.INIT is smaller than 0.5, an alert of abnormality is generated.

(35) A notification of the alert is provided to the host processor 320 via the interface circuit 230. The host processor 320 may alert a user of the system 300 of the aging deterioration using a user interface (not shown). The user can take measures such as replacing the load circuit 310 in order to deal with the alert of the aging deterioration.

(36) The signal processing part 220 may detect the degree of deterioration based on an aging change of the capacitance Cs and notify the host processor 320 of the degree of deterioration. The rate of change with respect to the initial capacitance may be used as the degree of deterioration, or the rate of change may be converted into the degree of deterioration using a predetermined arithmetic expression.

(37) The drivers Dr.sub.1 to Dr.sub.N are configured such that their driving capability can be adjusted according to the aging change of the measured capacitance Cs. The configuration for adjusting the driving capability is not particularly limited. For example, sizes of transistors in the output stage of the drivers Dr.sub.1 to Dr.sub.N may be varied, or a bias current flowing through the drivers Dr.sub.1 to Dr.sub.N may be varied.

(38) The driving capability of the drivers Dr.sub.1 to Dr.sub.N of all channels may be adjusted uniformly. Specifically, when the capacitance Cs decreases compared to the initial capacitance, it can be estimated that the above-described third abnormal mode has occurred.

(39) In this case, the driving capability may be decreased depending on the degree of decrease of the capacitance. This can suppress the overshoot and undershoot as well as the subsequent ringing shown in FIG. 6C.

(40) On the contrary, when the capacitance Cs increases compared to the initial capacitance, the driving capability may be increased depending on a degree of increase of the capacitance. This can suppress the waveform rounding shown in FIG. 6A.

(41) In monitoring the aging changes, a maximum value or a minimum value of the capacitances Cs.sub.1 to Cs.sub.N may be used instead of an average value of the capacitances Cs.sub.1 to Cs.sub.N. Alternatively, the capacitance Cs.sub.x of the predetermined channel CH.sub.x may be used as a representative value of the capacitance Cs.sub.1 to Cs.sub.N.

(42) In a modification, a history of the capacitance Cs may be individually monitored for all channels, and the degree of deterioration may be monitored for each channel. In this case, the driving capability of the driver may be optimized for each channel.

(43) In addition to or instead of the driving capability of the driver, the set value of the output (driving signal) of the drivers Dr.sub.1 to Dr.sub.N may be adjusted according to the aging change of the measured capacitance Cs.

(44) FIG. 8A to FIG. 8D are graphs showing capacitance distributions of a plurality of channels CH.sub.1 to CH.sub.N. In the graphs, the horizontal axis represents a channel number, and the vertical axis represents the capacitance Cs of each channel. FIG. 8A shows a capacitance distribution of the normal system 300, which is flat without dependence on a channel.

(45) FIG. 8B shows the capacitance distribution of the system 300 in which the first abnormal mode occurs. As shown, a capacitance of the channel Ch.sub.is where a parasitic capacitance Cp exists is larger than that of the other channels CH.sub.j (where j≠i). Therefore, when the capacitance Cs.sub.i of a certain channel CH.sub.j is larger than the capacitances Cs.sub.i−1 and Cs.sub.i+1 of adjacent channels (or larger than an average value of the capacitances of some or all channels), it can be estimated that the first abnormal mode has occurred in the channel CH.sub.i.

(46) FIG. 8C shows the capacitance distribution of the system 300 in which the second abnormal mode occurs. As shown, the capacitances of the two adjacent channels CH.sub.j and CH.sub.j+1 where the parasitic capacitance Cp exists are larger than that of the other channels. Therefore, when the capacitances Cs.sub.j and Cs.sub.j+1 of the two adjacent channels are larger than the capacitances Cs.sub.j−1 and Cs.sub.j+2 of adjacent channels (or larger than the average value of the capacitances of some or all channels), it can be estimated that the second abnormal mode has occurred in the channels CH.sub.j and CH.sub.j+1.

(47) FIG. 8D shows a capacitance distribution of the system 300 in which an open abnormality occurs. When a wiring is disconnected in a channel CH.sub.k, a capacitance Cs.sub.k of the channel CH.sub.k becomes very small. Therefore, when the capacitance Cs.sub.k of a certain channel CH.sub.k is larger than the capacitances Cs.sub.k−1 and Cs.sub.k+1 of adjacent channels (or larger than the average value of some or all channels), it can be estimated that an open abnormality has occurred in the channel CH.sub.k.

(48) In this way, by acquiring the capacitance distribution, it is possible to detect the first abnormality mode, the second abnormality mode, or the open abnormality based on the relative relationship among a plurality of capacitances.

(49) Further, when the driver circuit 200 detects the abnormal mode, it notifies the host processor 320 accordingly. At this time, a channel number i (j, j+1 or k) of the channel in which the abnormality is detected may be transmitted together. The channel number is useful for failure analysis of the system 300.

(50) FIG. 9 is a circuit diagram of a driver circuit 200A according to an embodiment of the present disclosure. A capacitance detection circuit 210 includes an electrostatic capacitance sensor 212, a selector 214, and an A/D converter 216.

(51) The electrostatic capacitance sensor 212 measures the electrostatic capacitance Cs connected to an input terminal 213, and outputs a detection voltage Vs indicating the electrostatic capacitance Cs from an output terminal 215. The circuit configuration of the electrostatic capacitance sensor 212 is not particularly limited, but may use a known technique. Since the electrostatic capacitance sensor 212 can use the same circuit as that used for a touch panel or an electrostatic capacitance switch, detailed description thereof is omitted here.

(52) When the capacitance detection circuit 210 measures the capacitance, the selector 214 connects the input terminal 213 of the electrostatic capacitance sensor 212 to one of the plurality of output terminals Po.sub.1 to Po.sub.N according to a control signal SEL. For example, the selector 214 includes a plurality of first switches SW1.sub.1 to SW1.sub.N. The A/D converter 216 converts the analog detection voltage Vs into a digital detection signal Ds. By sequentially selecting the plurality of output terminals Po.sub.1 to Po.sub.N by the selector 214, detection signals Ds.sub.1 to Ds.sub.N indicating the capacitances Cs.sub.1 to Cs.sub.N of the plurality of output terminals Po.sub.1 to Po.sub.N are outputted from the capacitance detection circuit 210 in a time-division manner.

(53) A plurality of second switches SW2.sub.1 to SW2.sub.N are interposed between the outputs of the drivers Dr.sub.1 to Dr.sub.N and the output terminals Po.sub.1 to Po.sub.N. In the normal driving state, the second switches SW2.sub.1 to SW2.sub.N are turned on, and are turned off when the capacitance is measured.

(54) FIG. 10A and FIG. 10B are operation waveform diagrams of the driver circuit 200A shown in FIG. 9. FIG. 10A shows the normal operation. During the normal operation, all of the first switches SW1.sub.1 to SW1.sub.N are turned off, all of the second switches SW2.sub.1 to SW2.sub.N are turned on, and output voltages Vo.sub.1 to Vo.sub.N of the drivers Dr.sub.1 to Dr.sub.N are applied to the corresponding load elements.

(55) FIG. 10B shows an abnormality detection based on the capacitance measurement. At the time of capacitance measurement, all of the second switches SW2.sub.1 to SW2.sub.N are turned off, the first switches SW1.sub.1 to SW1.sub.N are turned on in order, the capacitance Cs of a channel to be turned on is measured, and the detection signals Ds.sub.1 to Ds.sub.N are output in a time-division manner.

APPLICABILITY

(56) Next, the application of the driver circuit 200 will be described. FIG. 11 is a block diagram of a display system 100A according to an embodiment of the present disclosure. The display system 100A includes a panel 110, a gate driver 120A, and a source driver 130A. The gate driver 120A and the source driver 130A are implemented using the architecture of the driver circuit 200.

(57) The gate driver 120A includes a plurality of drivers Dr.sub.1 to Dr.sub.M and a capacitance detection circuit 210. The load element Z.sub.# of the driver Dr.sub.# is a plurality of TFTs connected to the corresponding gate line GL.sub.#. The capacitance detection circuit 210 detects the capacitances Cs.sub.1 to Cs.sub.M of the load elements Z.sub.1 to Z.sub.M connected respectively to the gate lines GL.sub.1 to GL.sub.M.

(58) The source driver 130A includes a plurality of drivers Dr.sub.1 to Dr.sub.N and a capacitance detection circuit 210. The load element Z.sub.# of the driver Dr.sub.# is a plurality of TFTs connected to the corresponding source line SL.sub.#. The capacitance detection circuit 210 detects the capacitances Cs.sub.1 to Cs.sub.M of the load elements Z.sub.1 to Z.sub.M connected respectively to the source lines SL.sub.1 to SL.sub.N.

(59) The above is the configuration of the display system 100A. By providing the capacitance detection circuit 210 in the gate driver 120A, an abnormality in a gate line can be detected. In addition, by providing the capacitance detection circuit 210 in the source driver 130A, an abnormality in a source line can be detected. Then, by integrating the detection results of the gate driver 120A and the source driver 130A, it is possible to specify a pixel in which an abnormality has occurred. That is, when an abnormality is detected in the channel CH.sub.i in the gate driver 120A and an abnormality is detected in the channel CH.sub.j in the source driver 130A, it can be confirmed that the abnormality has occurred in a pixel in the i-th row and j-th column.

(60) FIG. 12 is a block diagram of a printer system 400. The printer system 400 includes a head 410 and a printer driver 420. The head 410 includes a plurality of load elements Z.sub.1 to Z.sub.N arranged in an array. The type of a load element depends on the type of a printer. The load element is a piezo element in the case of an ink jet printer, a thermal head (a heater that generates heat by a driving current) in the case of a thermal head printer, and an LED in the case of an LED printer.

(61) The printer driver 420 is configured to be able to drive the load elements, and is constructed using the architecture of the above-described driver circuit 200.

(62) The application of the driver circuit 200 is not limited to a printer and an LCD display. For example, the present disclosure may be applied to a drive circuit for a μLED and an organic EL display, or may be applied to a drive circuit for an actuator of other channels.

(63) The disclosed embodiments are illustrative only. It should be understood by those skilled in the art that various modifications to combinations of elements or processes may be made and such modifications fall within the scope of the present disclosure.

First Modification

(64) In the embodiment, an abnormality is detected in the driver circuit 200 by the signal processing of the signal processing part 220, but the present disclosure is not limited thereto. The signal processing for detecting the abnormality may be performed by the host processor 320. In a first modification, the capacitances Cs.sub.1 to Cs.sub.N measured by the capacitance detection circuit 210 may be delivered to the host processor 320 via the interface circuit 230, and the host processor 320 may determine whether or not there is an abnormality (or an abnormal mode).

(65) The voltage output type driver circuit has been described in the embodiment of the present disclosure. However, the present disclosure is not limited thereto and may be applied to a current output type driver circuit. For example, when a load to be driven is an LED or a thermal head, the driver circuit includes a current sink type (or current source type) driver Dr.

(66) According to the present disclosure in some embodiments, it is possible to detect load abnormality and deterioration.

(67) While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosures. Indeed, the embodiments described herein may be embodied in a variety of other forms. Furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the disclosures. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosures.