Envelope tracking integrated circuit and related apparatus

Abstract

An envelope tracking (ET) integrated circuit (IC) (ETIC) is provided. The ETIC includes a number of ET circuits coupled to a number of amplifier circuits configured to amplify a radio frequency signal based on a number of ET voltages, respectively. The ET circuits are configured to generate the ET voltages based on a number of ET target voltages, respectively. The ETIC includes a reference ET circuit configured to generate a reference ET voltage based on a maximum ET target voltage among the ET target voltages. A selected ET circuit(s) among the ET circuits may be configured to not generate a respective ET voltage(s) but instead forward the reference ET voltage to a respective amplifier circuit(s) as the respective ET voltage(s). Hence, it may be possible to partially or completely turn off the selected ET circuit(s) to help reduce peak battery current and improve heat dissipation in an ET amplifier apparatus.

Claims

1. An envelope tracking (ET) integrated circuit (IC) (ETIC) comprising: a plurality of amplifier ports coupled to a plurality of amplifier circuits configured to amplify a radio frequency (RF) signal based on a plurality of ET voltages, respectively; a plurality of ET circuits coupled to the plurality of amplifier ports, respectively, and configured to: generate the plurality of ET voltages based on a plurality of ET target voltages, respectively; and provide the plurality of ET voltages to the plurality of amplifier ports, respectively; and a reference ET circuit configured to: generate a reference ET voltage based on a maximum ET target voltage among the plurality of ET target voltages; and provide the reference ET voltage to the plurality of ET circuits; wherein at least one selected ET circuit among the plurality of ET circuits is configured to: stop providing a respective ET voltage among the plurality of ET voltages to at least one selected amplifier port coupled to the at least one selected ET circuit; and provide the reference ET voltage to the at least one selected amplifier port coupled to the at least one selected ET circuit.

2. The ETIC of claim 1, wherein the at least one selected ET circuit is configured to receive a respective ET target voltage among the plurality of ET target voltages that equals the maximum ET target voltage.

3. The ETIC of claim 1, further comprising: a multi-level charge pump (MCP) configured to generate a plurality of direct current (DC) voltages based on a battery voltage; and an inductor coupled to the plurality of ET circuits and configured to generate a direct current based on a selected DC voltage among the plurality of DC voltages.

4. The ETIC of claim 3, wherein the reference ET circuit comprises: a reference voltage amplifier configured to generate the reference ET voltage based on the maximum ET target voltage; and a reference controller configured to: determine a desired level of the direct current based on the maximum ET target voltage; and control the MCP to output the selected DC voltage to cause the inductor to generate the direct current at the desired level.

5. The ETIC of claim 4, wherein the plurality of ET circuits comprises: a plurality of switching/regulating circuits comprising: a plurality of inputs each coupled to the inductor and the reference ET circuit to receive the direct current and the reference ET voltage; and a plurality of outputs coupled to the plurality of amplifier ports and configured to provide the direct current to the plurality of amplifier ports, respectively; a plurality of voltage amplifiers coupled to the plurality of outputs and configured to: generate the plurality of ET voltages based on the plurality of ET target voltages, respectively; generate a plurality of alternating currents based on the plurality of ET voltages, respectively; and provide the plurality of ET voltages and the plurality of alternating currents to the plurality of amplifier ports, respectively; and a plurality of controllers configured to control the plurality of switching/regulating circuits to regulate the direct current based on the plurality of ET voltages, respectively, prior to providing the direct current to the plurality of amplifier ports.

6. The ETIC of claim 5, wherein a respective controller in the at least one selected ET circuit is further configured to: deactivate a respective voltage amplifier to stop providing the respective ET voltage and a respective alternating current to the at least one selected amplifier port; and control a respective switching/regulating circuit to provide the reference ET voltage to the at least one selected amplifier port.

7. The ETIC of claim 6, wherein: the reference voltage amplifier is further configured to generate a reference alternating current based on the reference ET voltage; and the respective controller in the at least one selected ET circuit is further configured to control the respective switching/regulating circuit to cause the reference alternating current to be provided to the at least one selected amplifier port.

8. The ETIC of claim 5, wherein a respective controller in the at least one selected ET circuit is further configured to: cause a respective voltage amplifier to provide a respective alternating current to the at least one selected amplifier port; and control a respective switching/regulating circuit to block the reference ET voltage from the at least one selected amplifier port.

9. The ETIC of claim 8, wherein: the reference voltage amplifier is further configured to generate a reference alternating current based on the reference ET voltage; and the respective controller in the at least one selected ET circuit is further configured to control the respective switching/regulating circuit to regulate the reference alternating current.

10. An envelope tracking (ET) amplifier apparatus comprising: a plurality of amplifier circuits configured to amplify a radio frequency (RF) signal based on a plurality of ET voltages, respectively; and an ET integrated circuit (ETIC) comprising: a plurality of amplifier ports coupled to the plurality of amplifier circuits, respectively; a plurality of ET circuits coupled to the plurality of amplifier ports, respectively, and configured to: generate the plurality of ET voltages based on a plurality of ET target voltages, respectively; and provide the plurality of ET voltages to the plurality of amplifier ports, respectively; and a reference ET circuit configured to: generate a reference ET voltage based on a maximum ET target voltage among the plurality of ET target voltages; and provide the reference ET voltage to the plurality of ET circuits; wherein at least one selected ET circuit among the plurality of ET circuits is configured to: stop providing a respective ET voltage among the plurality of ET voltages to at least one selected amplifier port coupled to the at least one selected ET circuit; and provide the reference ET voltage to the at least one selected amplifier port coupled to the at least one selected ET circuit.

11. The ET amplifier apparatus of claim 10, wherein the at least one selected ET circuit is configured to receive a respective ET target voltage among the plurality of ET target voltages that equals the maximum ET target voltage.

12. The ET amplifier apparatus of claim 10, wherein the ETIC further comprises: a multi-level charge pump (MCP) configured to generate a plurality of direct current (DC) voltages based on a battery voltage; and an inductor coupled to the plurality of ET circuits and configured to generate a direct current based on a selected DC voltage among the plurality of DC voltages.

13. The ET amplifier apparatus of claim 12, wherein the reference ET circuit comprises: a reference voltage amplifier configured to generate the reference ET voltage based on the maximum ET target voltage; and a reference controller configured to: determine a desired level of the direct current based on the maximum ET target voltage; and control the MCP to output the selected DC voltage to cause the inductor to generate the direct current at the desired level.

14. The ET amplifier apparatus of claim 13, wherein the plurality of ET circuits comprises: a plurality of switching/regulating circuits comprising: a plurality of inputs each coupled to the inductor and the reference ET circuit to receive the direct current and the reference ET voltage; and a plurality of outputs coupled to the plurality of amplifier ports and configured to provide the direct current to the plurality of amplifier ports, respectively; a plurality of voltage amplifiers coupled to the plurality of outputs and configured to: generate the plurality of ET voltages based on the plurality of ET target voltages, respectively; generate a plurality of alternating currents based on the plurality of ET voltages, respectively; and provide the plurality of ET voltages and the plurality of alternating currents to the plurality of amplifier ports, respectively; and a plurality of controllers configured to control the plurality of switching/regulating circuits to regulate the direct current based on the plurality of ET voltages, respectively, prior to providing the direct current to the plurality of amplifier ports.

15. The ET amplifier apparatus of claim 14, wherein a respective controller in the at least one selected ET circuit is further configured to: deactivate a respective voltage amplifier to stop providing the respective ET voltage and a respective alternating current to the at least one selected amplifier port; and control a respective switching/regulating circuit to provide the reference ET voltage to the at least one selected amplifier port.

16. The ET amplifier apparatus of claim 15, wherein: the reference voltage amplifier is further configured to generate a reference alternating current based on the reference ET voltage; and the respective controller in the at least one selected ET circuit is further configured to control the respective switching/regulating circuit to cause the reference alternating current to be provided to the at least one selected amplifier port.

17. The ET amplifier apparatus of claim 14, wherein a respective controller in the at least one selected ET circuit is further configured to: cause a respective voltage amplifier to provide a respective alternating current to the at least one selected amplifier port; and control a respective switching/regulating circuit to block the reference ET voltage from the at least one selected amplifier port.

18. The ET amplifier apparatus of claim 17, wherein: the reference voltage amplifier is further configured to generate a reference alternating current based on the reference ET voltage; and the respective controller in the at least one selected ET circuit is further configured to control the respective switching/regulating circuit to regulate the reference alternating current.

19. The ET amplifier apparatus of claim 10, further comprising a target voltage circuit configured to: receive the maximum ET target voltage; provide the maximum ET target voltage to the reference ET circuit; scale the maximum ET target voltage to generate the plurality of ET target voltages to be lower than or equal to the maximum ET target voltage; and provide the plurality of ET target voltages to the plurality of ET circuits, respectively.

20. The ET amplifier apparatus of claim 19, further comprising a transceiver circuit configured to: generate and provide the maximum ET target voltage to the target voltage circuit; generate the RF signal in a plurality of phase terms; and provide the RF signal in the plurality of phase terms to the plurality of amplifier circuits, respectively, for concurrent transmission.

Description

BRIEF DESCRIPTION OF THE DRAWING FIGURES

(1) The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure.

(2) FIG. 1 is a schematic diagram of an exemplary envelope tracking (ET) integrated circuit (IC) (ETIC) configured according to an embodiment of the present disclosure to provide a number of ET voltages to a number of amplifier circuits for amplifying a radio frequency (RF) signal; and

(3) FIG. 2 is a schematic diagram of an exemplary ET amplifier apparatus incorporating the ETIC of FIG. 1.

DETAILED DESCRIPTION

(4) The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims.

(5) It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

(6) It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present.

(7) Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures.

(8) The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

(9) Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

(10) Embodiments of the disclosure relate to an envelope tracking (ET) integrated circuit (IC) (ETIC) and related ET amplifier apparatus. The ETIC includes a number of ET circuits coupled to a number of amplifier circuits configured to amplify a radio frequency (RF) signal based on a number of ET voltages, respectively. The ET circuits are configured to generate the ET voltages based on a number of ET target voltages, respectively. The ETIC also includes a reference ET circuit configured to generate a reference ET voltage based on a maximum ET target voltage among the ET target voltages. In examples discussed herein, a selected ET circuit(s) among the ET circuits is originally configured to generate a respective ET voltage(s) based on a respective ET target voltage(s) that happens to be the maximum ET target voltage. In this regard, the selected ET circuit(s) may be configured to not generate the respective ET voltage(s). Instead, the selected ET circuit may forward the reference ET voltage to a respective amplifier circuit(s) as the respective ET voltage. As such, it may be possible to partially or completely turn off the selected ET circuit(s), thus helping to reduce peak battery current and improve heat dissipation in an ET amplifier apparatus incorporating the ETIC.

(11) In this regard, FIG. 1 is a schematic diagram of an exemplary ETIC 10 configured according to an embodiment of the present disclosure to provide a number of ET voltages V.sub.CC-1-V.sub.CC-N to a number of amplifier circuits 12(1)-12(N) for amplifying an RF signal 14. The ETIC 10 is coupled to the amplifier circuits 12(1)-12(N) via a number of amplifier ports 16(1)-16(N), respectively. The ETIC 10 includes a number of ET circuits 18(1)-18(N) that are coupled to the amplifier ports 16(1)-16(N), respectively. The ET circuits 18(1)-18(N) are configured to generate the ET voltages V.sub.CC-1-V.sub.CC-N based on a number of ET target voltages V.sub.TGT-1-V.sub.TGT-N, respectively. In other words, the ET voltages V.sub.CC-1-V.sub.CC-N are generated to rise and fall in accordance with the ET target voltages V.sub.TGT-1-V.sub.TGT-N, respectively. Understandably, the closer the ET voltages V.sub.CC-1-V.sub.CC-N track the ET target voltages V.sub.TGT-1-V.sub.TGT-N, the more efficient the amplifier circuits 12(1)-12(N) will become.

(12) In a non-limiting example, the amplifier circuits 12(1)-12(N) are configured to amplify the RF signal 14, which may have been modulated in same or different phase terms θ.sub.1-θ.sub.N, for concurrent transmission in a formed RF beam (also known as “beamforming”). In this regard, the ET circuits 18(1)-18(N) may be required to operate concurrently to provide the ET voltages V.sub.CC-1-V.sub.CC-N to the amplifier circuits 12(1)-12(N), respectively. Notably, each of the ET circuits 18(1)-18(N) will draw a respective battery current while generating a respective ET voltage among the ET voltages V.sub.CC-1-V.sub.CC-N. As such, the ET circuits 18(1)-18(N) may cause a substantial amount of heat to potentially degrade performance of the ETIC 10.

(13) Although the RF signal 14 may have been modulated in the phase terms θ.sub.1-θ.sub.N prior to being amplified by the amplifier circuits 12(1)-12(N), some or all of the RF signal 14 in the phase terms θ.sub.1-θ.sub.N can correspond to identical peak-to-peak signal amplitudes. In this regard, some or all of the ET circuits 18(1)-18(N) may generate an identical ET voltage among the ET voltages V.sub.CC-1-V.sub.CC-N based on an identical ET target voltage among the ET target voltages V.sub.TGT-1-V.sub.TGT-N. As such, it may be possible to generate the identical ET voltage using a single ET circuit and power off some or all of the ET circuits 18(1)-18(N) to help reduce battery current drain and improve heat dissipation in the ETIC 10.

(14) In this regard, the ETIC 10 is configured to include a reference ET circuit 20 in addition to the ET circuits 18(1)-18(N). The reference ET circuit 20 is configured to generate a reference ET voltage V.sub.CCr based on a maximum ET target voltage V.sub.TGT-MAX among the ET target voltages V.sub.TGT-1-V.sub.TGT-N. In one non-limiting example, the maximum ET target voltage V.sub.TGT-MAX can be equal to a maximum of the ET target voltages V.sub.TGT-1-V.sub.TGT-N. In another non-limiting example, the maximum ET target voltage V.sub.TGT-MAX can be equal to the maximum of the ET target voltages V.sub.TGT-1-V.sub.TGT-N plus a headroom voltage (e.g., 0.1 V). In other words, the maximum ET target voltage V.sub.TGT-MAX is greater than or equal to any of the ET target voltages V.sub.TGT-1-V.sub.TGT-N.

(15) Accordingly, at least one selected ET circuit among the ET circuits 18(1)-18(N) may be configured to stop providing a respective ET voltage V.sub.CC1 to at least one selected amplifier port among the amplifier ports 16(1)-16(N) that is coupled to the selected ET circuit. Instead, the selected ET circuit can be configured to provide the reference ET voltage V.sub.CCr to the coupled amplifier port. Accordingly, it may be possible to partially or completely turn off the selected ET circuit to help reduce battery current drain and improve heat dissipation in the ETIC 10.

(16) The selected ET circuit can be any ET circuit(s) among the ET circuits 18(1)-18(N) that may have been configured to receive a respective ET target voltage(s) that is equal to the maximum ET target voltage V.sub.TGT-MAX or less than the maximum ET target voltage V.sub.TGT-MAX by a defined margin (e.g., 0.1 V). For example, the ET circuit 18(1) may have been configured to receive the ET target voltage V.sub.TGT-1 that equals the maximum ET target voltage V.sub.TGT-MAX or is less than the maximum ET target voltage V.sub.TGT-MAX by the defined margin. As such, the ET circuit 18(1) may become the selected ET circuit that is configured to stop providing the respective ET voltage V.sub.CC1 to the amplifier port 16(1) and forward the reference ET voltage V.sub.CCr to the amplifier port 16(1) instead. Accordingly, the ET circuit 18(1) may be partially or completely turned off. Notably, as more of the ET circuits 18(1)-18(N) can operate as the selected ET circuit, more of the ET circuits 18(1)-18(N) can be partially or completely turned off and, therefore, more heat dissipation improvement can be achieved in the ETIC 10.

(17) The ETIC 10 can be configured to include a direct current (DC) circuit 22, which may include a multi-level charge pump (MCP) 24 coupled in series to an inductor 26. In a non-limiting example, the MCP 24 can be a combination of micro-inductance-based and micro-capacitance-based buck-boost circuits configured to generate a number of DC voltages V.sub.DC1-V.sub.DCM based on a battery voltage V.sub.BAT. Although the MCP 24 is capable of generating the DC voltages V.sub.DC1-V.sub.DCM at different levels, the MCP 24 is configured to output only a selected DC voltage V.sub.DC among the DC voltages V.sub.DC1-V.sub.DCM at a given time. Accordingly, the inductor 26 can generate a direct current I.sub.DC based on the selected DC voltage V.sub.DC.

(18) The reference ET circuit 20 includes a reference voltage amplifier 28 (denoted as “R-AMP”) and a reference controller 30 (denoted as “R-CONTROLLER”). The reference voltage amplifier 28 is configured to receive the maximum ET target voltage V.sub.TGT-MAX and generate an initial reference ET voltage V′.sub.CCr based on the maximum ET target voltage V.sub.TGT-MAX. The reference voltage amplifier 28 may be coupled to a reference offset capacitor 32. The reference offset capacitor 32 may be configured to raise the initial reference ET voltage V′.sub.CCr by a reference offset voltage V.sub.OFFr (e.g., 0.8 V) to generate the reference ET voltage V.sub.CCr (V.sub.CCr=V′.sub.CCr+V.sub.OFFr). In addition, the reference voltage amplifier 28 may also be configured to source a reference alternating current I.sub.ACr in accordance with the maximum ET target V.sub.TGT-MAX.

(19) In a non-limiting example, the reference ET circuit 20 and the DC circuit 22 are coupled to a coupling node 34. In this regard, the reference ET circuit 20 is configured to provide the reference ET voltage V.sub.CCr and the reference alternating current I.sub.ACr to the coupling node 34 and the DC circuit 22 is configured to provide the direct current I.sub.DC to the coupling node 34. The coupling node 34 may be coupled to the ET circuits 18(1)-18(N) to provide the reference ET voltage V.sub.CCr and a reference ET current I.sub.CCr (I.sub.CCr=I.sub.DC+I.sub.ACr) to any of the ET circuits 18(1)-18(N).

(20) The reference controller 30 may be configured to receive the initial reference ET voltage V′.sub.CCr and the reference ET voltage V.sub.CCr. Accordingly, the reference controller 30 may determine a desired level of the direct current I.sub.DC based on the initial reference ET voltage V′.sub.CCr and/or the reference ET voltage V.sub.CCr. Accordingly, the reference controller 30 may control the MCP 24 to output the selected DC voltage V.sub.DC that corresponds to the desired level of the direct current I.sub.DC. The reference controller 30 may be further configured to control the reference voltage amplifier 28 (e.g., by adjusting supply voltage to output stage of the reference voltage amplifier 28) to change the initial reference ET voltage V′.sub.CCr and/or the reference alternating current I.sub.ACr in accordance with the maximum ET target voltage V.sub.TGT-MAX.

(21) The ET circuits 18(1)-18(N) include a number of switching/regulating circuits 36(1)-36(N), a number of voltage amplifiers 38(1)-38(N) (denoted as “AMP”), and a number of controllers 40(1)-40(N), respectively. The switching/regulating circuits 36(1)-36(N) include a number of inputs 42(1)-42(N) and a number of outputs 44(1)-44(N), respectively. Each of the inputs 42(1)-42(N) is coupled to the coupling node 34, and thus to the reference ET circuit 20 and the DC circuit 22. As such, each of the switching/regulating circuits 36(1)-36(N) may receive the reference ET voltage V.sub.CCr, the direct current I.sub.DC, and the reference alternating current I.sub.ACr. The outputs 44(1)-44(N) are coupled to the amplifier ports 16(1)-16(N), respectively.

(22) The voltage amplifiers 38(1)-38(N) are configured to generate a number of initial ET voltages V′.sub.CC-1-V′.sub.CC-N based on the ET target voltages V.sub.TGT-1-V.sub.TGT-N, respectively. The voltage amplifiers 38(1)-38(N) may be coupled to a number of offset capacitors 46(1)-46(N), respectively. The offset capacitors 46(1)-46(N) are configured to raise the initial ET voltages V′.sub.CC-1-V′.sub.CC-N by a number of offset voltages V.sub.OFF-1-V.sub.OFF-N to generate the ET voltages V.sub.CC-1-V.sub.CC-N, respectively. The offset capacitors 46(1)-46(N) are coupled to the outputs 44(1)-44(N) to present the ET voltages V.sub.CC-1-V.sub.CC-N at the outputs 44(1)-44(N), respectively. In addition, the voltage amplifiers 38(1)-38(N) may also be configured to source a number of alternating currents I.sub.AC-1-I.sub.AC-N and present the alternating currents I.sub.AC-1-I.sub.AC-N at the outputs 44(1)-44(N), respectively.

(23) Given that the reference ET circuit 20 is configured to generate the reference ET voltage V.sub.CCr based on the maximum ET target voltage V.sub.TGT-MAX that is higher than or equal to any of the ET target voltages V.sub.TGT-1-V.sub.TGT-N, the reference ET voltage V.sub.CCr presented at the inputs 42(1)-42(N) will be higher than or equal to the ET voltages V.sub.CC-1-V.sub.CC-N presented at the outputs 44(1)-44(N). As such, the switching/regulating circuits 36(1)-36(N) may prevent the direct current I.sub.DC, the reference alternating current I.sub.ACr, and the alternating currents I.sub.AC-1-I.sub.AC-N from flowing back toward the reference ET circuit 20 and the DC circuit 22.

(24) In a non-limiting example, the voltage amplifier 38(1) in the ET circuit 18(1) is configured to receive the ET target voltage V.sub.TGT-1 that is either equal to the maximum ET target voltage V.sub.TGT-MAX or within the defined margin from the maximum ET target voltage V.sub.TGT-MAX. As such, the controller 40(1) may be configured to deactivate the voltage amplifier 38(1) to stop providing the ET voltage V.sub.CC-1 and the alternating current I.sub.AC-1 to the amplifier port 16(1). Instead, the controller 40(1) may configure the switching/regulating circuit 36(1) to operate as a closed switch to couple the input 42(1) directly to the amplifier port 16(1) such that the amplifier port 16(1) can receive the reference ET voltage V.sub.CCr, the direct current I.sub.DC, and the reference alternating current I.sub.ACr.

(25) In the meantime, the rest of the voltage amplifiers 38(2)-38(N) may be configured to receive the ET target voltages V.sub.TGT-2-V.sub.TGT-N that are below the maximum ET target voltage V.sub.TGT-MAX by more than the defined margin. In this regard, the controllers 40(2)-40(N) are configured to keep the voltage amplifiers 38(2)-38(N) activated to generate the ET voltages V.sub.CC-2-V.sub.CC-N and the alternating currents I.sub.AC-2-I.sub.AC-N, respectively. Accordingly, the controllers 40(2)-40(N) may control the switching/regulating circuits 36(2)-36(N) to block the reference ET voltage V.sub.CCr and/or the reference alternating current I.sub.ACr from the amplifier ports 16(2)-16(N), respectively. Further, the controllers 40(2)-40(N) may configure the switching/regulating circuits 36(2)-36(N) to operate as regulators (e.g., low-dropout regulators) to adjust an amount of the direct current I.sub.DC flowing to the amplifier ports 16(2)-16(N), respectively. In a non-limiting example, the controllers 40(2)-40(N) may configure the switching/regulating circuits 36(2)-36(N) to adjust the amount of the direct current I.sub.DC flowing to the amplifier ports 16(2)-16(N) in accordance with the ET voltages V.sub.CC-2-V.sub.CC-N, respectively.

(26) In another non-limiting example, instead of deactivating the voltage amplifier 38(1) in the ET circuit 18(1), the controller 40(1) may be configured to keep the voltage amplifier 38(1) activated to provide the ET voltage V.sub.CC-1 to the amplifier port 16(1). The controller 40(1) may control the switching/regulating circuit 36(1) to block the reference ET voltage V.sub.CCr. The controller 40(1) may configure the switching/regulating circuit 36(1) to operate as a regulator to regulate the direct current I.sub.DC and/or the reference alternating current I.sub.ACr. For example, the controller 40(1) may configure the switching/regulating circuit 36(1) to pass one-half (½) of the reference alternating current I.sub.ACr and control the voltage amplifier 38(1) to supplement the other ½ of the reference alternating current I.sub.ACr (I.sub.AC-1=½I.sub.ACr).

(27) In the event that all of the voltage amplifiers 38(1)-38(N) are configured to receive the ET target voltages V.sub.TGT-1-V.sub.TGT-N that are either equal to the maximum ET target voltage V.sub.TGT-MAX or within the defined margin below the maximum ET target voltage V.sub.TGT-MAX, the controllers 40(1)-40(N) may be configured to deactivate all of the voltage amplifiers 38(1)-38(N), respectively. In this regard, the controllers 40(1)-40(N) can configure all of the switching/regulating circuits 36(1)-36(N) to operate as switches to provide the reference ET voltage V.sub.CCr, the direct current I.sub.DC, and the reference alternating current I.sub.ACr to the amplifier ports 16(1)-16(N), respectively.

(28) Alternatively, the controllers 40(1)-40(N) may also keep all of the voltage amplifiers 38(1)-38(N) activated to provide the ET voltages V.sub.CC-1-V.sub.CC-N to the amplifier ports 16(1)-16(N), respectively. In addition, the controllers 40(1)-40(N) may configure the switching/regulating circuits 36(1)-36(N) to block the reference ET voltage V.sub.CCr from the amplifier ports 16(1)-16(N), respectively. Further, the controllers 40(1)-40(N) may control the switching/regulating circuits 36(1)-36(N) to regulate the direct current I.sub.DC and the reference alternating current I.sub.ACr that flow from the switching/regulating circuits 36(1)-36(N) to the amplifier ports 16(1)-16(N). Accordingly, the controllers 40(1)-40(N) may cause the voltage amplifiers 38(1)-38(N) to reduce or eliminate the alternating currents I.sub.AC-1-I.sub.AC-N to help improve efficiency of the voltage amplifiers 38(1)-38(N).

(29) The ETIC 10 may be provided in an ET amplifier apparatus to enable ET operation with improved heat dissipation. In this regard, FIG. 2 is a schematic diagram of an exemplary ET amplifier apparatus 48 incorporating the ETIC 10 of FIG. 1. Common elements between FIGS. 1 and 2 are shown therein with common element numbers and will not be re-described herein.

(30) The ET amplifier apparatus 48 includes a target voltage circuit 50 configured to generate and provide the maximum ET target voltage V.sub.TGT-MAX and the ET target voltages V.sub.TGT-1-V.sub.TGT-N to the ETIC 10. In a non-limiting example, the target voltage circuit 50 includes a voltage controller 52, a number of multipliers 54(1)-54(N), and a number of combiners 56(1)-56(N). The voltage controller 52 is configured to receive the maximum ET target voltage V.sub.TGT-MAX as an input and forward the maximum ET target voltage V.sub.TGT-MAX to the ETIC 10. The voltage controller 52 may be configured to provide the maximum ET target voltage V.sub.TGT-MAX to the multipliers 54(1)-54(N) configured to scale the maximum ET target voltage V.sub.TGT-MAX to generate the ET target voltages V.sub.TGT-1-V.sub.TGT-N lower than or equal to the maximum ET target voltage V.sub.TGT-MAX based on a number of look-up tables (LUTs) corresponding to a number of slopes SLOPE.sub.1-SLOPE.sub.N, respectively. The combiners 56(1)-56(N) are configured to further adjust the ET target voltages V.sub.TGT-1-V.sub.TGT-N based on a number of offset factors OFFSET.sub.1-OFFSET.sub.N, respectively. For an exemplary implementation of a target voltage circuit, such as the target voltage circuit 50, please refer to U.S. patent application Ser. No. 16/270,119, entitled “MULTI-VOLTAGE GENERATION CIRCUIT AND RELATED ENVELOPE TRACKING AMPLIFIER APPARATUS” and filed on Feb. 7, 2019.

(31) The ET amplifier apparatus 48 may include or be coupled to a transceiver circuit 58 configured to generate the maximum ET target voltage V.sub.TGT-MAX and the RF signal 14. The ET amplifier apparatus 48 may also include a signal processing circuit 60 configured to modulate the RF signal 14 into the phase terms θ.sub.1-θ.sub.N and provide the RF signal 14 in the phase terms θ.sub.1-θ.sub.N to the amplifier circuits 12(1)-12(N), respectively.

(32) Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.