METHOD OF MANUFACTURING SILICON CARBIDE SEMICONDUCTOR DEVICE

Abstract

In a method of manufacturing a silicon carbide semiconductor device that is a silicon carbide diode having a JBS structure including a mixture of a Schottky junction and a pn junction and that maintains low forward voltage through a SBD structure and enhances surge current capability, nickel silicide films are formed in an oxide film by self-alignment by causing a semiconductor substrate and a metal material film to react with one another through two sessions of heat treatment including a low-temperature heat treatment and a high-temperature heat treatment, the metal material film including sequentially a first nickel film, an aluminum film, and a second nickel film, the first nickel film being in contact with an entire area of a connecting region of a FLR and p-type regions respectively exposed in openings of the oxide film.

Claims

1. A method of manufacturing a silicon carbide semiconductor device, the method comprising: preparing a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface, the semiconductor substrate containing silicon carbide, and including a first-conductivity-type region having a main surface that forms the first main surface of the semiconductor substrate, the first-conductivity-type region having surface regions at the main surface thereof; selectively forming a plurality of first second-conductivity-type regions in the surface regions of the first-conductivity-type region; forming an oxide film on the first main surface of the semiconductor substrate, the oxide film covering the first-conductivity-type region and the first second-conductivity-type regions; forming a plurality of first openings in the oxide film by selectively removing the oxide film, the first openings exposing the first second-conductivity-type regions; forming a metal material film in the first openings of the oxide film, the metal material film being in direct contact with the first main surface of the semiconductor substrate and including sequentially from the first main surface, a first nickel film, an aluminum film, and a metal film having a melting point higher than that of aluminum; forming a compound layer on the first main surface of the semiconductor substrate in each of the first openings of the oxide film by self-alignment using the oxide film as a mask and causing the metal material film and the semiconductor substrate to react through a first heat treatment; after forming the compound layer, removing an excess portion of the metal material film excluding the compound layer; after removing the excess portion, forming a plurality of nickel silicide films in ohmic contact with the semiconductor substrate by generating a nickel silicide in the compound layer in each of the first openings through a second heat treatment at a temperature higher than a temperature of the first heat treatment; after forming the nickel silicide films, forming a contact hole connecting all of the first openings by removing the oxide film remaining between the nickel silicide films; forming a first electrode on the first main surface of the semiconductor substrate in the contact hole, the first electrode including sequentially from the first main surface, a titanium film in direct contact with the first-conductivity-type region and forming a Schottky junction therewith, and a metal electrode film containing aluminum; and forming a second electrode on the second main surface of the semiconductor substrate.

2. The method according to claim 1, wherein the metal film having a melting point higher than that of aluminum is a second nickel film.

3. The method according to claim 2, wherein a rate of a film thickness of the aluminum film relative to a film thickness of the metal material film is in a range from 20% to 55%.

4. The method according to claim 3, wherein the first nickel film has a film thickness in a range from 50 nm to 120 nm, the film thickness of the aluminum film is in a range from 25 nm to 250 nm, and the second nickel film has a film thickness in a range from 50 nm to 120 nm.

5. The method according to claim 1, wherein the metal film having a melting point higher than that of aluminum is a titanium film, a molybdenum film, or a tungsten film.

6. The method according to claim 5, wherein a rate of a film thickness of the aluminum film relative to a film thickness of the metal material film is in a range from 33% to 63%.

7. The method according to claim 6, wherein the first nickel film has a film thickness in a range from 50 nm to 120 nm, and the film thickness of the aluminum film is in a range from 25 nm to 210 nm.

8. The method according to claim 1, wherein the temperature of the first heat treatment is in a range from 500 degrees C. to 700 degrees C.

9. The method according to claim 1, wherein the temperature of the second heat treatment is in a range from 900 degrees C. to 1100 degrees C.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0039] FIG. 1 is a plan view depicting a layout of a silicon carbide semiconductor device according to an embodiment when viewed from a front side of a semiconductor substrate.

[0040] FIG. 2 is a plan view depicting a layout of the silicon carbide semiconductor device according to the embodiment when viewed from the front side of the semiconductor substrate.

[0041] FIG. 3 is a cross-sectional view of the structure along cutting line A-A in FIG. 2.

[0042] FIG. 4 is a flowchart of an outline of a method of manufacturing the silicon carbide semiconductor device according to the embodiment.

[0043] FIG. 5 is a cross-sectional view depicting a state of the silicon carbide semiconductor device according to the embodiment during manufacture.

[0044] FIG. 6 is a cross-sectional view depicting a state of the silicon carbide semiconductor device according to the embodiment during manufacture.

[0045] FIG. 7 is a cross-sectional view depicting a state of the silicon carbide semiconductor device according to the embodiment during manufacture.

[0046] FIG. 8 is a cross-sectional view depicting a state of the silicon carbide semiconductor device according to the embodiment during manufacture.

[0047] FIG. 9 is a cross-sectional view depicting a state of the silicon carbide semiconductor device according to the embodiment during manufacture.

[0048] FIG. 10 is a cross-sectional view depicting a state of the silicon carbide semiconductor device according to the embodiment during manufacture.

[0049] FIG. 11 is a cross-sectional view depicting a state of the silicon carbide semiconductor device according to the embodiment during manufacture.

[0050] FIG. 12 is a cross-sectional view depicting a state of the silicon carbide semiconductor device according to the embodiment during manufacture.

[0051] FIG. 13 is a cross-sectional view depicting a state of the silicon carbide semiconductor device according to the embodiment during manufacture.

[0052] FIG. 14 is a cross-sectional view depicting a state of the silicon carbide semiconductor device according to the embodiment during manufacture.

[0053] FIG. 15 is a cross-sectional view depicting a state of the silicon carbide semiconductor device according to the embodiment during manufacture.

[0054] FIG. 16 is a cross-sectional view schematically depicting a state of a front electrode of the silicon carbide semiconductor device according to the embodiment during manufacture.

[0055] FIG. 17 is a cross-sectional view schematically depicting a state of the front electrode of the silicon carbide semiconductor device according to the embodiment during manufacture.

[0056] FIG. 18 is a cross-sectional view schematically depicting a state of the front electrode of the silicon carbide semiconductor device according to the embodiment during manufacture.

[0057] FIG. 19 is a graph of contact resistance of the front electrode of the silicon carbide semiconductor device, for various types of metal films.

[0058] FIG. 20A is a diagram depicting a state of a conventional ohmic electrode during formation.

[0059] FIG. 20B is a diagram depicting a state of the conventional ohmic electrode during formation.

[0060] FIG. 21A is an enlarged view of the state of the conventional ohmic electrode.

[0061] FIG. 21B is an enlarged view of the state of the conventional ohmic electrode.

[0062] FIG. 22 is a plan view depicting a conventional silicon carbide semiconductor device when viewed from a front side of a semiconductor substrate.

[0063] FIG. 23 is a plan view depicting an example of a state of another conventional silicon carbide semiconductor device when viewed from a front side of a semiconductor substrate.

[0064] FIG. 24 is a cross-sectional view of the structure along cutting line AA-AA′ in in FIG. 23.

[0065] FIG. 25 is a cross-sectional view of an example of another conventional silicon carbide semiconductor device.

[0066] FIG. 26 is a cross-sectional view of an example of an ohmic electrode formed by self-alignment according a conventional method of manufacturing a silicon carbide semiconductor device.

DETAILED DESCRIPTION OF THE INVENTION

[0067] First, problems associated with the conventional techniques will be discussed. To improve the surge current tolerance of the conventional silicon carbide semiconductor device 140′ (silicon carbide diode having a JBS structure, refer to FIGS. 23 and 24) described above, when the ohmic electrode is provided only in contact with the p-type regions 113 between the semiconductor substrate 130 and the Schottky electrode (the titanium film 131), and the ohmic electrode is a nickel silicide film, contact resistance between the p-type regions 113 and the ohmic electrode cannot be sufficiently reduced and therefore, a predetermined design value of the surge current tolerance is unattainable.

[0068] To reduce the contact resistance between the p-type regions 113 and the ohmic electrode, when a mathematical area of a junction (junction area) between the p-type regions 113 and the ohmic electrode is increased and a mathematical surface area of the active region 110 is kept the same, as a junction area of the p-type regions 113 and the ohmic electrode increases, a junction area of the n.sup.−-type drift region 112 and the Schottky electrode decreases. Therefore, during forward bias, electron current flow from the n.sup.−-type drift region 112 toward the Schottky electrode decreases and reductions in forward voltage (Vf) become difficult.

[0069] Thus, to set a junction area necessary for setting the junction area of the p-type regions 113 and the ohmic electrode for a predetermined surge current tolerance and to set the junction area of the n.sup.−-type drift region 112 and the Schottky electrode to be as large as possible, the ohmic electrode is formed only on the p-type regions 113, and between adjacent p-type regions 113, the Schottky electrode is formed at an entire area of the surface of the n.sup.−-type drift region 112. Further, a material of the ohmic electrode is a stacked film of aluminum/nickel, thereby enabling reduction of the contact resistance between the p-type regions 113 and the ohmic electrode.

[0070] Nonetheless, a width w101 of the p-type regions 113 (refer to FIG. 33) is narrow at a few μm or less and therefore, patterning control for the stacked film having metals (aluminum and nickel) of two different types and differing etching rates is difficult and with consideration of process margins of mass production, the ohmic electrode is formed to have a width narrower than the width w101 of the p-type regions 113. Therefore, the p-type regions 113 and the Schottky electrode contact each other, forming a non-operating region in which the contact resistance is not reduced, whereby characteristics sufficient for increasing the pulled amount of the surge current cannot be obtained.

[0071] In the technique recited in Japanese Laid-Open Patent Publication No. 2008-282972, the metal film is patterned by photolithography and etching, thereby leaving a part that becomes the ohmic electrode 133′ (refer to FIG. 25). Therefore, the number of processes increase, leading to increases in cost. Further, patterning of the metal film is limited by the minimum processing dimension by etching and thus, is not suitable for size reductions. When size reductions are impossible, the junction area of the Schottky electrode at a surface of the semiconductor substrate 130 decreases and therefore, as described above, reduction of the forward voltage decreases.

[0072] In the technique recited in Japanese Laid-Open Patent Publication No. 2005-276978, as described above, the ohmic electrode 164 having a fine pattern is formed in the contact hole 163a of the interlayer insulating film 163 by self-alignment using the interlayer insulating film 163 as a mask, nonetheless, it was confirmed that the contact resistance between the high-concentration impurity region 162 and the ohmic electrode 164 is not sufficiently reduced. Further, when a general self-alignment technique such as that recited in Japanese Laid-Open Patent Publication No. 2008-282972 and Japanese Laid-Open Patent Publication No. 2005-276978 is applied in a case where a stacked film including an aluminum film and a nickel film is used as a material, the following problems were found to occur.

[0073] For example, a case in which the ohmic electrode 133′ is formed only on the p-type regions 113 will be described as an example. FIGS. 20A and 20B are diagrams depicting a state of a conventional ohmic electrode during formation. FIGS. 21A and 21B are enlarged views of the state of the conventional ohmic electrode. FIGS. 20A and 21A schematically depict the state of the ohmic electrode 133′ observed by a scanning electron microscope (SEM); and FIGS. 20B and 21B depict cross-sectional views near the ohmic electrode 133′.

[0074] As depicted in FIGS. 20A and 20B, an oxide film mask 171 that covers the n.sup.−-type drift region 112 between adjacent p-type regions 113 is formed on the front surface of the semiconductor substrate 130. Next, on the oxide film mask 171, in openings 171a of the oxide film mask 171, a metal material film 172 is formed so as to be in contact with the p-type regions 113. Subsequently, by a heat treatment, the metal material film 172 and the semiconductor substrate 130 are caused to react and form a silicide, whereby a nickel silicide film that becomes the ohmic electrode 133′ is formed.

[0075] When the metal material film 172 is a stacked film including an aluminum film and a nickel film, during the heat treatment for converting the contact portions where the metal material film 172 and the semiconductor substrate 130 contact each other into a silicide, aluminum atoms in the metal material film 172 enter the oxide film mask 171 and react therewith, thereby generating a product 134 in the oxide film mask 171. It was confirmed that the product 134 remains between the semiconductor substrate 130 and the Schottky electrode 131′ even after completion of the device (refer to FIGS. 21A and 21B), becoming a source of leak current.

[0076] Embodiments of a method of manufacturing a silicon carbide semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the present description and accompanying drawings, layers and regions prefixed with n or p mean that majority carriers are electrons or holes. Additionally, + or − appended to n or p means that the impurity concentration is higher or lower, respectively, than layers and regions without + or −. In the description of the embodiments below and the accompanying drawings, main portions that are identical will be given the same reference numerals and will not be repeatedly described. Further, in the present description, when Miller indices are described, “−” means a bar added to an index immediately after the “−”, and a negative index is expressed by prefixing “−” to the index.

[0077] A structure of a silicon carbide semiconductor device according to an embodiment will be described. FIGS. 1 and 2 are plan views depicting a layout of the silicon carbide semiconductor device according to the embodiment when viewed from a front side of a semiconductor substrate. FIG. 1 depicts an example of a layout of p-type regions (first second-conductivity-type regions) 13 that configure a JBS structure. FIG. 2 depicts an example of a layout of a bonding pad 41 among parts on a front surface of a semiconductor substrate (semiconductor chip) 30 containing silicon carbide (SiC).

[0078] A silicon carbide semiconductor device 40 according to the embodiment and depicted in FIGS. 1 and 2 is a silicon carbide diode having in an active region 10, at the front side of the semiconductor substrate 30, a SBD structure configured by Schottky junctions between a front electrode (first electrode) 14 (refer to FIG. 3) and an n.sup.−-type drift region (first-conductivity-type region) 12, and a JBS structure configured by pn junctions between the p-type regions 13 and the n.sup.−-type drift region 12.

[0079] The n.sup.−-type drift region 12 and the p-type regions 13 are disposed substantially evenly in a substantially uniform pattern at a surface of the active region 10. The n.sup.−-type drift region 12 and the p-type regions 13, for example, are disposed in a striped pattern extending in a same direction parallel to the front surface of the semiconductor substrate 30 and are disposed in contact with one another and repeatedly alternate one another along a width direction that is orthogonal to a longitudinal direction along which the n.sup.−-type drift region 12 and the p-type regions 13 extend in the striped pattern. The n.sup.−-type drift region 12 is exposed at the front surface of the semiconductor substrate 30, between adjacent p-type regions 13.

[0080] The active region 10 is a region in which current flows when the silicon carbide diode is in an ON state. The active region 10, for example, has a substantially rectangular planar shape and is disposed at substantially a center of the semiconductor substrate 30. The edge termination region 20 is a region between the active region 10 and ends of the semiconductor substrate 30, and surrounds a periphery of the active region 10. The edge termination region 20 is a region of the n.sup.−-type drift region 12, mitigating electric field at the front side of the semiconductor substrate 30 and sustaining a breakdown voltage. The breakdown voltage is a voltage limit at which no erroneous operation or destruction of an element occurs.

[0081] In the edge termination region 20, a voltage withstanding structure such as a junction termination extension (JTE) structure is disposed (refer to FIG. 3). The JTE structure is a voltage withstanding structure in which, from a center-side (side nearest the center of the semiconductor substrate 30) thereof to end-sides (sides nearest the ends of the semiconductor substrate 30) thereof, plural p-type regions (in FIG. 3, reference numerals 22, 23) having differing impurity concentrations are disposed in descending order of impurity concentration, in a circular concentric pattern around a center of the active region.

[0082] Further, in a connecting region 20a (refer to FIG. 3) of the edge termination region 20, a field limiting ring (FLR (second second-conductivity-type region)) 21 is disposed. The FLR 21 is a p.sup.+-type region that surrounds a periphery of the active region 10 in a substantially rectangular shape, and is in contact with a p.sup.−-type region 22 (refer to FIG. 3) that extends from the connecting region 20a of the edge termination region 20 toward the end of the semiconductor substrate 30. The FLR 21 may be in contact with the p-type regions 13, along the longitudinal direction along which the p-type regions 13 extend in the striped pattern.

[0083] The connecting region 20a of the edge termination region 20 is a region between the active region 10 and a field oxide film 15 described hereinafter; the connecting region 20a surrounding a periphery of the active region 10 and connecting the active region 10 and a voltage withstanding structure part of the edge termination region 20. The voltage withstanding structure part of the edge termination region 20 is a part of the edge termination region 20, from ends of the field oxide film 15 described hereinafter nearest the center of the semiconductor substrate 30 to ends (chip ends) of the semiconductor substrate 30, the part in which a predetermined voltage withstanding structure such as the JTE structure and an n.sup.+-type channel stopper region 24 are disposed (refer to FIG. 3).

[0084] The front electrode 14 (refer to FIG. 3) is provided on the front surface of the semiconductor substrate 30, in the active region 10. The front electrode 14 is in contact with the n.sup.−-type drift region 12 and the p-type regions 13, and is electrically connected to the n.sup.−-type drift region 12 and the p-type regions 13. On the front surface of the semiconductor substrate 30, a passivation film 18 (refer to FIG. 3) is provided. The passivation film 18 functions as protective film that protects the front electrode 14 and the element structure at the front side of the semiconductor substrate 30.

[0085] In the passivation film 18, an opening 18a that exposes a part of the front electrode 14 is provided. The part of the front electrode 14 exposed in the opening 18a of the passivation film 18 functions as the bonding pad 41. The bonding pad 41, for example, is disposed at the center of the semiconductor substrate 30. A non-depicted aluminum (Al) wire, which is a most common wiring connection when current is supplied to the bonding pad 41, is bonded (joined) to the bonding pad 41.

[0086] In FIG. 2, a bonding region 42 of the bonding pad 41 and the aluminum wire (not depicted) is indicated by a circular planar shape. For the bonding region 42 of the bonding pad 41 and the aluminum wire, for example, a mathematical surface area of about 1 square-mm has to be assumed when the aluminum wire has a diameter of 500 μm and is bonded to the bonding pad 41. A reason for this is that, at a surface of the semiconductor substrate 30, when surge voltage is applied and surge current flows in the forward direction, the flow of the surge current differs depending on the breakdown voltage of the silicon carbide diode.

[0087] While disposal of the bonding pad 41 at the center of the semiconductor substrate 30 is favorable, as described above, the n.sup.−-type drift region 12 and the p-type regions 13 are disposed substantially evenly in a substantially uniform pattern at a surface of the active region 10 and therefore, even when the bonding pad 41 is not disposed at the center of the semiconductor substrate 30, electrical characteristics are not adversely affected. Therefore, degrees of freedom for wire bonding are high.

[0088] Next, a cross-sectional view of the silicon carbide semiconductor device 40 according to the embodiment will be described. FIG. 3 is a cross-sectional view of the structure along cutting line A-A in FIG. 2. As described above, the silicon carbide semiconductor device 40 according to the embodiment includes the JBS structure and the SBD structure of the silicon carbide diode, in the active region 10 of the semiconductor substrate 30 containing silicon carbide and includes the JTE structure as the voltage withstanding structure, in the edge termination region 20.

[0089] The semiconductor substrate 30 is an epitaxial substrate in which an n.sup.−-type epitaxial layer that becomes the n.sup.−-type drift region 12 is stacked on a front surface of an n.sup.+-type starting substrate 11 that contains silicon carbide. The n.sup.+-type starting substrate 11 is an n.sup.+-type cathode region. The semiconductor substrate 30 has a main surface (surface of the n.sup.−-type epitaxial layer that constitutes the n.sup.−-type drift region 12) including the n.sup.−-type drift region 12 and regarded as the front surface and a main surface (back surface of the n.sup.+-type starting substrate 11) including the n.sup.+-type starting substrate 11 and regarded as a back surface.

[0090] In the active region 10, at a surface region of the front side of the semiconductor substrate 30, at least one of the p-type regions 13 that configure the JBS structure is selectively provided. The p-type regions 13 are provided between the front surface of the semiconductor substrate 30 and the n.sup.−-type drift region 12. The p-type regions 13 are exposed at the front surface of the semiconductor substrate 30 and are in contact with the n.sup.−-type drift region 12.

[0091] In the edge termination region 20, the FLR 21, at least one p-type region (herein, two including the p.sup.−-type region 22 and a p.sup.−−-type region 23) configuring the JTE structure, and the n.sup.+-type channel stopper region 24 are each provided in surface regions of the front side of the semiconductor substrate 30. The FLR 21 is provided in an entire area of the connecting region 20a of the edge termination region 20, the FLR 21 extending from the connecting region 20a, toward the end of the semiconductor substrate 30, and being in contact with the p.sup.−-type region 22. A region closer to the center of the semiconductor substrate 30 than is the FLR 21 is the active region 10.

[0092] The p.sup.−-type region 22 is separate from the connecting region 20a of the edge termination region 20, is disposed closer to the ends of the semiconductor substrate 30 than is the FLR 21, and is adjacent to the FLR 21. The p.sup.−−-type region 23 is disposed closer to the end of the semiconductor substrate 30 than is the p.sup.−-type region 22 and is adjacent to the p.sup.−-type region 22. The n.sup.+-type channel stopper region 24 is disposed closer to the ends of the semiconductor substrate 30 than is the p.sup.−−-type region 23 and is separate from the p.sup.−−-type region 23. The n.sup.+-type channel stopper region 24 is exposed at the ends of the semiconductor substrate 30 (chip ends).

[0093] The FLR 21, the p.sup.−-type region 22, the p.sup.−−-type region 23, and the n.sup.+-type channel stopper region 24 are disposed between the front surface of the semiconductor substrate 30 and the n.sup.−-type drift region 12. The FLR 21, the p.sup.−-type region 22, the p.sup.−−-type region 23, and the n.sup.+-type channel stopper region 24 are exposed at the front surface of the semiconductor substrate 30 and are in contact with the n.sup.−-type drift region 12. Depths of the FLR 21, the p.sup.−-type region 22, the p.sup.−−-type region 23, and the n.sup.+-type channel stopper region 24, for example, may be equal to a depth of the p-type regions 13.

[0094] The front surface of the semiconductor substrate 30 is covered by the field oxide film 15. The field oxide film 15, for example, may be a stacked film including sequentially a thermal oxide film 16 and a deposited oxide film 17. The thermal oxide film 16 is capable of improving adhesiveness between the semiconductor substrate 30 and the field oxide film 15. The field oxide film 15 includes the deposited oxide film 17, thereby enabling formation of the field oxide film 15 in a shorter time as compared to a case in which all of the field oxide film 15 is the thermal oxide film 16.

[0095] In the field oxide film 15, a contact hole 15a that exposes substantially an entire area of the front surface of the semiconductor substrate 30 in the active region 10 is provided. A sidewall (sidewall of the field oxide film 15 nearest the active region 10) of the contact hole 15a of the field oxide film 15, for example, is substantially orthogonal to the front surface of the semiconductor substrate 30. The contact hole 15a of the field oxide film 15 is provided at an entire area of the active region 10 and the connecting region 20a of the edge termination region 20.

[0096] In the contact hole 15a of the field oxide film 15, the n.sup.−-type drift region 12 and the p-type regions 13 in the active region 10, and a part of the FLR 21 in the edge termination region 20 are exposed. In the contact hole 15a of the field oxide film 15, on the front surface of the semiconductor substrate 30, the front electrode 14 that functions as an anode electrode is provided along the front surface of the semiconductor substrate 30.

[0097] The front electrode 14 has a layered structure in which a titanium film 31 and an aluminum alloy film (metal electrode film containing aluminum) 32 are sequentially stacked. In addition, the front electrode 14 has nickel silicide (NiSi) films 33 (33a, 33b) that are selectively provided lowermost, between the front surface of the semiconductor substrate 30 and the titanium film 31. The nickel silicide films 33 contain aluminum. The nickel silicide films 33 may contain carbon (C). The front electrode 14 may extend on the field oxide film 15 toward an end of the semiconductor substrate 30.

[0098] The titanium film 31 is provided in an entire area of the front surface of the semiconductor substrate 30 in the contact hole 15a, and is in contact with the n.sup.−-type drift region 12. A part of the titanium film 31 bonded to the n.sup.−-type drift region 12 is a Schottky electrode that forms a Schottky junction with the n.sup.−-type drift region 12. The titanium film 31 may extend on the field oxide film 15, toward an end of the semiconductor substrate 30 and, for example, may terminate at a position facing the FLR 21 in a depth direction.

[0099] The aluminum alloy film 32 covers an entire area of the titanium film 31, is electrically connected to the titanium film 31, and is electrically connected to the nickel silicide films 33, via the titanium film 31. The aluminum alloy film 32 may extend on the field oxide film 15, toward an end of the semiconductor substrate 30 to a greater extent that does the titanium film 31 and, for example, may terminate at a position facing the p.sup.−-type region 22 in the depth direction. The aluminum alloy film 32, for example, is an aluminum-silicon (AlSi) film. Instead of the aluminum alloy film 32, an aluminum film may be provided.

[0100] The nickel silicide films 33 include first nickel silicide films 33a provided between the p-type regions 13 and the titanium film 31 and a second nickel silicide film 33b provided between the FLR 21 and the titanium film 31. The first nickel silicide films 33a are ohmic electrodes that form ohmic contacts with the p-type regions 13. Surge current is generated in the semiconductor substrate 30 and flows in the forward direction during surge voltage application; and the first nickel silicide films 33a have a function of increasing an amount (pulled amount) of the surge current pulled out from the semiconductor substrate 30 to the front electrode 14, and improving surge current tolerance.

[0101] The first nickel silicide films 33a, as described hereinafter, are formed at parts where the p-type regions 13 and a metal material film 52 (refer to FIG. 10) deposited on the front surface of the semiconductor substrate 30 are in contact with each other, the first nickel silicide films 33a being formed by causing surface regions of the semiconductor substrate 30 and the metal material film 52 to react by a heat treatment. Thus, the first nickel silicide films 33a are provided in surface regions of the front surface of the semiconductor substrate 30, are in contact with the p-type regions 13 in the depth direction, and protrude from the front surface of the semiconductor substrate 30, in a direction away from the front surface of the semiconductor substrate 30.

[0102] The first nickel silicide films 33a each may have a width w2a that, for example, is substantially equal to a width w1 of each of the p-type regions 13. By setting the width w2a of the first nickel silicide films 33a to be equal to the width w1 of the p-type regions 13, the p-type regions 13 are not exposed at the front surface of the semiconductor substrate 30. As a result, a Schottky junction having high resistance is not formed between the p-type regions 13 and the titanium film 31, whereby forward voltage (Vf) of the silicon carbide diode may be reduced as compared to a case in which the p-type regions 13 are exposed at the front surface of the semiconductor substrate 30.

[0103] The width w2a of the first nickel silicide films 33a may be narrower than the width w1 of the p-type regions 13. By setting the width w2a of the first nickel silicide films 33a to be narrower than the width w1 of the p-type regions 13, design margins may be taken for improving positioning accuracy of a mask (remaining part of the field oxide film 15 described hereinafter, refer to FIG. 10) used when the first nickel silicide films 33a are formed. As a result, the first nickel silicide films 33a may be disposed accurately at positions facing the p-type regions 13 in the depth direction.

[0104] The second nickel silicide film 33b is an ohmic electrode that forms an ohmic contact with the FLR 21. The second nickel silicide film 33b is provided in substantially an entire area of a surface of the FLR 21 in the connecting region 20a of the edge termination region 20. The second nickel silicide film 33b is in contact with the field oxide film 15 at a sidewall of the field oxide film 15, the sidewall (outer sidewall) nearest an end of the semiconductor substrate 30. The second nickel silicide film 33b, similarly to the first nickel silicide films 33a, has a function of increasing the pulled amount of the surge current and improving surge current tolerance.

[0105] Provision of the second nickel silicide film 33b enables disposal of an ohmic electrode in the connecting region 20a of the edge termination region 20, the ohmic electrode having a same function as the first nickel silicide films 33a. As a result, even when chip size (planar dimension parallel to the front surface of the semiconductor substrate 30) is reduced, an ohmic junction area of the front electrode 14 and the semiconductor substrate 30, necessary for obtaining a predetermined surge current tolerance may be sufficiently established by a total junction area of the first and the second nickel silicide films 33a, 33b and the semiconductor substrate 30.

[0106] Further, extension of the second nickel silicide film 33b toward an end of the semiconductor substrate 30 to a position in contact with the field oxide film 15 enables maximization of the ohmic junction area of the FLR 21 and the second nickel silicide film 33b. As a result, a width w2b of the second nickel silicide film 33b is substantially equal to a width w3 of the connecting region 20a of the edge termination region 20 and as described above, the second nickel silicide film 33b may be provided in substantially an entire area of the surface of the FLR 21 in the connecting region 20a of the edge termination region 20.

[0107] Further, similarly to a case in which the width w2a of the first nickel silicide films 33a is substantially equal to the width w1 of the p-type regions 13 due to the width w2b of the second nickel silicide film 33b being substantially equal to the width w3 of the connecting region 20a of the edge termination region 20, reduction of the forward voltage of the silicon carbide diode may be facilitated. The width w2b of the second nickel silicide film 33b, for example, may be narrower than the width w3 of the connecting region 20a of the edge termination region 2. A reason for this is that the width w2a of the first nickel silicide films 33a may be narrower than the width w1 of the p-type regions 13.

[0108] The second nickel silicide film 33b, as described hereinafter, is formed at a part where the FLR 21 and the metal material film 52 that is deposited on the front surface of the semiconductor substrate 30 are in contact with each other, the second nickel silicide film 33b being formed by causing the semiconductor substrate 30 and the metal material film 52 to react by a heat treatment. The second nickel silicide film 33b is provided in a surface region of the front surface of the semiconductor substrate 30, is in contact with the FLR 21 in the depth direction, and protrudes from the front surface of the semiconductor substrate 30 in an external direction away from the front surface of the semiconductor substrate 30.

[0109] A part of the front surface of the semiconductor substrate 30 other than a part in contact with the front electrode 14 is covered by the field oxide film 15. At an uppermost surface of the front surface of the semiconductor substrate 30, the passivation film 18 containing a polyimide is provided. Here, a channel stopper electrode in contact with and electrically connected to the n.sup.+-type channel stopper region 24 may be provided at a top of the n.sup.+-type channel stopper region 24. The channel stopper electrode, for example, may be an aluminum alloy film that is formed concurrently with the aluminum alloy film 32.

[0110] The passivation film 18 is a protective film that protects the front electrode 14 and the field oxide film 15. In the passivation film 18, the opening 18a that exposes a part of the aluminum alloy film 32 is provided in the active region 10. A part of the front electrode 14 exposed in the opening 18a of the passivation film 18 functions as the bonding pad 41. A back electrode (second electrode) 19 is provided in an entire area of the back surface (back surface of the n.sup.+-type starting substrate 11) of the semiconductor substrate 30 and is electrically connected to the n.sup.+-type starting substrate 11.

[0111] Next, a method of manufacturing the silicon carbide semiconductor device 40 according to the embodiment will be described. FIG. 4 is a flowchart of an outline of the method of manufacturing the silicon carbide semiconductor device according to the embodiment. FIGS. 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, and 15 are cross-sectional views depicting states of the silicon carbide semiconductor device according to the embodiment during manufacture. FIGS. 16, 17, and 18 are cross-sectional views schematically depicting states of the front electrode of the silicon carbide semiconductor device according to the embodiment during manufacture. FIG. 19 is a graph of contact resistance of the front electrode of the silicon carbide semiconductor device, for various types of metal films.

[0112] First, as depicted in FIG. 5, a 4-layer periodic hexagonal silicon carbide crystal (4H-SiC) substrate doped with, for example, nitrogen (N) of about 1×10.sup.16/cm.sup.3 is prepared as the n.sup.+-type starting substrate (semiconductor wafer) 11. The front surface of the n.sup.+-type starting substrate 11, for example, may have an off-angle of about 4 degrees with respect to a (0001) plane. Next, on the front surface of the n.sup.+-type starting substrate 11, an n.sup.−-type epitaxial layer doped with nitrogen at about, for example, 1.8×10.sup.16/cm.sup.3, is grown, forming the n.sup.−-type drift region 12 (first process).

[0113] A thickness of the n.sup.+-type starting substrate 11 forming the n.sup.+-type cathode region, for example, may be about 350 μm. A thickness of the n.sup.−-type epitaxial layer forming the n.sup.−-type drift region 12, for example, may be about 6 μm. By the processes up to here, the semiconductor substrate (semiconductor wafer) 30 is fabricated in which the n.sup.−-type epitaxial layer forming the n.sup.−-type drift region 12 is stacked on the front surface of the n.sup.+-type starting substrate 11. As described above, regarding the semiconductor substrate 30, the main surface thereof including the n.sup.−-type drift region 12 is regarded as the front surface, while the main surface thereof including the n.sup.+-type starting substrate 11 is regarded at the back surface.

[0114] Next, as depicted in FIG. 6, by photolithography and a first ion implantation of a p-type impurity such as aluminum, in the active region 10 (refer to FIGS. 1, 3), at least one of the p-type regions 13 configuring the JBS structure, and the FLR 21 are each selectively formed in a surface region of the front surface of the semiconductor substrate 30 (step S1 (part 1): second and third processes). In FIG. 6, the p-type regions 13 are simplified and a fewer number thereof (herein, 3) as compared to FIG. 1 are depicted (similarly in FIGS. 7 to 15). The p-type regions 13 are disposed along a direction parallel to the front surface of the semiconductor substrate 30 at equal intervals of, for example, about 2 μm.

[0115] Here, the first ion implantation is performed from the front surface of the semiconductor substrate 30 to the n.sup.−-type epitaxial layer (the n.sup.−-type drift region 12) while the semiconductor substrate 30 is heated at a temperature of, for example, 500 degrees C. In the first ion implantation, for example, ion implantation of a p-type impurity is divided into plural stages at differing acceleration energies within a range from about 30 keV to 350 keV so that the impurity concentration having a box-profile from the front surface of the semiconductor substrate 30 to a depth of 500 nm becomes about 2×10.sup.19/cm.sup.3.

[0116] Next, as depicted in FIG. 7, by repeatedly performing, under differing conditions, a process including photolithography and a second ion implantation of an impurity as one set, p-type regions (the p.sup.−-type region 22 and the p.sup.−−-type region 23) configuring the JTE structure, and the n.sup.+-type channel stopper region 24 (refer to FIG. 3) are each selectively formed in surface regions of the front surface of the semiconductor substrate 30, in the edge termination region 20 (refer to FIG. 3) (step S1 (part 2)). The second ion implantation, for example, similarly to the first ion implantation, is separated into plural stages so that the impurity concentration distribution has a box-profile.

[0117] Next, as depicted in FIG. 8, after an entire area of the front surface of the semiconductor substrate 30, for example, is covered and protected by a carbon (C) protective film 50, the impurities implanted by the first and the second ion implantations are activated by a heat treatment (step S2). In the process at step S2, for example, after the semiconductor substrate 30 is inserted in a processing furnace of heat treatment equipment and an atmosphere inside the processing furnace is evacuated (vacuumed) to at most about 1×10.sup.−2 Pa, argon (Ar) gas is introduced into the processing furnace and in an atmosphere of a pressure of about 1×10.sup.5 Pa, a heat treatment at a temperature of about 1700 degrees C. is performed for about five minutes.

[0118] Next, as depicted in FIG. 9, for example, by ashing using ashing process (ashing) equipment, the carbon protective film 50 is removed. For example, as the ashing equipment, reactive ion etching (RIE) equipment is used. In a processing furnace of the RIE equipment, after an oxygen (O.sub.2) gas atmosphere of a pressure of about 6 Pa is established, high-frequency (radio frequency (RF)) power of about 500 W is applied and by ashing of about five minutes under the plasmatized oxygen gas atmosphere, the carbon protective film 50 is removed.

[0119] Next, as depicted in FIG. 10, an oxide film 51 is formed in an entire area of the front surface of the semiconductor substrate 30 (step S3: third process). Next, by photolithography and etching, the oxide film 51 is selectively removed, forming openings (first and second openings) 51a, 51b (step S4: fourth process). In the process at step S4, the plural openings 51a respectively exposing the p-type regions 13, and the one opening 51b exposing a part of the FLR 21 in a substantially rectangular shape surrounding a periphery of the active region 10, are formed in the oxide film 51.

[0120] By the process at step S4, of the oxide film 51, parts 15′ covering the n.sup.−-type drift region 12 in the active region 10 and a part forming the field oxide film 15 in the edge termination region 20 are left. After the process at step S4, all of the oxide film 51 including the part forming the field oxide film 15 is an oxide film mask used in forming the nickel silicide films 33 at a process described hereinafter. Of the oxide film 51, the parts 15′ covering the n.sup.−-type drift region 12 in the active region 10 do not remain in the product.

[0121] In other words, in the process at step S4, the field oxide film 15 and the oxide film mask used in forming the nickel silicide films 33 are formed concurrently. Therefore, the oxide film 51 has the same layered structure as that of the field oxide film 15. In particular, the oxide film 51 is a stacked oxide film having a thickness of about 500 nm, in which the thermal oxide film 16 and the deposited oxide film 17 (refer to FIG. 3) are sequentially stacked and formed by, for example, a thermal oxidation method and a chemical vapor deposition (CVD) method.

[0122] In the process at step S4, dry etching having high dimensional accuracy may be performed. As a result, the p-type regions 13 and the FLR 21 may be exposed with dimensional accuracy. Further, the outer sidewall of the opening 51b of the oxide film 51 forms a sidewall of the contact hole 15a of the field oxide film 15. Therefore, by performing dry etching in the process at step S4, the contact hole 15a of the field oxide film 15 may be formed with dimensional accuracy.

[0123] Next, for example, on the front surface (surface) of the semiconductor substrate 30 in the openings 51a, 51b of the oxide film 51, the metal material film 52 is formed spanning from the oxide film 51 by a sputtering method (step S5: fifth process). The metal material film 52 is a stacked metal film in which a first nickel film 58, an aluminum film (metal film containing aluminum) 53 and a film having a higher melting point than that of aluminum, for example, a second nickel film 54 are sequentially stacked (FIG. 16). In FIG. 10, the first nickel film 58, the aluminum film 53, and the second nickel film 54 are depicted collectively as one layer, the metal material film 52.

[0124] Here, in a silicon carbide semiconductor device, formation of an aluminum film as an ohmic electrode to reduce contact resistance with p-type regions (the p-type regions 13, the field limiting ring 21 configuring the JBS structure) is known. Nonetheless, with aluminum alone, the alloying reaction is vigorous and after the heat treatment, surface condensation occurred. Other than aluminum, use of a nickel silicide enables the contact resistance with the p-type regions to be reduced, however, reduction of sheet resistance was limited.

[0125] Therefore, when silicon carbide and nickel are converted into a silicide using the stacked metal film in which the aluminum film and the nickel film are sequentially stacked, excess carbon and aluminum react, forming Al.sub.3C, whereby reduction of the sheet resistance was enabled. Further, similarly to the nickel silicide, formation by self-alignment by two-stage sintering was possible.

[0126] Nonetheless, with the stacked metal film in which the aluminum film and the nickel film are sequentially stacked, condensation of the aluminum occurred on the front surface of the semiconductor substrate and therefore, the temperature of the first-stage of the sintering has an upper limit and the thickness of the generated silicide layer is limited. Further, by a subsequent process, a portion of the silicide layer disappears.

[0127] Thus, in the method of manufacturing the silicon carbide semiconductor device of the embodiment, the stacked metal film in which the first nickel film 58, the aluminum film 53, and the second nickel film 54 are sequentially stacked is used. The first nickel film 58 is a film that suppresses the condensation of aluminum on the surface of the semiconductor substrate 30 during a heat treatment at step S6 described hereinafter and, for example, has a thickness t3 of about 80 nm. In a case in which the first nickel film 58 is not used, the aluminum film 53 is in contact with the semiconductor substrate 30, and an Al—Ni—Si compound (compound layer) 55 described hereinafter cannot be formed uniformly spanning an entire area of the front surface of the semiconductor substrate 30.

[0128] In the embodiment, the stacked metal film has three layers including the first nickel film 58, the aluminum film 53, and the second nickel film 54, thereby enabling the thickness of the generated silicide layer to be increased. In addition, due to the first nickel film 58, even when the temperature of the first stage of the sintering (step S6 described hereinafter) is about equal to that conventionally (stacked metal film in which an aluminum film and a nickel film are sequentially stacked), the thickness of the silicide layer may be increased. Therefore, the ohmic area increases, enabling reduction of the sheet resistance.

[0129] In FIG. 19, a vertical axis indicates contact resistance in units of Ωcm.sup.2 and a horizontal axis indicates composition of the metal film for forming the silicide layer. As depicted in FIG. 19, it is found that the contact resistance is lower for Ni than for Ti, the contact resistance is lower for AlNi than for Ni, and the contact resistance (2.51×10.sup.−4 Ωcm.sup.2) is lower for NiAlNi of the embodiment than for AlNi. Further, when the metal film is NiAlNi, the film thickness is 80 nm for all.

[0130] The second nickel film 54 is a cap film that prevents melting of the aluminum film 53 during the heat treatment at step S6 described hereinafter and, for example, has a thickness t2 of about 80 nm. The cap film is used for the following reasons. When the cap film is not used, the aluminum film 53 that melts due to the heat treatment at step S6 becomes granular and partially contacts the semiconductor substrate 30. In this case, the Al—Ni—Si compound (compound layer) 55 described hereinafter cannot be formed uniformly spanning an entire area of the front surface of the semiconductor substrate 30.

[0131] Here, the second nickel film 54 is a film to prevent the aluminum melted by the heat treatment from being splattered on the surface of the semiconductor substrate 30 and therefore, may be another metal film having a higher melting point than that of aluminum such as, for example, a molybdenum (Mo), a tantalum (Ta), titanium (Ti), or a tungsten (W) film. For example, in the case of titanium, the film thickness may be about 50 nm. A nickel film may be removed by wet etching at step S7 of removing excess metal (excess portion) described hereinafter and therefore, the second nickel film 54 is more advantageous than other materials.

[0132] Further, when the metal film is the first nickel film 58, the aluminum film 53, and the second nickel film 54, a film thickness t1 of the aluminum film 53 may be 20% to 55% of the film thickness of the metal film. Further, a film thickness t3 of the first nickel film 58 may be in a range from 50 nm to 120 nm; the film thickness t1 of the aluminum film 53 may be in a range from 25 nm to 250 nm; and the film thickness t2 of the second nickel film 54 may be in a range from 50 nm to 120 nm.

[0133] Further, when the second nickel film 54 is a metal other than nickel, the film thickness t1 of the aluminum film 53 may be 33% to 63% of the film thickness of the metal film. Further, the film thickness t3 of the first nickel film 58 may be in a range from 50 nm to 120 nm and the film thickness t1 of the aluminum film 53 may be in a range from 25 nm to 210 nm. When the film thickness t1 of the aluminum film 53 is at most 20 nm, the second nickel film 54 contributes to a reaction between the aluminum film 53 and the second nickel film 54 and therefore, the film thickness t1 of the aluminum film 53 may be greater than 20 nm, or may be at least 25 nm.

[0134] Thereafter, by a heat treatment, the metal material film 52 is subject to a first sintering (sintering) (step S6: sixth process), whereby the aluminum-nickel-silicon (Al—Ni—Si) compound 55 is generated in the openings 51a, 51b of the oxide film 51 (refer to FIG. 11). A mechanism by which the Al—Ni—Si compound 55 is generated by this process (first sintering) will be described in detail using FIGS. 16 to 18.

[0135] In FIG. 16, only contact portions of the metal material film 52 and of the semiconductor substrate 30 where each is in contact with the other in the openings 51a, 51b of the oxide film 51 are depicted while other parts are not depicted (similarly in FIGS. 17, 18). In FIG. 16, while a state in one of the openings (51a, 51b) of the oxide film 51 is depicted, the state in all the openings 51a, 51b of the oxide film 51 is a same as that depicted in FIG. 16.

[0136] By the heat treatment at step S6, at the contact portions of the metal material film 52 and of the semiconductor substrate 30 in the openings 51a, 51b of the oxide film 51, silicon atoms in the semiconductor substrate 30 thermally diffuse into the aluminum film 53 (thermal diffusion 61). Aluminum atoms in the aluminum film 53 thermally diffuse into the first nickel film 58 and the second nickel film 54 (thermal diffusion 62). Nickel atoms in the first nickel film 58 thermally diffuse into the semiconductor substrate 30 (thermal diffusion 63), and nickel atoms in the second nickel film 54 thermally diffuse into the aluminum film 53 (thermal diffusion 64) (FIG. 17).

[0137] By the thermal diffusion 62 of the aluminum atoms into the second nickel film 54 and the thermal diffusion 64 of the nickel atoms into the aluminum film 53, on the front surface of the semiconductor substrate 30 and on a surface of the oxide film 51 in the openings 51a, 51b of the oxide film 51, an aluminum-nickel (AlNi) compound 56 is generated. Furthermore, the Al—Ni—Si compound 55 is generated at contact portions of the metal material film 52 and of the semiconductor substrate 30 by the thermal diffusion 62 of the aluminum atoms to the first nickel film 58, the thermal diffusion 63 of the nickel atoms to the semiconductor substrate 30, and the thermal diffusion 61 of the silicon atoms to the first nickel film 58 (FIG. 18).

[0138] The Al—Ni—Si compound 55 is generated by a reaction between the metal material film 52 and low-impurity-concentration portions of the p-type regions 13 and the FLR 21 that are diffusion regions formed by ion implantation, the low-impurity-concentration portions being from the front surface of the semiconductor substrate 30 to positions at a depth of about 20 nm to 30 nm and having a low impurity concentration. Therefore, a compound layer including the Al—Ni—Si compound 55 is formed by self-alignment using the oxide film 51 as a mask so as to cut into the semiconductor substrate 30 in the depth direction, in the openings 51a, 51b of the oxide film 51.

[0139] Further, the Al—Ni—Si compound 55 is in contact with a portion of the p-type region 13 at which the Al—Ni—Si compound 55 is formed or a portion of the FLR 21 at which the Al—Ni—Si compound 55 is formed, the portion with which the Al—Ni—Si compound 55 is in contact has an impurity concentration higher than that of the low-impurity-concentration portions and the Al—Ni—Si compound 55 is positioned at a depth deeper from the front surface of the semiconductor substrate 30 than are the low-impurity-concentration portions. The Al—Ni—Si compound 55 forms low-resistance ohmic contacts with the high impurity concentration in the p-type regions 13 or the FLR 21.

[0140] In the Al—Ni—Si compound 55, by a silicide reaction between the Al—Ni—Si compound 55 and the semiconductor substrate 30, leftover carbon (C) (hereinafter, excess carbon) in the semiconductor substrate 30 may be deposited to an extent that no layering occurs. The excess carbon is carbon atoms leftover in the semiconductor substrate 30 after consumption by the silicide reaction with the silicon atoms in the semiconductor substrate 30. In particular, the excess carbon may be deposited granularly and distributed in the Al—Ni—Si compound 55.

[0141] A period of the heat treatment at step S6, for example, may be at least two minutes with consideration of chemical reaction uniformity and may be, for example, at most about one hour with consideration of product mass production. A temperature of the heat treatment at step S6, for example, may be in a range from about 500 degrees C. to 700 degrees C. A reason for this is as follows. When the temperature of the heat treatment at step S6 exceeds 700 degrees C., the aluminum-nickel compound 56 enters and reacts with the oxide film 51 that is a silicon oxide (SiO.sub.2) film, whereby a product is generated in the oxide film 51 as described hereinafter. Next, at step S7 at which excess metal (excess portion) is removed, the nickel silicide films 33 are not removed and therefore, the product remains in the field oxide film 15 and causes leak failure during reverse bias.

[0142] When the temperature of the heat treatment at step S6 is less than 500 degrees C., the above reaction between the semiconductor substrate 30 and the metal material film 52 does not occur, the metal material film 52 is not used, and by a subsequent process at step S7, the metal material film 52 is removed entirely. The heat treatment at step S6, for example, may be performed by a heat treatment furnace for which uniform temperature management is simple. A uniform temperature means a substantially same temperature within a range that includes an allowable error due to process variation. The above is a detailed description related to the first sintering.

[0143] Next, as depicted in FIG. 12, excess metal (excess portion) on the oxide film 51 and in the openings 51a, 51b of the oxide film 51 is removed (step S7: seventh process). The excess metal is metal generated from the unreacted metal material film 52 and the metal material film 52, excluding that of the nickel silicide films 33 and in particular, the aluminum-nickel compound 56 that did not contribute to the generation of the nickel silicide films 33. In the process at step S7, for example, by wet etching using phosphorus nitric acid, an entire area of the front surface of the semiconductor substrate 30 is etched. By the process at step S7, the Al—Ni—Si compound 55 is left in each of the openings 51a, 51b of the oxide film 51.

[0144] Next, as depicted in FIG. 13, the Al—Ni—Si compound 55 is subject to a second sintering by a heat treatment (step S8: eighth process). By the heat treatment at step S8, a nickel silicide is generated in the Al—Ni—Si compound 55, and the Al—Ni—Si compound 55 is set as the nickel silicide films 33 that form ohmic contacts with the semiconductor substrate 30. As a result, in the openings 51a, 51b of the oxide film 51, the nickel silicide films 33 that form ohmic contacts with the semiconductor substrate 30 are formed, respectively, by self-alignment using the oxide film 51 as a mask.

[0145] A temperature of the heat treatment at step S8, for example, may be at a higher temperature than the temperature of the heat treatment at step S6. A temperature of the heat treatment at step S8 may be in a range from at least, for example, about 900 degrees C. to generate the nickel silicide in the Al—Ni—Si compound 55 to about, for example, at most 1100 degrees C. capable of low cost processing using a vertical heat treatment furnace. The heat treatment at step S8, for example, may be performed using a heat treatment furnace capable of uniform management of the temperature of the heat treatment.

[0146] Next, as depicted in FIG. 14, a resist film 57 opened at a formation region of the contact hole 15a of the field oxide film 15 is formed by photolithography. Next, etching is performed using the resist film 57 as a mask, thereby forming the contact hole 15a that penetrates through the field oxide film 15 in the depth direction (step S9: ninth process). In the process at step S9, of the oxide film 51, only a part that forms the field oxide film 15 is left.

[0147] In the process at step S9, of the oxide film 51, in the active region 10, the parts 15′ covering the n.sup.−-type drift region 12 are removed completely and by connecting all of the openings 51a, 51b of the oxide film 51, the contact hole 15a already formed in the process at step S4 appears. During the process at step S9, the outer sidewall of the opening 51b of the oxide film 51 is completely covered by the resist film 57 and therefore, this sidewall of the opening 51b of the oxide film 51 is not etched.

[0148] An entire area of the active region 10 and an entire area of a surface of the connecting region 20a of the edge termination region 20 are exposed in the contact hole 15a of the field oxide film 15. As a result, in the contact hole 15a of the field oxide film 15, all the nickel silicide films 33 (the nickel silicide films 33a, the nickel silicide films 33b) and parts of the n.sup.−-type drift region 12 between adjacent nickel silicide films 33 are exposed.

[0149] When the widths w2a, w2b of the first and the second nickel silicide films 33a, 33b are respectively less than the width w1 of the p-type regions 13 and less than the width w3 of the connecting region 20a of the edge termination region 20, parts of the surfaces of the p-type regions 13 and of the FLR 21, the parts not bonded to the nickel silicide films 33 are further exposed in the contact hole 15a of the field oxide film 15.

[0150] The process at step S9 may be performed by wet etching. When the process at step S9 is performed by dry etching, plasma damage due to dry etching may remain at the front surface of the semiconductor substrate 30. Even when the process at step S9 is performed by wet etching, the contact hole 15a may be formed in the field oxide film 15 with dimensional accuracy. A reason for this is that during the process at step S4, the outer sidewall of the opening 51b formed with dimensional accuracy by dry etching in the oxide film 51 is configured by the sidewall of the contact hole 15a of the field oxide film 15.

[0151] In the process at step S4, of the oxide film 51, the parts 15′ covering the n.sup.−-type drift region 12 and the part forming the field oxide film 15 are left (refer to FIG. 10). Therefore, after the process at step S4, of the oxide film 51, the parts 15′ covering the n.sup.−-type drift region 12 are left in the contact hole 15a of the field oxide film 15 and the outer sidewall of the opening 51b of the oxide film 51 configures the sidewall of the contact hole 15a of the field oxide film 15. The outer sidewall of the opening 51b of the oxide film 51 is completely covered by the resist film 57 during the process at step S9 and is not etched. Therefore, in the process at step S4 and thereafter, the position of the outer sidewall of the opening 51b of the oxide film 51 does not change.

[0152] In this manner, dimensional accuracy of the contact hole 15a of the field oxide film 15 is a same as the dimensional accuracy of the opening 51b of the oxide film 51 formed by dry etching and is not dependent on the dimensional accuracy of the wet etching in the process at step S9. Further, in the process at step S4 and thereafter, the position of the outer sidewall of the opening 51b of the oxide film 51 does not change, whereby the second nickel silicide film 33b that is formed by self-alignment using the oxide film 51 as a mask is maintained in a state of being in contact with the outer sidewall of the opening 51b of the oxide film 51 even after the process at step S9. In other words, the second nickel silicide film 33b is maintained in the state of being in contact with the field oxide film 15 at the sidewall of the contact hole 15a even after the process at step S9.

[0153] Next, as depicted in FIG. 15, for example, by a physical vapor deposition (PVD) such as sputtering, the titanium film 31 is formed from the surface of the field oxide film 15, to an entire area of the front surface of the semiconductor substrate 30 in the contact hole 15a. Next, by photolithography and etching, the titanium film 31 is left only in the contact hole 15a (step S10: tenth process). The titanium film 31 has a thickness that, for example, may be about 100 nm. The titanium film 31 may extend on the field oxide film 15, from inside the contact hole 15a.

[0154] Next, for example, the titanium film 31 is sintered by a heat treatment for about ten minutes at a temperature of about 500 degrees C. By the heat treatment, a Schottky junction between the titanium film 31 and the n.sup.−-type drift region 12 is formed. Next, for example, by a physical vapor deposition such as sputtering, an aluminum alloy film having a thickness of, for example, about 5 μm is formed from a surface of the titanium film 31, to an entire area of the surface of the field oxide film 15. Next, by photolithography and etching, the aluminum alloy film is selectively removed to be left at the surface of the titanium film 31, as the aluminum alloy film 32 that forms the front electrode 14.

[0155] Next, after the front surface of the semiconductor substrate 30 (semiconductor wafer) is covered and protected by a protective film (not depicted), the semiconductor substrate 30 is ground from a back side thereof, whereby the semiconductor substrate 30 is thinned to a product thickness. Next, for example, after nickel and/or titanium is deposited at an entire area of the back surface of the semiconductor substrate 30 (the back surface of the n.sup.+-type starting substrate 11) by a physical vapor deposition such as sputtering, laser annealing is performed, whereby the back electrode 19 is formed (step S11: eleventh process). Thereafter, after the protective film at the front surface of the semiconductor substrate 30 is removed, the semiconductor substrate 30 is diced (cut) into individual chips, whereby the silicon carbide semiconductor device 40 depicted in FIGS. 1 to 3 is completed.

[0156] As described above, according to the embodiment, the silicide layer is formed using the stacked metal film in which the first nickel film, the aluminum film, and the second nickel film are sequentially stacked. As a result, aluminum may be prevented from condensing on the surface of the semiconductor substrate during heat treatment. Therefore, even when the temperature of the sintering is equal to the conventional temperature, the thickness of the silicide layer may be increased and sheet resistance may be reduced. Further, according to the embodiment, contact resistance between the nickel silicide film that is an ohmic electrode and the semiconductor substrate may be reduced.

[0157] In the foregoing, without limitation to the embodiments described above, the present invention may be variously changed within a range not departing from the spirit of the present invention and is applicable to silicon carbide semiconductor devices that include an ohmic electrode in ohmic contact with p-type regions disposed in a predetermined pattern.

[0158] In particular, for example, the present invention is useful for silicon carbide semiconductor devices that are configured to reduce the contact resistance between a p-type region (or p.sup.+-type contact region disposed between the p-type region and a main surface of the semiconductor substrate) and an ohmic electrode, and silicon carbide semiconductor devices having a structure in which an oxide film and an ohmic electrode in ohmic contact with a p-type region are in contact with each other.

[0159] Further, for example, in a metal oxide semiconductor field effect transistor ((MOSFET) having an insulated gate of a 3-layered structure including a metal, an oxide film, and a semiconductor) having a built-in SBD on a single semiconductor substrate, the present invention is applicable to a configuration at the front side of the semiconductor substrate.

[0160] Further, in a reverse-conducting insulated gate bipolar transistor (RC-IGBT) having a structure in which an insulated gate bipolar transistor (IGBT) and a freewheeling diode (FWD) connected in antiparallel to the IGBT are built into and integrated on a single semiconductor chip, application is possible to a part at which a p-type collector region of a back side of the semiconductor substrate is formed. In an IGBT, application is possible to an entire area of the back surface of the semiconductor substrate.

[0161] The method of manufacturing a silicon carbide semiconductor device according to the present invention achieves an effect in that a low resistance ohmic electrode is formed, whereby surge current capability is high and the pulled amount of forward surge current may be enhanced while low Vf characteristics are maintained.

[0162] As described above, the silicon carbide semiconductor device and the method of manufacturing a silicon carbide semiconductor device according to the present invention are useful for power semiconductor devices used in power converting equipment and in power supply devices such those of various types of industrial machines.

[0163] Although the invention has been described with respect to a specific embodiment for a complete and clear disclosure, the appended claims are not to be thus limited but are to be construed as embodying all modifications and alternative constructions that may occur to one skilled in the art which fairly fall within the basic teaching herein set forth.