Abstract
Disclosed is a Proton Exchange Membrane Fuel Cell (PEMFC) incorporating a porous membrane element formed of a porous silicon wafer, in which the pores are coated at least in part with a noble metal. Alternatively, the porous silicon wafer may be sandwiched between paper, carbon or graphite sheet impregnated with a noble metal. The separator is formed of using MEMS Technology. Also disclosed is a lithium ion battery, has a cathode electrode; an anode electrode formed of a porous silicon substrate in which surfaces of the pores of the porous silicon substrate are coated at least in part with a metal silicide; a separator element disposed between the cathode and the anode; and an electrolyte.
Claims
1. A Proton Exchange Membrane Fuel Cell (PEMFC) comprising a separator membrane element formed of a porous silicon wafer.
2. The PEMFC of claim 1, wherein pores of the porous silicon wafer are substantially cylindrical through holes, and/or wherein the cylindrical through holes have a length to diameter aspect ratio of >50:1.
3. The PEMFC of claim 1, wherein surfaces of pores of the porous silicon wafer are coated, at least in part, with a noble metal, preferably a noble metal selected from the group consisting of silver, gold, platinum, rhodium, iridium, palladium, ruthenium and osmium.
4. The PEMFC of claim 1, wherein the porous silicon wafer is sandwiched between paper, carbon or graphite sheets impregnated with a noble metal, preferably a noble metal selected from the group consisting of silver, gold, platinum, rhodium, iridium, palladium, ruthenium and osmium.
5. A Proton Exchange Membrane Fuel Cell (PEMFC), comprising: an electrical assembly comprising positive and negative electrodes separated by a porous membrane, wherein the porous membrane comprises a porous silicon wafer.
6. The PEMFC of claim 5, wherein pores of the porous silicon wafer are substantially cylindrical though holes, and/or have a length to diameter aspect ratio of >50:1.
7. The PEMFC of claim 5, wherein the pores of the porous membrane are coated, at least in part, with a noble metal catalyst, preferably a noble metal selected from the group consisting of silver, gold, platinum, rhodium, iridium, palladium, ruthenium and osmium.
8. The PEMFC of claim 5, wherein the porous silicon wafer is sandwiched between paper, carbon or graphite sheets impregnated with a noble metal, preferably a noble metal selected from the group consisting of silver, gold, platinum, rhodium, iridium, palladium, ruthenium and osmium.
9. The PEMFC of claim 5, comprising a membrane formed by method of forming the membrane, comprising: providing a silicon wafer; etching through holes extending through at least a portion of the wafers, wherein the through holes have a length to diameter aspect ratio of >50:1; and coating surface of the holes at last in part with a noble metal, or sandwiching the etched silicon wafer between paper, carbon or graphite sheets impregnated with a noble metal, wherein the noble metal preferably is selected from the group consisting of silver, gold, platinum, rhodium, iridium, palladium, ruthenium and osmium.
10. A lithium ion battery, comprising: a cathode electrode; an anode electrode formed of a porous silicon substrate in which surfaces of the pores of the porous silicon substrate are coated at least in part with a metal silicide; a separator element disposed between the cathode and the anode; and an electrolyte.
11. The lithium ion battery of claim 10, wherein the silicon substrate comprises monocrystalline silicon, polycrystalline silicon, or amorpohous silicon.
12. The lithium ion battery of claim 10, wherein the metal silicide coating is selected from the group consisting of TiSi.sub.2, CoSi.sub.2 and WSi.sub.2.
13. The lithium ion battery of claim 10, wherein the pores have a length to diameter aspect ratio of >50:1.
14. The lithium ion battery of claim 10, wherein the electrolyte is selected from the group consisting of LiPF.sub.6, LiBF.sub.4 and LiCoO.sub.2.
15. The lithium ion battery of claim 10, wherein an anode electrode comprises a substrate formed of porous silicon in which surface areas of the pores are coated at least in part with a metal silicide.
16. The lithium ion battery of claim 15, wherein the silicon substrate comprises monocrystalline silicon, polycrystalline silicon, or amorphous silicon.
17. The lithium ion battery of claim 15, wherein the pores have a length to diameter aspect ratio of >50:1.
18. The lithium ion battery of claim 15, wherein the metal silicide is selected from the group consisting of TiSi.sub.2, CoSi.sub.2 and WSi.sub.2.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0035] Further features and advantages of the present disclosure will be seen from the following detailed description, wherein like numerals depict like parts, and wherein:
[0036] FIG. 1 is a schematic flow diagram showing formation of a porous silicon wafer useful as a membrane in a PEMFC in accordance with a first embodiment of the present disclosure;
[0037] FIGS. 2(a)-2(h) are cross-sectional views illustrating the silicon wafer at various stages of the process of FIG. 1;
[0038] FIG. 3 is a view, similar to FIG. 1, showing an formation of a porous silicon wafer useful as a porous membrane in a PEMFC in accordance with a second embodiment of the present disclosure;
[0039] FIG. 4(a)-4(k) are cross-sectional views illustrating the silicon wafer at various stages of the process of FIG. 3;
[0040] FIGS. 5(a)-5(d) are schematic cross-sectional views showing formation of a porous silicon wafer made in accordance with another embodiment of the present disclosure;
[0041] FIG. 6 is a schematic view of a PEMFC in accordance with the present disclosure;
[0042] FIG. 7 is a schematic block diagram with a process for producing electrode material in accordance with one embodiment of the present disclosure;
[0043] FIGS. 8A and 8B are cross-sectional view of electrode material at various stages of production in accordance with the present disclosure;
[0044] FIG. 9 is a schematic block diagram of a process for producing electrode material in accordance with another embodiment of the present disclosure;
[0045] FIG. 10 is a schematic block diagram of a yet another process for producing electrode material in accordance with the present disclosure;
[0046] FIG. 11 is a cross-sectional view of a rechargeable battery made in accordance with the present disclosure;
[0047] FIG. 12 is a schematic block diagram of still yet another process for producing electrode material in accordance with the present disclosure;
[0048] FIG. 13 is a cross-sectional view of a rechargeable battery in accordance with the present disclosure; and
[0049] FIG. 14 is a perspective view of a battery made in accordance with the present disclosure.
DETAILED DESCRIPTION OF THE PRESENT INVENTION
[0050] The terms “top” and “bottom” and “left” and “right” are employed in a relative, and not an absolute sense to facilitate description and to describe relative locations of elements. The terms can be used interchangeably.
[0051] Modes for carrying out the present disclosure will be described in detail below, with reference to the drawings.
First Embodiment
[0052] FIGS. 1 and 2(a)-2(h) are schematic and cross-sectional views showing the steps of manufacturing a porous silicon wafer according to a first embodiment of the present disclosure. In the drawings the cross-sectional dimension of the pores in the horizontal direction of the drawings figures are shown enlarged for clarity.
[0053] Referring to FIGS. 1 and 2(a)-2(h), starting with a silicon wafer 10, as shown in FIG. 2(a), dielectric materials are deposited in step 100 to form a hard mask on front and back sides of the wafer 10. In this case each side of the wafer will first be deposited with 50 nm layer 12a, 12b of SiO.sub.2 followed by 300 nm layers 14a, 14b of SiN.sub.x.
[0054] Next, in step 102, the front side mask 14a is patterned with a photoresist 16 which is spun and patterned on the front side of the wafer, and a polymer material 18 is spun onto the back side of the wafer. Pattern 16 defines the hard mask etch which will in turn be used for a deep anisotropic etch. Alignment elements (not shown) for a subsequent backside etch are also formed at this step 102.
[0055] FIG. 2(c) shows a cross section of the wafer after the etch of the pad hardmask (step 104). Here a dry etch (plasma) is used to control the edges of the hardmask to ensure uniform edge erosion during KOH etch (although other etchants are contemplated as a function of application).
[0056] As shown in FIG. 2(d), the front side of the wafer has been spun with a polymer 20 at step 106 to protect the pattern on the front side while the pad structure on the back side is patterned at 22 in step 108. Alternatively, a back side hardmask could be deposited after the patterning of the front side. The back side pattern 22 is aligned to marks (not shown) formed on the front side of the wafer to ensure they are aligned.
[0057] After the back side pad structures are patterned at step 108, a dry etch (plasma) is used in step 110 to etch the dielectrics while controlling the edge shape. This is shown in FIG. 2(e).
[0058] FIG. 2(e) shows the nitride (PAD) etch of the back side pad structure, which is aligned to the front side pattern. This step is followed by a resist strip and wafer clean step 112 in preparation for wet etch of features.
[0059] FIG. 2(f) shows the configuration of the wafer after the resist strip and before KOH or other anisotropic etch in step 114. We prefer to use a wet etch so that both faces can be etched simultaneously to ensure the same etch depth on both sides. However, a plasma etch could be used to independently etch each face. The open areas 24 as delineated by the etching of the dielectrics are shown on each side of the wafer.
[0060] The next step 116 is to etch the silicon to thin it locally to create regions 26 for defining thinner silicon regions for formation of the porous silicon material in a subsequent step 118 as will be described below. This step preferably is conducted using a simple open bath etch, although a tool etch could be used. FIG. 2(g) shows the wafer after anisotropic wet etch 116.
[0061] The thinned or contoured silicon wafer from step 116, is then subjected to an electrochemical etching by applying uniform electrical field across the wafer while immersing the wafer in an etchant such a Dimethylformamide (DMF)/Dimethylsulfoxide (DMSO)/HF etchant in an electrochemical immersion cell, in an electrochemical etching step 118, to form through holes or pores 28 through the thinned section 26 as shown in FIG. 2(h) (although other etchants are contemplated as a function of application). The growth of well-defined cylindrical micropores or through holes can be controlled by controlling etching conditions, i.e., etching current density, etchant concentration, temperature, silicon doping, etc., following the teachings of Santos et al., Electrochemically Engineered Nanoporous Material, Springer Series in Materials Science 220 (2015), Chapter 1, the contents of which are incorporated herein by reference.
[0062] The resulting pores have a high aspect ratio of length to cross-sectional diameter typically a length to diameter aspect ratio of >50:1 (although other aspect ratios are contemplated as a function of application). The resulting structure, shown in FIG. 2(h) comprises a porous silicon wafer 30 having substantially cylindrical through holes or pores 28 having a length of, e.g., 180 μm and a diameter of 1.6 μm, i.e, an aspect ratio of 112.5:1 which is quite effective for use as a membrane in a PEMFC as will be described below (although other aspect ratios are contemplated as a function of application). The surfaces of the resulting porous silicon wafer 30 may then be coated with a noble metal at a step 120, and the resulting noble metal coated porous wafer 30 may be incorporated as a membrane in a PEMFC as will be described below.
Second Embodiment
[0063] FIGS. 3-4 illustrate a second embodiment of the present disclosure. The process steps 200-216 of FIG. 3, and cross-sectional views of FIGS. 4(a)-4(g) are identical to process steps 100-116 of FIG. 1 and cross-sectional views 2(a)-2(g) above described.
[0064] However, referring to FIG. 4(h) upon completion of contouring etch step 216, we put a thin metal layer 40 on the back side of the contoured wafer e.g., by sputtering in a step 218 followed by a photolithographing resist step 220 on the front side of the contouring wafer. Metal layer 40 on the backside of the wafer promotes improved electrical contact to the wafer, while the resist 42 applied in the photolithography step 220 limits porous silicon formation to the thinned region 26 of silicon in the following etching step described below.
[0065] As shown in FIG. 4(i), an electro chemical etching (step 222) is used to form porous silicon 44 within the areas unprotected by the resist 42.
[0066] After porous silicon formation, step 222, the front side is protected by spinning a photoresist 46 on it in step 224 (see FIG. 4(j)) and a wet etch (step 226) is used to remove the thin metal 40 from the back side. The front side resist 46 is then striped in a resist stripping step 228. FIG. 4(k) shows the configuration after metal etch and photoresist strip. The pores may then be coated with a noble metal at step 230. Optionally, an additive process such as atomic layer deposition may be used to coat the surfaces of the pores or the pore diameters with a noble metal, before the stripping step 228. The resulting porous silicon wafer may then be incorporated as a membrane in a PEMFC as will be described below.
Third Embodiment
[0067] FIGS. 5-6 illustrate a third embodiment of the present disclosure. The process starts with a silicon wafer 400 covered on one side with a resist layer 402, and covered on the opposite side by a sacrificial metal layer 404 formed of, for example, a noble metal such as platinum (see step FIG. 5(a)) (although other metals are contemplated as a function of application). The resist layer 402 is patterned at step 502, and etched at step 504 to expose a selected surface 406 one side of the wafer 400 (FIG. 5(b)). The resist covered and patterned wafer is then subjected to electrochemical etching by applying an uniform electrical field across the metal layer 404 and substrate wafer 400 as the wafer is immersed in an electrochemical cell containing an etchant such as HF and H.sub.2O.sub.2, in step 506, whereby to produce substantially uniform pores 408 through the exposed portion of the substrate 400 to the metal layer 404 (FIG. 5(c)) (although other etchants are contemplated as a function of application). As before, the growth of well-defined cylindrical micropores with two holes can be controlled by controlling etching conditions, i.e., etching current density, etching concentration, temperature, silicon doping, etc., again following the teachings of Santos et al. Alternatively, micropore or through hole formation can be controlled by covering selected portions of the silicon wafer with a nanoporous anodic alumina mask (although other masks are contemplated as a function of application). Self-ordered nanoporous anodic alumina is basically a nanoporous matrix based on alumina that features closed-packed arrays of hexagonally arranged cells, at the center of which a cylindrical nanopore grows perpendicularly to the underlying aluminum substrate. Nanoporous anodic alumina may be produced by electrochemical anodization of aluminum, again following the teachings of Santos et al. the teachings of which are incorporated herein by reference. The resist layers 402 and sacrificial metal layer 404 can then be removed in a step 508 leaving a porous silicon wafer having a section 405 having substantially cylindrical through holes or pores 408 (FIG. 5) which may then be coated with a noble metal catalyst coating, and the resulting porous silicon substrate may be incorporated as a membrane in a PEMFC as will be described below.
[0068] The noble metal catalyst may be platinum black, platinum-on-carbon, and/or other composite noble metal material, e.g., silver, gold, rhodium, iridium, palladium, ruthenium and osmium (although other metal catalysts are contemplated as a function of application).
[0069] Referring now to FIG. 6, a PEMFC is assembled as follows:
[0070] The porous silicon membrane formed as above may be incorporated into a PEMFC module 700 which is schematically illustrated in FIG. 6. The PEMFC module 700 includes a porous silicon membrane 702 as formed above, sandwiched between an anode or negative electrode 704, and a cathode or a positive electrode 706. The anode/membrane/cathode sandwich is in turn sandwiched between hydrogen gas flow channel or plate assembly 708 on the anode side, and an oxidant (oxygen or air) of flow channel or plate assembly 710 on the cathode side. The assembly is held together in a case (not shown) which includes fittings for flowing the oxygen hydrogen gas and oxidate, a sump and drain (not shown) for draining water which is formed by reaction of the hydrogen gas an oxidate, and an electric circuit 712 including electrodes 714, 716 which are coupled across payload/source 718.
[0071] In operation, gaseous hydrogen fuel is channeled through hydrogen gas flow assembly 708 to the anode side of the fuel cell, while oxygen gas (oxygen or air) is channeled through the oxidant gas flow assembly 710 to the cathode side of the cell. At the anode 704, the platinum catalyst causes the hydrogen to split into positive hydrogen ions (protons) and negatively charged electrons. The porous silicon membrane 702 allows only the positively charged ions to pass through it to the cathode. The negatively charged electrons travel along the external circuit 712 to the cathode 706 creating an electrical current. At the cathode 706, the electrons and positively charged hydrogen ions combine with oxygen to form water, which then collects in a bottom of a cell and is removed.
[0072] Various changes may be made in the above disclosure. For example, as mentioned above, the noble metal catalysts may be coated directly on the pores of the porous silicon substrate membrane, or the porous silicon substrate membrane may be sandwiched between porous paper or carbon or graphite sheets impregnated with a noble metal. Also, other hydrogen fuel sources may be employed such as methanol and chemical hydrides.
[0073] Referring now to FIGS. 7-14, an improved lithium ion rechargeable battery is formed according to the present disclosure as follows.
[0074] Referring in particular to FIG. 7, starting with a thin monocrystalline silicon wafer 10, typically 50-200 mil thick, the wafer 1010 is subjected to an electrochemical etching by applying uniform electrical field across the wafer while immersing the wafer in an etchant such a Dimethylformamide (DMF)/Dimethylsulfoxide (DMSO)/HF etchant (although other etchants are contemplated as a function of application), in an electrochemical immersion cell, in an electrochemical etching step 1012, to form micron sized through holes or pores 1016 through the wafer as shown in FIG. 8A. The growth of well-defined cylindrical micropores or through holes can be controlled by controlling etching conditions, i.e., etching current density, etchant concentration, temperature, silicon doping, etc., following the teachings of Santos et al., Electrochemically Engineered Nanoporous Material, Springer Series in Materials Science 220 (2015), Chapter 1, the contents of which are incorporated herein by reference.
[0075] The resulting pores have a high aspect ratio of length to cross-sectional diameter typically a length to diameter aspect ratio of >50:1. The resulting structure, shown in FIG. 8A comprises a porous silicon wafer 1018 having substantially cylindrical through holes or pores 1016 having a length of, e.g., 180 μm and a diameter of 1.6 i.e, an aspect ratio of 112.5:1 which is quite effective for use as electrode in a lithium ion battery as will be described below (although other aspect ratios are contemplated as a function of application). The walls of the resulting porous silicon wafer 1018 are then coated with a metal such as titanium, tungsten or cobalt in step 1020 (although other metals are contemplated as a function of application), and the metal coated porous silicon wafer is then subjected to a heat treatment in a heating step 1022 to convert the deposited metal to the corresponding metal silicide 1025 at heat treatment step 1022. There results a porous silicon substrate material 1024 in which the wall surfaces of the pores of the material are coated with a thin layer of a metal silicide material 1026 (FIG. 8A).
[0076] FIG. 9 illustrates an alternative embodiment of the present disclosure. The process starts with a silicon wafer 1030 to which is applied a thin metal layer 1032 on the back side of the wafer 1030 e.g., by sputtering in a step 1034. Metal layer 1032 on the backside of the wafer promotes improved electrical contact to the wafer. An electro chemical etching (step 1036) is used to form pores 1037 through the silicon wafer 1030. After porous silicon formation, a wet etch (step 1038) is used to remove the thin metal 1032 from the back side. The porous silicon wafer which is similar to the porous silicon substrate shown in FIG. 8A is then coated with metal in step 1040 and the metal converted to the silicide in a heating step 1042 similar to the first embodiment. There results a porous silicon substrate in which the surface of the wall surfaces of the pores are coated with a metal silicide similar to the porous silicon substrate shown in FIG. 8B.
[0077] FIG. 10 illustrates a third embodiment of the present disclosure. The process starts with a silicon wafer 1050 covered on one side in step 1052 with a sacrificial metal layer 1054 formed of, for example, a noble metal such as platinum (although other metals are contemplated as a function of application). The silicon wafer 1050 is then subjected to electrochemical etching by applying an uniform electrical field across the metal layer 1054 and substrate wafer 1050 as the wafer is immersed in an electrochemical cell containing an etchant such as HF and H.sub.2O.sub.2 (although other etchants are contemplated as a function of application), in step 1056, whereby to produce substantially uniform pores 1058 through the exposed portion of the silicon wafer substrate 1050 to the metal layer 1054. As before, the growth of well-defined cylindrical micropores or through holes can be controlled by controlling etching conditions, i.e., etching current density, etching concentration, temperature, silicon doping, etc., again following the teachings of Santos et al. Alternatively, micropore or through hole formation can be controlled by covering selected portions of the silicon wafer with a nanoporous anodic alumina mask (although other masks are contemplated as a function of application). Self-ordered nano porous anodic alumina is basically a nanoporous matrix based on alumina that features closed-packed arrays of hexagonally arranged cells, at the center of which a cylindrical nanopore grows perpendicularly to the underlying aluminum substrate. Nanoporous anodic alumina may be produced by electrochemical anodization of aluminum, again following the teachings of Santos et al. the teachings of which are incorporated herein by reference. The sacrificial metal layer 1054 can then be removed in a step 1058 leaving a porous silicon wafer having substantially cylindrical through holes or pores having a length to diameter aspect ratio of >50:1, i.e., similar to the porous silicon substrate shown in FIG. 8A. The porous silicon substrate is then coated with metal in step 1058, and heated to convert the metal to the metal silicide in step 1060, whereby a porous silicon substrate in which the wall surfaces of the pores are coated with metal silicide similar to FIG. 8B is produced.
[0078] Porous silicon wafers as produced above are assembled into a lithium ion battery as will be described below.
[0079] FIG. 11 shows a lithium ion battery 1060 in accordance with the present disclosure. Battery 1060 includes a case 1062, an anode 1064 formed of a metal silicide coated porous silicon substrate formed as above described, and a cathode 66 formed, for example, of graphite, separated by a membrane or separator 1068. Anode 1064 and cathode 1066 are connected respectively, to external tabs 1070, 1072, respectively. A lithium containing electrolyte 1074, for example, lithium cobalt oxide is contained within the battery 1060 (although other electrolytes are contemplated as a function of application).
[0080] Both the anode and cathode allow lithium ions to move in and out of their structures by a process called insertion (intercalation) or extraction (deintercalation), respectively. During discharge, the positive lithium ions move from the negative electrode (anode) to the positive electrode (cathode) forming a lithium compound through the electrolyte while the electrodes flow through the external circuit in the same direction. When the cell is charging, the reverse occurs, with the lithium ions and the electrodes moving back into the negative electrode with a net higher energy stake.
[0081] A feature an advantage of the present disclosure is that the anode may be made physically larger, i.e., thicker than the cathode. The increased thickness porous structure of the anode allows protons more time to move into the electrode matrix. Also, less lithium electrolyte is required for similar energy storage. And, since the protons move more slowly into the anode, this permits a faster charge and discharge rate without a danger of fractures or pulverization of the electrode.
[0082] Changes may be made in the above disclosure without departing from the spirit and scope thereof. For example, while the anode production has been described as being formed from monocrystalline silicon wafers, monocrystalline silicon ribbon advantageously may be employed for forming the anode. Referring to FIG. 12, employing silicon ribbon 1080 permits a continuous process in which ribbon is run through an electrochemical etching bath 1082 to form pores through the ribbon, and then from there through a metal coating station 1084 and from there a heat treating station 1086 to form metal silicide on the surfaces of the walls of the pores. The resultant porous silicon metal silicide coated ribbon may then be used to form a lithium ion battery using standard roll manufacturing techniques. For example, referring to FIG. 13, the silicide coated porous silicon ribbon anode electrode 1084 may be assembled in a stack with cathode electrode 86 between separator sheets 1088. The electrodes 1084, 1086 and separator sheets 88 are wound together in a jelly roll and then inserted in a case 1090 with a positive tab 1092 and negative tab 1094 extending from the jelly roll. The tabs may then be welded to an exposed portion of the electrodes 1084, 1086, the case 1090 filled with electrolyte, and the case 1090 sealed. There results a high capacity lithium ion rechargeable battery in which the anode material comprises porous metal silicide coated porous silicon ribbon capable of repeated charges and discharges without adverse effects.
[0083] Still other changes are possible. For example, rather than using monocrystalline silicon chips or monocrystalline silicon ribbon, the silicon may be polysilicon silicon or amorphous silicon. Also, while tungsten cobalt and titanium have been described as the preferred metals for forming the metal silicides, other conventionally used in forming advantageously may be employed including silver (Ag), aluminum (Al), gold (Au), palladium (Pd), platinum (Pt), Zn, Cd, Hg, B, Ga, In, Th, C, Si, Ge, Sn, Pb, As, Sb, Bi, Se and Te. Also, while LiPF.sub.6 and LiBf.sub.4 have been described as useful electrolytes, other electrolytes conventionally used with lithium ion batteries including but not limited to lithium cobalt oxide (LiCoO.sub.2). It should be appreciated that other metals and/or electrolytes are contemplated as a function of application.
