Programmable two-dimensional simultaneous multi-beam optically operated phased array receiver chip and multi-beam control method

Abstract

A programmable two-dimensional simultaneous multi-beam optically operated phased array receiver chip is manufactured based on silicon-on-insulator (SOI) and indium phosphide (InP) semiconductor manufacturing processes, including the SiN process. The InP-based semiconductor is used for preparing a laser array chip and a semiconductor optical amplifier array chip, the SiN is used for preparing an optical power divider, and the SOI semiconductor is used for preparing a silicon optical modulator, a germanium-silicon detector, an optical wavelength multiplexer, a true delay line, and other passive optical devices. The whole integration of the receiver chip is realized through heterogeneous integration of the InP-based chip and the SOI-based chip. Simultaneous multi-beam scanning can be realized through peripheral circuit programming control. The chip not only can realize two-dimensional multi-beam scanning, but also has strong expansibility, such that the chip can be used for ultra-wideband high-capacity wireless communication and simultaneous multi-target radar recognition systems.

Claims

1. A programmable two-dimensional simultaneous multi-beam light-operated phased array receiver chip, comprising an indium phosphide (InP) photonic chip and a silicon-on-insulator (SOI) photonic chip that are heterogeneously integrated; wherein the InP photonic chip integrates q distributed feedback (DFB) lasers and q semiconductor optical amplifiers (SOAs), wavelengths of optical signals output by the q DFB lasers are λ.sub.1, λ.sub.2, . . . , λ.sub.q-1 and λ.sub.q, optical output ports of the q DFB lasers are respectively connected to input ports of the q SOAs, the optical signals output by the DFB lasers on the InP photonic chip are amplified by the corresponding SOAs and are input to input ports of corresponding silicon nitride optical power splitters (SiN-OPSs) on the SOI photonic chip; the SOI photonic chip integrates q SiN-OPSs, denoted as SiN-OPS.sub.q, each having 1 stages of 1×2 SiN-based multimode interferometers (SiN-MMIs), each SiN-OPS has 2.sup.l output ports, the output port of SiN-OPSq is denoted as SiN-OPS.sub.q-O.sub.k, 1≤k≤2.sup.l, and k is an integer; each SiN-OPS.sub.q-O.sub.k is cascaded with a corresponding silicon modulator; the SOI photonic chip further integrates 2.sup.l 1×q SiN-based optical wavelength multiplexers (SiN-WDMs), denoted as SiN-WDM.sub.k; each SiN-WDM has q optical input ports connected to the corresponding silicon modulator, and each SiN-WDM has one optical output port for synthesizing q optical signals with different wavelengths into one optical signal for transmission; the optical output port of each SiN-WDM is cascaded with two different SiN-based optical true time delay lines (SiN-OTTDLs) SiN-OTTDL1 and SiN-OTTDL2; the SiN-OTTDL1 comprises m+1 stages of 2×2 silicon nitride optical switches (SiN-OSs) and m stages of delay lines-reference waveguides that are cascaded, both the reference waveguide and the delay line are SiN single-mode waveguides, and delay is realized only by changing a length difference between the reference waveguide and the delay line; and the SiN-OTTDL2 comprises n+1 stages of 2×2 SiN-OSs and n stages of delay lines-reference waveguides that are cascaded, and the delay line is a dispersor; the 2×2 SiN-OS comprises two 2×2 SiN-MMIs and two SiN thermo-optic phase shifters that are cascaded, and voltages applied to the thermo-optic phase shifters on the 2×2 SiN-OS are regulated to switch the optical signal between the two ports to achieve delay regulation; and an output port of the SiN-OTTDL2 is cascaded with germanium silicon photodetectors (GeSi-PD), and electrical signals demodulated through 2.sup.l GeSi-PDs are output to a peripheral electrical synthesizer for synthesis.

2. The programmable two-dimensional simultaneous multi-beam light-operated phased array receiver chip according to claim 1, wherein each DFB laser has a different wavelength.

3. The programmable two-dimensional simultaneous multi-beam light-operated phased array receiver chip according to claim 1, wherein the SiN-WDM is a SiN micro-ring resonant cavity, a lattice filter, or an arrayed waveguide grating (AWG).

4. The programmable two-dimensional simultaneous multi-beam light-operated phased array receiver chip according to claim 1, wherein the SiN-OTTDL1 and the SiN-OTTDL2 are both switch array switching delay lines, and optical switches of the SiN-OTTDL1 and the SiN-OTTDL2 are both 2×2 SiN-OSs based on the Mach Zendel structure and the thermo-optic effect; and the SiN-OTTDL1 is a SiN-OTTDL based on a non-dispersive single-mode waveguide and the SiN-OTTDL2 is a SiN-based chirped Bragg grating (SiN-CBG).

5. The programmable two-dimensional simultaneous multi-beam light-operated phased array receiver chip according to claim 1, wherein the SiN-OTTDL1 comprises m+1 2×2 SiN-OSs and m pairs of delay lines-reference waveguides, one delay line and one reference waveguide are connected to upper and lower arms between every two 2×2 SiN-OSs, the delay line and the reference waveguide are both SiN single-mode waveguides, and the delay line has a total of 2.sup.m delay states; and the SiN-OTTDL2 comprises n+1 2×2 SiN-OSs and n pairs of delay lines-reference waveguides, one delay line and one reference waveguide are connected to upper and lower arms between every two 2×2 SiN-OSs, the delay line and the reference waveguide are a SiN-CBG and a SiN single-mode waveguide, and the delay line has a total of 2.sup.n delay states.

6. The programmable two-dimensional simultaneous multi-beam light-operated phased array receiver chip according to claim 5, wherein a SiN directional coupler (SiN-DC), a Si-SiN interlayer transition structure and a GeSi-PD that are cascaded are integrated with the upper and lower arms of each 2×2 SiN-OS, the SiN-DC couples a portion of optical power from the SiN waveguide and inputs to the GeSi-PD through the Si-SiN interlayer transition structure, and the magnitude of a photoelectric current output by the GeSi-PD is observed to monitor an operating state of the SiN-OS.

7. The programmable two-dimensional simultaneous multi-beam light-operated phased array receiver chip according to claim 1, wherein the optical signals output by the DFB lasers on the InP photonic chip are amplified by the corresponding SOAs and are input to the input ports of the corresponding SiN-OPSs on the SOI photonic chip through photonic wire bonding, end-coupling, or flip chip bonding.

8. The programmable two-dimensional simultaneous multi-beam light-operated phased array receiver chip according to claim 1, wherein the silicon modulator is a Si-based carrier-depletion ring modulator (Si-MRM), the Si-MRM comprises a SiN waveguide and a Si waveguide-based resonant cavity; the SiN waveguide is used as a BUS waveguide and an optical input and output waveguide of the Si-MRM, the SiN waveguide is coupled with the Si waveguide-based resonant cavity through a Si-SiN waveguide coupling region; a PN junction phase shifter is integrated in the Si waveguide-based resonant cavity, and a radio frequency (RF) signal received by a corresponding antenna array element drives the PN junction phase shifter to modulate an optical carrier input to the Si-MRM, the Si-MRM further integrates a thermo-optic phase shifter, and a voltage is applied to the thermo-optic phase shifter for heating a silicon waveguide, to regulate a resonant wavelength of the Si-MRM to achieve regulation of operating points of the Si-MRM; the Si-SiN waveguide coupling region is a double-layer structure, and an overlapping region or the size of the structure is changed to change a coupling coefficient to regulate a quality factor and operating performance of the Si-MRM.

9. A multi-beam control method for the chip according to claim 1, comprising: 1) applying drive currents to all of the DFB lasers and SOAs on the InP photonic chip to enable the DFB lasers to generate optical signals with the wavelengths of λ.sub.1, λ.sub.2, . . . , λ.sub.q-1, and λ.sub.q, wherein the optical signals are amplified by the corresponding SOAs and are coupled into the SiN-OPSs on the SOI photonic chip; 2) cascading each of k output ports of each SiN-OPS with one Si-MRM, connecting an RF input port of each Si-MRM to an RF output port of an element in a phased array antenna, and modulating a received RF signal to a corresponding optical carrier via the Si-MRM, wherein a k.sup.th output port of SiN-OPS.sub.q is cascaded with Si-MRM.sub.kq and a wavelength of a corresponding optical carrier is λ.sub.q, and the two-dimensional simultaneous multi-beam light-operated phased array receiver chip corresponds to the phased array antenna with k×q elements; 3) inputting to SiN-WDM.sub.k modulated optical signals output by Si-MRM.sub.k1 to Si-MRM.sub.kq, and delaying a synthesized signal through SiN-OTTDL1.sub.k and SiN-OTTDL2.sub.k, wherein SiN-OTTDL1.sub.k comprises m+1 stages of 2×2 SiN-OSs and m stages of delay lines-reference waveguides that are cascaded, a delay on each stage is determined by a relative delay between the delay line and the reference waveguide, a relative delay on the first stage is 2.sup.0Δt, a relative delay on the second stage is 2.sup.1Δt, a relative delay on an m.sup.th stage is 2.sup.m-1Δt, the reference waveguide and the delay line are both SiN single-mode waveguides, delay is achieved only by changing a length difference of the SiN single-mode waveguides, and the delay is considered as dispersion-free delay, that is, the optical signals with the wavelengths of λ.sub.1, λ.sub.2, . . . ,λ.sub.q-1, and λ.sub.q have the same delay in the delay line; and SiN-OTTDL2.sub.k comprises n+1 stages of 2×2 SiN-OSs and n stages of delay lines-reference waveguides that are cascaded, a delay on each stage is determined by a relative delay between the delay line and the reference waveguide, the delay line is a dispersor, the relative delay on each stage is regulated by changing the length of the dispersive delay line to regulate a relative delay difference among the optical signals with the wavelengths of λ.sub.1 to λ.sub.q, wherein a relative delay difference between the optical signals with the wavelengths of λ.sub.1 to λ.sub.q on the first stage is Δt, a relative delay difference between the optical signals with the wavelengths of λ.sub.1 to λ.sub.q on the second stage is 2.sup.lΔt, and a relative delay difference between the optical signals with the wavelengths of λ.sub.1 to λ.sub.q on an nth stage is 2.sup.n-1Δt; 4) regulating voltages applied to the thermo-optic phase shifters of the SiN-OS on the SOI photonic chip, to achieve two-dimensional beam scanning of the corresponding phased array antenna; and grouping links of SiN-OTTDL1.sub.1 to SiN-OTTDL1.sub.k into multiple combinations, to achieve multi-beam scanning control; and 5) after delaying the optical signals through the two stages of delay lines, demodulating the optical signals into electrical signals through the corresponding GeSi-PDs, and synthesizing the electrical signals through an electrical synthesizer and sending to an external signal processing unit, to complete signal analysis and detection.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is an overall schematic diagram of a two-dimensional simultaneous multi-beam optically operated phased array receiver chip according to the present disclosure;

(2) FIG. 2 is a schematic structural diagram of a Si-MRM on an SOI photonic chip;

(3) FIG. 3 is a schematic structural diagram of a SiN-OTTDL1 on an SOI photonic chip;

(4) FIG. 4 is a schematic structural diagram of a SiN-OTTDL2 on an SOI photonic chip;

(5) FIG. 5 is a schematic structural diagram of a SiN-OS on an SOI photonic chip; and

(6) FIG. 6 is a schematic diagram of a Si-SiN transition structure on an SOI photonic chip.

DETAILED DESCRIPTION OF THE EMBODIMENTS

(7) The present disclosure is described in further detail below with reference to specific implementations. All the implementations of the present disclosure can be correspondingly combined on the premise that their technical features are not conflicted.

(8) As shown in FIG. 1, a two-dimensional simultaneous multi-beam optically operated phased array receiver chip includes an InP photonic chip and an SOI photonic chip.

(9) The present disclosure adopts the following technical solutions for the InP photonic chip.

(10) An InP-based photonic chip is designed and manufactured, with q DFB lasers and q SOAs integrated on it, denoted as DFB.sub.1, DFB.sub.2, . . . , DFB.sub.q-1, and DFB.sub.q and SOA.sub.1, SOA.sub.2, SOA.sub.q-1, and SOA.sub.q.

(11) Wavelengths of optical signals output by DFB.sub.1, DFB.sub.2, DFB.sub.q-1, and DFB.sub.q are λ.sub.1, λ.sub.2, . . . , λ.sub.q-1, and λ.sub.q respectively.

(12) Optical output ports of DFB.sub.1, DFB.sub.2, DFB.sub.q-1, and DFB.sub.q are connected to input ports of SOA.sub.1, SOA.sub.2, . . . , SOA.sub.q-1, and SOA.sub.q respectively, that is, an optical signal output by each DFB is amplified and output by a corresponding SOA.

(13) The output port of each SOA is integrated with an InP edge coupler (InP-GC), denoted as InP-GC.sub.1, InP-GC.sub.2, . . . , InP-GC.sub.q-1, and InP-GC.sub.q, and each InP-GC is used for edge-coupling with the SOI photonic chip.

(14) The present disclosure adopts the following technical solutions for the SOI photonic chip:

(15) The SOI photonic chip is integrated with q silicon nitride edge couplers (SiN-ECs), denoted as SiN-EC.sub.1, SiN-EC.sub.2, SiN-EC.sub.q-1, and SiN-EC.sub.q.

(16) A back end of each SiN-EC is cascaded with one SiN-OPS with one stage of 1×2 SiN-MMI, denoted as SiN-OPS.sub.q. Each SiN-OPS has 2.sup.l output ports, and an output port of SiN-OPS.sub.q is denoted as SiN-OPS.sub.q-O.sub.k (1≤k≤2.sup.l, and k is an integer).

(17) Each SiN-OPS.sub.q-O.sub.k is cascaded with a corresponding silicon modulator, which may be a depletion Mach-Zehnder modulator and micro-ring modulator based on carrier dispersion effects, or a germanium-silicon electroabsorption modulator. To achieve high integration density of the chip, a Si-MRM is preferably used, denoted as Si-MRM.sub.kq (q and l are positive integers, 1≤k≤2.sup.l).

(18) The SOI photonic chip integrates 2.sup.l 1×q SiN-WDM, denoted as SiN-WDMk (1≤k≤2.sup.l). Each SiN-WDM has q optical input ports, denoted as SiN-WDM.sub.kq, and one optical output port, that is, q optical signals with different wavelengths (λ.sub.1, λ.sub.2, . . . , λ.sub.q-1, and λ.sub.q) are synthesized into one optical signal for transmission.

(19) Two different SiN-OTTDLs SiN-OTTDL1 and SiN-OTTDL2 are consecutively cascaded after the optical output port of each SiN-WDM, denoted as SiN-OTTDL1.sub.k and SiN-OTTDL2.sub.k (1≤k≤2.sup.l).

(20) The SiN-OTTDL1.sub.k includes m+1 (m is a positive integer) 2×2 SiN-OSs and m pairs of delay lines-reference waveguides, one delay line and one reference waveguide are connected to upper and lower arms between every two 2×2 SiN-OSs, the delay line and the reference waveguide are both SiN single-mode waveguides, and the delay line has a total of 2.sup.m delay states.

(21) the SiN-OTTDL2.sub.k includes n+1 (n is a positive integer) 2×2 SiN-OSs and n pairs of delay lines-reference waveguides, one delay line and one reference waveguide are connected to upper and lower arms between every two 2×2 SiN-OSs, the delay line and the reference waveguide are a SiN-CBG and a SiN single-mode waveguide, and the delay line has a total of 2.sup.n delay states.

(22) The 2×2 SiN-OS is of the Mach-Zehnder interferometer structure, including two 2×2 SiN-MMIs and two thermo-optic phase shift arms, and a peripheral control circuit applies a voltage to the thermo-optic phase shift arms to regulate the operating state of 2×2 SiN-OS. In order to monitor the optical switching state in OTTDL, a SiN-DC, a Si-SiN interlayer coupler and a GeSi-PD that are cascaded in sequence are integrated with the upper and lower arms of each 2×2 SiN-OS. The SiN-DC couples a portion (1%-5%) of optical power from the SiN waveguide and inputs to the GeSi-PD through the Si-SiN interlayer coupler, and the magnitude of a photoelectric current output by the GeSi-PD is observed to monitor an operating state of the SiN-OS.

(23) After two stages of delaying through the SiN-OTTDL1.sub.k and the SiN-OTTDL2.sub.k, the optical signal is demodulated into an electrical signal through a GeSi-PD cascaded with an output port of the SiN-OTTDL2.sub.k, where the GeSi-PD is denoted as GeSi-PDk (1≤k≤2.sup.l).

(24) Electrical signals demodulated through k GeSi-PDs are synthesized into one electrical signal and sent to a peripheral signal processing circuit for signal analysis.

(25) A peripheral control circuit regulates SiN-OS in the corresponding SiN-OTTDL1 and SiN-OTTDL2 on the chip, to perform programmable two-dimensional simultaneous multi-beam scanning control.

(26) The size of the corresponding phased array of this chip is q×k, and up to k 1×q beams can be simultaneously regulated.

(27) In this embodiment, a three-dimensional schematic diagram of an interlayer coupling structure (SiN-Si interlayer coupler) required for coupling optical signals between SiN-WG and Si-WG is shown in FIG. 6. The SiN-Si interlayer coupler is used to couple the optical signal from the SiN-based optical waveguide into a Si-based optical waveguide or from a Si-based optical waveguide into a SiN-based optical waveguide.

(28) The following describes the multi-beam control process of the present disclosure:

(29) Drive currents are applied to all the DFB lasers (DFB.sub.1, DFB.sub.2, . . . , DFB.sub.q-1, and DFB.sub.q) and SOAs (SOA.sub.1, SOA.sub.2, . . . , SOA.sub.q-1, and SOA.sub.q) on the InP photonic chip, to enable the lasers to generate optical signals with the wavelengths of λ.sub.1, λ.sub.2, λ.sub.q-1, and λ.sub.q, the optical signals are amplified by the corresponding SOAs and coupled into the SiN-OPS.sub.1, SiN-OPS.sub.2, . . . , SiN-OPS.sub.q-1, and SiN-OPS.sub.q on the SOI photonic chip through InP-GC and SiN-GC on the SOI photonic chip.

(30) As shown in FIG. 1, each of k output ports of each SiN-OPS is cascaded with one Si-MRM, an RF input port of each Si-MRM is connected to an RF output port of an element in a phased array antenna, and a received RF signal is modulated to a corresponding optical carrier via the Si-MRM, where a k.sup.th output port of SiN-OPS.sub.q is cascaded with Si-MRMk.sub.kq and a wavelength of a corresponding optical carrier is λ.sub.q. Therefore, the two-dimensional simultaneous multi-beam optically operated phased array receiver chip corresponds to the phased array antenna with k×q elements.

(31) As shown in FIG. 2, the Si-MRM uses a SiN waveguide as a BUS waveguide and as an input and output port of the Si-MRM A section of PN junction phase shifter is integrated in the Si waveguide-based resonator, and the RF signal received by each antenna array element drives the phase shifter, to modulate a corresponding optical carrier. In addition, the Si-MRM further integrates a thermo-optic phase shifter, and a voltage is applied to the thermo-optic phase shifter for heating a silicon waveguide, to regulate a resonant wavelength of the Si-MRM to achieve regulation of operating points of the Si-MRM The Si-SiN waveguide coupling region is a double-layer structure, and an overlapping region or the size of the structure is changed to change a coupling coefficient to regulate a quality factor and operating performance of the Si-MRM, for example, modulating the depth and the bandwidth. The operating performance of the Si-MRM is regulated according to the external system performance requirements.

(32) As shown in FIG. 1, modulated optical signals output by Si-MRM.sub.k1 to Si-MRM.sub.kq are input to SiN-WDM.sub.k, and a synthesized signal is delayed through SiN-OTTDL1.sub.k and SiN-OTTDL2.sub.k sequentially.

(33) As shown in FIG. 3, SiN-OTTDL1.sub.k includes m+1 stages of 2×2 SiN-OSs and m stages of delay lines-reference waveguides that are cascaded. A delay on each stage is determined by a relative delay between the delay line and the reference waveguide, a relative delay on the first stage is 2.sup.0Δt, a relative delay on the second stage is 2.sup.1Δt, and a relative delay on an m.sup.th stage is 2.sup.m-1Δt. Herein, both the reference waveguide and the delay line are SiN single-mode waveguides, delay is achieved only by changing a length difference of the SiN single-mode waveguides, and the delay is considered as dispersion-free delay, that is, the optical signals with the wavelengths of λ.sub.1, λ.sub.2, . . . , λ.sub.q-1, and λ.sub.q have the same delay in the delay line.

(34) As shown in FIG. 4, SiN-OTTDL2.sub.k includes n+1 stages of 2×2 SiN-OSs and n stages of delay lines-reference waveguides that are cascaded. A delay on each stage is determined by a relative delay between the delay line and the reference waveguide, and the delay line herein is a dispersor (that is, a dispersive line). Two optical signals with a wavelength difference of AA produce a relative delay difference of Δt=Δλ×D(λ)×L in a dispersive delay line with the length L and the dispersion coefficient D(λ). Here, At in SiN-OTTDL2.sub.k is defined as λt=(λ.sub.q-λ.sub.1)×D(λ)×L, and the unit length of the dispersive delay line is defined as L=1 mm. Herein, the relative delay on each stage is regulated by changing the length of the dispersive delay line to regulate a relative delay difference among the optical signals with the wavelengths of λ.sub.1 to λ.sub.q, A relative delay difference between the optical signals with the wavelengths of λ.sub.1 to λ.sub.q on the first stage is Δt, a relative delay difference between the optical signals with the wavelengths of λ.sub.1 to λ.sub.q on the second stage is 2.sup.lΔt, and a relative delay difference between the optical signals with the wavelengths of λ.sub.1 to λ.sub.q on an n.sup.th stage is 2.sup.n-1Δt.

(35) As shown in FIG. 5, the 2×2 SiN-OS includes two 2×2 SiN-MMIs and two SiN thermo-optic phase shifters that are cascaded. A SiN-DC is integrated with both two output ports of each 2×2 SiN-OS, and the SiN-DC couples a portion (1%-5%) of optical power of the corresponding output port to the GeSi-PD though the SiN-Si transition structure. The voltages applied to the thermo-optic phase shifters on the SiN-OS can be regulated to switch the optical signal between the two ports to achieve delay regulation. In addition, the operating state of the corresponding SiN-OS can be monitored based on the magnitude of the photoelectric current of the corresponding GeSi-PD. When the optical signal is output from the output port of the upper arm of the SiN-OS, that is, when the delay line is taken, the photoelectric current of the GeSi-PD corresponding to the upper arm reaches the maximum, while the photoelectric current of the GeSi-PD corresponding to the lower arm reaches the minimum.

(36) Voltages applied to the thermo-optic phase shifters of the SiN-OS on the SOI photonic chip are regulated, to achieve two-dimensional beam scanning of the corresponding phased array antenna.

(37) The Cartesian coordinate system is used as the standard coordinate system, and a upward direction perpendicular to the antenna array is the Z coordinate. Regulating the operating state of the SiN-OS in SiN-OTTDL1 can regulate the beam scanning in the X-O-Z direction, and regulating the operating state of the SiN-OS in SiN-OTTDL2 can regulate the beam scanning in the Y-O-Z direction.

(38) Links of SiN-OTTDL1.sub.1 to SiN-OTTDL1.sub.k are grouped into multiple combinations, to achieve multi-beam scanning control. For example, links of SiN-OTTDL1.sub.1 to SiN-OTTDL1.sub.k/2 are considered as a whole and links of SiN-OTTDL1.sub.k/2+1 to SiN-OTTDL1.sub.k are considered as a whole, two-dimensional simultaneous two-beam scanning can be realized by regulating the optical switching states of SiN-OSs on the SOI photonic chip.

(39) After delaying the optical signals through the two stages of delay lines, the optical signals are demodulated into electrical signals through the corresponding GeSi-PDs, and the electrical signals are synthesized through an electrical synthesizer and sending to an external signal processing unit, to complete signal analysis and detection.

(40) The above embodiments merely represent several implementations of the present disclosure, and the descriptions thereof are specific and detailed, but they should not be construed as limiting the patent scope of the present disclosure. It should be noted that those of ordinary skill in the art can further make several variations and improvements without departing from the concept of the present disclosure, and all of these fall within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the appended claims.