SUCCESSIVE APPROXIMATION AD CONVERTER

Abstract

A successive approximation (SA) AD converter includes a SA control circuit generating a digital output signal based on an output from a comparator; a first capacitor coupled to an input of the comparator, receiving an analog input signal, and capable of storing electric charges; a second and a third capacitor groups coupling to a reference voltage and storing electric charges previously. The SA control circuit operates for each SA step that the second or the third capacitor group is coupled to a non-inverting input of the comparator and the other is coupled to an inverting input of the comparator based on the output from the comparator. The SA control circuit operates that capacitor terminals of the second and the third capacitor groups coupled to the input of the comparator have the same potential when the reference voltage is stored previously in the second and the third capacitor groups.

Claims

1. A successive approximation AD converter, comprising: a comparator; a successive approximation control circuit that generates a digital output signal based on a determination output result from the comparator; a first capacitor that is coupled to an input terminal of the comparator, is configured to be able to couple to an analog input signal, and is able to store electric charges in advance; and a second capacitor group and a third capacitor group that are configured to be able to couple to a reference voltage and are able to store electric charges in advance, wherein the successive approximation control circuit performs controls for each successive approximation step such that one of the second capacitor group and the third capacitor group is coupled to a non-inverting input terminal of the comparator and the other one of the second capacitor group and the third capacitor group is coupled to an inverting input terminal of the comparator based on the determination output result from the comparator for each successive approximation step, and wherein the successive approximation control circuit is configured such that a capacitor terminal of the second capacitor group and a capacitor terminal of the third capacitor group which are coupled to the input terminal of the comparator have the same potential when electric charges corresponding to the reference voltage is stored in advance in the second capacitor group and the third capacitor group.

2. The successive approximation AD converter according to claim 1, wherein the electric charges are stored in only the second capacitor group when the reference voltage is stored in advance in the second capacitor group and the third capacitor group.

3. The successive approximation AD converter according to claim 1, wherein the capacitor terminal of the second capacitor group and the capacitor terminal of the third capacitor group which are coupled to the input terminal of the comparator are applied the reference voltage when the electric charges corresponding to the reference voltage is stored in advance in the second capacitor group and the third capacitor group.

4. The successive approximation AD converter according to claim 1, wherein the second capacitor group and the third capacitor group comprise a plurality of capacitive elements which is weighted.

5. The successive approximation AD converter according to claim 1, wherein the second capacitor group and the third capacitor group comprise a plurality of capacitive elements with the same capacitance value.

6. The successive approximation AD converter according to claim 5, wherein the second capacitor group and the third capacitor group are the same.

7. The successive approximation AD converter according to claim 1, wherein the second capacitor group and the third capacitor group comprise a plurality of capacitive elements which is weighted with a power of 2.

8. The successive approximation AD converter according to claim 1, wherein the successive approximation control circuit performs a successive approximation control in synchronization with a clock signal which is externally received.

9. The successive approximation AD converter according to claim 1, further comprising a switching circuit that switches a connection relationship of two ends of the first capacitor, the second capacitor group, and the third capacitor group, wherein the switching circuit switches the connection relationship such that the analog input signal is coupled to one end of the first capacitor and one end of the second capacitor group and one end of the third capacitor group have the same potential in a first period.

10. The successive approximation AD converter according to claim 9, wherein the switching circuit couples the one end of the second capacitor group and the one end of the third capacitor group to the reference voltage in the first period.

11. The successive approximation AD converter according to claim 9, wherein the switching circuit couples the one end of the second capacitor group and the one end of the third capacitor group in the first period.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0027] FIG. 1 is a diagram schematically illustrating a configuration of a charge redistribution type successive approximation AD converter according to the related art;

[0028] FIG. 2 is a diagram schematically illustrating a configuration of a charge sharing type successive approximation AD converter according to the related art;

[0029] FIG. 3 is a diagram illustrating an example of a configuration of the charge sharing type successive approximation AD converter according to the related art;

[0030] FIG. 4 is a diagram illustrating an example of an operation of a sampling phase in the charge sharing type successive approximation AD converter according to the related art;

[0031] FIG. 5 is a diagram illustrating an example of an operation at the time of determining a most significant bit in the charge sharing type successive approximation AD converter according to the related art;

[0032] FIG. 6 is a diagram illustrating an example of an operation at the time of determining a second high-order bit in the charge sharing type successive approximation AD converter according to the related art;

[0033] FIG. 7 is a diagram illustrating an example of an operation at the time of determining a third high-order bit in the charge sharing type successive approximation AD converter according to the related art;

[0034] FIG. 8 is a diagram illustrating problems of the sampling phase in the charge sharing type successive approximation AD converter according to the related art;

[0035] FIG. 9 is a diagram illustrating problems at the time of determining a second high-order bit in the charge sharing type successive approximation AD converter according to the related art;

[0036] FIG. 10 is a diagram schematically illustrating a configuration of a successive approximation AD converter according to a first embodiment;

[0037] FIG. 11 is a diagram illustrating an example of the configuration of the successive approximation AD converter according to the first embodiment;

[0038] FIG. 12 is a diagram illustrating another example of the configuration of the successive approximation AD converter according to the first embodiment;

[0039] FIG. 13 is a diagram illustrating an example of an operation of a sampling phase in the successive approximation AD converter according to the first embodiment;

[0040] FIG. 14 is a diagram illustrating an example of an operation at the time of determining a most significant bit in the successive approximation AD converter according to the first embodiment;

[0041] FIG. 15 is a diagram illustrating an example of an operation at the time of determining a second high-order bit in the successive approximation AD converter according to the first embodiment;

[0042] FIG. 16 is a diagram illustrating an example of an operation at the time of determining a third high-order bit in the successive approximation AD converter according to the first embodiment;

[0043] FIG. 17 is a diagram illustrating an example of an operation (with a parasitic capacitance) of the sampling phase in the successive approximation AD converter according to the first embodiment;

[0044] FIG. 18 is a diagram illustrating an example of an operation at the time of determining a second high-order bit in the successive approximation AD converter according to the first embodiment;

[0045] FIG. 19 is a diagram illustrating a difference between the disclosure and the related art;

[0046] FIG. 20 is a diagram illustrating an example of an operation of a sampling phase in a successive approximation AD converter according to a second embodiment;

[0047] FIG. 21 is a diagram illustrating an example of an operation at the time of determining a most significant bit in the successive approximation AD converter according to the second embodiment; and

[0048] FIG. 22 is a diagram illustrating an example of an operation at the time of determining a second high-order bit in the successive approximation AD converter according to the second embodiment.

DESCRIPTION OF THE EMBODIMENTS

[0049] Hereinafter, the disclosure will be described with reference to embodiments. The following embodiments are not intended to limit the configurations described in the appended claims. All combinations of features described in the embodiments cannot be said to be essential to solutions of the invention.

First Embodiment

[0050] An embodiment of the disclosure will be described below with reference to FIG. 10. FIG. 10 is a diagram schematically illustrating a configuration of a successive approximation AD converter according to a first embodiment. The successive approximation AD converter 100 is a charge sharing type successive approximation AD converter and includes a successive approximation control circuit 10, a comparator 20, a first capacitor 30 that is coupled to an input terminal of the comparator 20, is configured to be able to couple to an analog input signal, and is able to store electric charges in advance, and a second capacitor group 40 and a third capacitor group 50 that are configured to be able to couple to a reference voltage and are able to store electric charges in advance. The second capacitor group 40 and the third capacitor group 50 include a plurality of capacitive elements which is weighted (for example, weighted with a power of 2). The first capacitor 30 is coupled to an input terminal of the comparator 20.

[0051] The successive approximation control circuit 10 performs controls for each successive approximation step such that one of the second capacitor group 40 and the third capacitor group 50 which are weighted is coupled to a P-side input terminal of the comparator 20 and the other is coupled to an N-side input terminal of the comparator 20 based on a determination output result from the comparator 20 for each successive approximation step, and sets the determination output result from the comparator 20 which is sequentially determined as a digital output signal.

[0052] FIG. 11 is a diagram illustrating an example of the configuration of the successive approximation AD converter according to the first embodiment. As illustrated in FIG. 11, the first capacitor 30 is coupled to an analog input signal via a switch (switching circuit) 60. The second capacitor group 40 and the third capacitor group 50 are coupled to a reference voltage via a switch (switching circuit) 70. Capacitor terminals which are coupled to an input of the comparator 20 at the time of performing a successive approximation operation out of capacitor terminals of the second capacitor group 40 and the third capacitor group 50 are coupled via a switch 70 to have the same potential. For example, a voltage Vc is applied in FIG. 11, but the capacitor terminals may merely short-circuit as illustrated in FIG. 12.

[0053] Circuit operations of the successive approximation AD converter 100 will be sequentially described below for each successive approximation step with reference to FIGS. 13 to 16. For the purpose of simplification, an operation example of the successive approximation AD converter 100 of 3 bits will be described below.

[0054] FIG. 13 is a diagram illustrating a state in a sampling phase before the successive approximation operation is performed. As illustrated in FIG. 13, in the sampling phase, an analog input is coupled to the first capacitor 30 via a switch 60 and electric charges corresponding to an analog input voltage is stored in the first capacitor 30. On the other hand, a reference voltage is coupled to the second capacitor group 40 and the third capacitor group 50 via the switch 70, and electric charges corresponding to the reference voltage is stored in the second capacitor group 40 and the third capacitor group 50 in advance. The disclosure is characterized in that the capacitor terminals of the second capacitor group 40 and the third capacitor group 50 which are coupled to the input of the comparator 20 have the same potential when the electric charges corresponding to the reference voltage is stored in advance. In the description of the operation, the potential is set to V. which is equal to the reference voltage.

[0055] More specifically, when the analog input voltage is a differential input voltage expressed by V.sub.inp−V.sub.inn, electric charges of Q.sub.p=−8CV.sub.inn and Q.sub.n=−8CV.sub.inp are stored in the capacitors 30 coupled to the P-side input terminal and the N-side input terminal of the comparator 20.

[0056] On the other hand, electric charges of Q.sub.ref42=4CV.sub.ref is stored in a capacitive element with a greatest weight in the second capacitor group 40, and electric charges of Q.sub.ref41=2CV.sub.ref is stored in a capacitive element with a second greatest weight in the second capacitor group 40. Electric charges of Q.sub.ref52=4C(V.sub.ref−V.sub.ref)=0 is stored in a capacitive element with a greatest weight in the third capacitor group 50, and electric charges of Q.sub.ref51=2C(V.sub.ref−V.sub.ref)=0 is stored in a capacitive element with a second greatest weight in the third capacitor group 50. That is, substantially, electric charges are not stored in the third capacitor group 50 in this embodiment.

[0057] FIG. 14 is a diagram illustrating a state at the time of determining a most significant bit. As illustrated in FIG. 14, a terminal of the first capacitor 30 which is not coupled to the comparator 20 is coupled to a voltage which is to be a common voltage of the comparator 20. The terminal is coupled to, for example, the ground in FIG. 14.

[0058] Here, when the input terminals of the comparator 20 are V.sub.p and V.sub.n, a differential input voltage of the comparator 20 is V.sub.p−V.sub.n=V.sub.inp−V.sub.inn. When V.sub.inp−V.sub.inn=0.3V.sub.ref is supposed, the input voltage of the comparator 20 is V.sub.p−V.sub.n=V.sub.inp−V.sub.inn=0.3V.sub.ref>0, the comparator 20 generates “1,” and the most significant bit is determined to be “1.”

[0059] FIG. 15 is a diagram illustrating a state at the time of determining a second high-order bit. As illustrated in FIG. 15, the most significant bit is 1, thus a capacitive element with a greatest weight in the second capacitor group 40 is coupled to the N-side input terminal of the comparator 20 via a switch (switching circuit) 80. On the other hand, the most significant bit is 1, thus a capacitive element with a greatest weight in the third capacitor group 50 is coupled to the P-side input terminal of the comparator 20 via the switch 80. More specifically, electric charges of Q.sub.ref42=4CV.sub.ref which are stored in the sampling phase is applied to the N-side input terminal of the comparator 20 and electric charges of Q.sub.ref52=0 is applied to the P-side input terminal of the comparator 20.

[0060] Accordingly, a total sum of the electric charges Q.sub.p in the P-side input terminal of the comparator 20 and a total sum of the electric charges Q.sub.n in the N-side input terminal of the comparator 20 are Q.sub.p=−8CV.sub.inn and Q.sub.n=−8CV.sub.inp+4CV.sub.ref, respectively. The input voltage of the comparator 20 is V.sub.p−V.sub.n={8C(V.sub.inp−V.sub.inn)−4CV.sub.ref}/12C =2/3{(V.sub.inp−V.sub.inn)−0.5V.sub.ref}. Here, since V.sub.inp−V.sub.inn=0.3V.sub.ref is supposed, V.sub.p−V.sub.n=2/3{0.3V.sub.ref−0.5V.sub.ref}<0 is satisfied, the comparator 20 generates “0,” and the second high-order bit is determined to be “0.”

[0061] FIG. 16 is a diagram illustrating a state at the time of determining a third high-order bit. As illustrated in FIG. 16, the second high-order bit is “0”, thus a capacitive element with a second greatest weight in the second capacitor group 40 is coupled to the P-side input terminal of the comparator 20 via the switch 80. On the other hand, the second high-order bit is “0”, thus a capacitive element with a second greatest weight in the third capacitor group 50 is coupled to the N-side input terminal of the comparator 20 via the switch 80. More specifically, electric charges of Q.sub.ref41=2CV.sub.ref which are stored in the sampling phase is applied to the P-side input terminal of the comparator 20 and electric charges of Q.sub.ref51=0 are applied to the N-side input terminal of the comparator 20. At this time, the capacitive elements with the greatest weight which are coupled at the time of determining the second high-order bit in the second capacitor group 40 and the third capacitor group 50 are kept coupled to the input of the comparator 20.

[0062] Accordingly, the total sum of the electric charges Q.sub.p in the P-side input terminal of the comparator 20 and the total sum of the electric charges Q.sub.n in the N-side input terminal of the comparator 20 are Q.sub.p=−8CV.sub.inn+2CV.sub.ref and Q.sub.n=−8CV.sub.inp+4CV.sub.ref, respectively. The input voltage of the comparator 20 is V.sub.p−V.sub.n={8C(V.sub.inp−V.sub.inn)−2CV.sub.ref}/14C=4/7{(V.sub.inp−V.sub.inn)−0.25V.sub.ref}. Here, since V.sub.inp−V.sub.inn=0.3V.sub.ref is supposed, V.sub.p−V.sub.n=4/7{0.3V.sub.ref−0.25V.sub.ref}>0 is satisfied, the comparator 20 generates “1,” and the third high-order bit is determined to be “1.”

[0063] Through a series of successive approximation steps described above and illustrated in FIGS. 13 to 16, the analog input signal V.sub.inp−V.sub.inn=0.3V.sub.ref is converted to a digital output “101” in an analog-digital conversion manner. These successive approximation steps may be performed in synchronization with a clock signal which is received from outside. This is because voltage comparison with higher accuracy becomes possible by selecting the clock signal such that a time of one cycle of the clock signal is longer than a time which is consumed in completion of migration of the electric charges.

[0064] It will be described below that an AD converter with high accuracy can be provided according to the disclosure even when a parasitic capacitor is present in the second capacitor group 40 and the third capacitor group 50 with reference to FIGS. 17 and 18.

[0065] As illustrated in FIG. 17, it is assumed that C.sub.p1 and C.sub.p2 are added as parasitic capacitors to both ends of each capacitive element of the second capacitor group 40 and C.sub.p1 and C.sub.p2 are added as parasitic capacitors to both ends of each capacitive element of the third capacitor group 50. The second capacitor group 40 and the third capacitor group 50 may have the same capacitance value and the same layout (when the capacitive elements are formed on an integrated circuit). This is because the parasitic capacitance values of the second capacitor group 40 and the third capacitor group 50 can be set to be equivalent. Accordingly, the second capacitor group 40 and the third capacitor group 50 may be the same. Here, the “same” means that the second capacitor group 40 and the third capacitor group 50 are the same in shape (layout), material, constituent, and the like as well as in capacitance value.

[0066] In the sampling phase, electric charges of Q.sub.ref42=4CV.sub.ref are stored in the capacitive element with a greatest weight in the second capacitor group 40, and ΔQ.sub.1=C.sub.p1.Math.V.sub.ref and ΔQ.sub.2=C.sub.p20=0 are stored in C.sub.p1 and C.sub.p2, respectively. Electric charges of Q.sub.ref52=4C(V.sub.ref−V.sub.ref)=0 are stored in the capacitive element with the greatest weight in the third capacitor group 50. That is, substantially, electric charges are not stored in the third capacitor group 50 in this embodiment. Electric charges of ΔQ.sub.1=C.sub.p1.Math.V.sub.ref and ΔQ.sub.2=C.sub.p2.Math.V.sub.ref are stored in C.sub.p1 and C.sub.p2.

[0067] Thereafter, determination of the most significant bit is not affected by the parasitic capacitors as in the related art. On the other hand, determination of the second high-order bit is affected in the same way as in the related art.

[0068] This will be more specifically described below with reference to FIG. 18. electric charges Q.sub.p in the P-side input terminal of the comparator 20 and electric charges Q.sub.n in the N-side input terminal of the comparator 20 at the time of determining the second high-order bit are Q.sub.p=−8CV.sub.inn+C.sub.p1V.sub.ref and Q.sub.n=−8CV.sub.inp+4CV.sub.ref+C.sub.p1V.sub.ref, respectively. The input voltage of the comparator 20 is V.sub.p−V.sub.n={8C(V.sub.inp−V.sub.inn)−4CV.sub.ref+C.sub.p1V.sub.ref−C.sub.p1V.sub.ref}/(12C+C.sub.p1)=8C/(12C+C.sub.p1){(V.sub.inp−V.sub.inn)−0.5V.sub.ref}.

[0069] As described above, according to the disclosure, since terms which are added in consideration of the parasitic capacitors in the second capacitor group 40 and the third capacitor group 50 are cancelled out, deterioration in linearity of the AD converter due to the parasitic capacitors does not occur in comparison with the related art. In the related art, one capacitor group that stores the reference voltage in advance is prepared and the one capacitor group is coupled to the input terminals of the comparator 20 with a predetermined polarity or an opposite polarity thereof based on a signal from the successive approximation control circuit. On the other hand, according to the disclosure, the aforementioned advantages are achieved based on a distinct structural difference that two capacitor groups that store electric charges corresponding to the reference voltage in advance are prepared, and one thereof is coupled to the P-side input terminal of the comparator 20 and the other thereof is coupled to the N-side input terminal of the comparator 20 based on a signal from the successive approximation control circuit 10.

[0070] This difference will be more visually described with reference to FIG. 19. In the related art, when electric charges corresponding to the reference voltage which are stored in the capacitor are coupled to the input of the comparator 20 (which is equivalent to the capacitor storing the input voltage), such connection is performed with a predetermined polarity or the opposite polarity thereof as illustrated in the upper part of FIG. 19. In the disclosure, electric charges corresponding to the reference voltage which are stored in the capacitor are coupled to only one of the input of the comparator 20. In order to cancel out an influence of the parasitic capacitors, another capacitor that does not store electric charges is prepared, and is coupled to the other input of the comparator 20. The disclosure is characterized in that control is performed such that the voltages of the capacitor terminals coupled to the comparator 20 are the same potentials when electric charges corresponding to the reference voltage are stored in advance, whereby an influence of parasitic capacitors is cancelled out.

Second Embodiment

[0071] FIG. 20 is a diagram schematically illustrating a configuration of a successive approximation AD converter according to a second embodiment. The successive approximation AD converter 101 is a charge sharing type successive approximation AD converter and includes a successive approximation control circuit 10, a comparator 20, a first capacitor 30 that is coupled to an input terminal of the comparator 20, is configured to be able to couple to an analog input signal, and is able to store electric charges in advance, and a second capacitor group 40 and a third capacitor group 50 that are configured to be able to couple to a reference voltage and are able to store electric charges in advance. The second capacitor group 40 and the third capacitor group 50 include a plurality of capacitive elements which is weighted.

[0072] The successive approximation control circuit 10 performs control for each successive approximation step such that one of the second capacitor group 40 and the third capacitor group 50 which are weighted is coupled to a P-side input terminal of the comparator 20 and the other is coupled to an N-side input terminal of the comparator 20 based on a determination output result from the comparator 20 for each successive approximation step, and sets the determination output result from the comparator 20 which is sequentially determined as a digital output signal.

[0073] The successive approximation AD converter 101 according to this embodiment is different from the successive approximation AD converter 100 according to the first embodiment, in that an analog input signal is a single end signal. A full scale range of the AD converter ranges from −V.sub.ref to +V.sub.ref in the first embodiment, but ranges from 0 to +V.sub.ref in this embodiment.

[0074] Circuit operations of the successive approximation AD converter 101 will be sequentially described below for each successive approximation step with reference to FIGS. 20 to 22. For the purpose of simplification, an operation example of the successive approximation AD converter 101 of 3 bits will be described below.

[0075] FIG. 20 is a diagram illustrating a state in a sampling phase before the successive approximation operation is performed. As illustrated in FIG. 20, in the sampling phase according to this embodiment, an analog input and a reference voltage are coupled to the first capacitor 30 via a switch 60 and electric charges corresponding to an analog input voltage and electric charges corresponding to the reference voltage are stored in the first capacitor 30. The operations of the second capacitor group 40 and the third capacitor group 50 are the same as in the first embodiment and thus description thereof will be omitted. In this embodiment, when the electric charges corresponding to the reference voltage are stored in advance, the electric charges are stored in the second capacitor group 40, and the electric charges are not stored in the third capacitor group 50.

[0076] More specifically, when the analog input voltage is a single-end input voltage expressed by V.sub.in, electric charges of Q.sub.p=−8CV.sub.ref and Q.sub.n=−16CV.sub.in are stored in the capacitors 30 coupled to the P-side input terminal and the N-side input terminal of the comparator 20.

[0077] On the other hand, electric charges of Q.sub.ref42=4CV.sub.ref are stored in a capacitive element with a greatest weight in the second capacitor group 40, and ΔQ.sub.1=C.sub.p1.Math.V.sub.ref and ΔQ.sub.2=C.sub.p2.Math.0=0 are stored in C.sub.p1 and C.sub.p2, respectively. The electric charges of Q.sub.ref52=4C(V.sub.ref−V.sub.ref)=0 are stored in a capacitive element with a greatest weight in the third capacitor group 50. That is, substantially, the electric charges are not stored in the third capacitor group 50 in this embodiment. ΔQ.sub.1=C.sub.p1.Math.V.sub.ref and ΔQ.sub.2=C.sub.p2.Math.0=0 are stored in C.sub.p1 and C.sub.p2, respectively.

[0078] FIG. 21 is a diagram illustrating a state at the time of determining a most significant bit. As illustrated in FIG. 21, a terminal of the first capacitor 30 which is not coupled to the comparator 20 is coupled to a voltage which is to be a common voltage of the comparator 20. The terminal is coupled to, for example, the ground in FIG. 21. The capacitor on the reference voltage side is configured to have a capacitance value of a half the capacitance value on the analog input voltage side as illustrated in the drawing.

[0079] Here, when the input terminals of the comparator 20 are V.sub.p and V.sub.n, a differential input voltage of the comparator 20 is V.sub.p−V.sub.n=V.sub.in310.5V.sub.ref. When V.sub.in=0.6V.sub.ref is supposed, the input voltage of the comparator 20 is V.sub.p−V.sub.n=0.1V.sub.ref>0, the comparator 20 generates “1,” and the most significant bit is determined to be “1.”

[0080] FIG. 22 is a diagram illustrating a state at the time of determining a second high-order bit. As illustrated in FIG. 22, the most significant bit is “1”, thus a capacitive element with a greatest weight in the second capacitor group 40 is coupled to the N-side input terminal of the comparator 20 via the switch 80. On the other hand, the most significant bit is “1”, thus a capacitive element with a greatest weight in the third capacitor group 50 is coupled to the P-side input terminal of the comparator 20 via the switch 80. More specifically, the electric charges of Q.sub.ref42=4CV.sub.ref which are stored in the sampling phase is applied to the N-side input terminal of the comparator 20 and the electric charges of Qref52 =0 are applied to the P-side input terminal of the comparator 20.

[0081] Accordingly, the total sum of the electric charges Q.sub.p in the P-side input terminal of the comparator 20 and the total sum of the electric charges Q.sub.n in the N-side input terminal of the comparator 20 are Q.sub.p=−8CV.sub.ref+C.sub.p1V.sub.ref and Q.sub.n 32 −16CVin+4CV.sub.ref+C.sub.p1V.sub.ref, respectively. The input voltage of the comparator 20 is V.sub.p−V.sub.n=(16CVin-8CV.sub.ref−4CV.sub.ref+C.sub.p1V.sub.ref−C.sub.p1V.sub.ref)/(20C+C.sub.p1)=16C/(20C+C.sub.p1)(Vin−0.75V.sub.ref). Here, since V.sub.in=0.6V.sub.ref is supposed, V.sub.p−V.sub.n=16C/(20C+C.sub.p1)(0.6V.sub.ref−0.75V.sub.ref)<0 is satisfied, the comparator 20 generates “0,” and the second high-order bit is determined to be “0.”

[0082] As described above, according to this embodiment, since terms which are added in consideration of the parasitic capacitors in the second capacitor group 40 and the third capacitor group 50 are cancelled out, deterioration in linearity of the AD converter due to the parasitic capacitors does not occur. The operations for the third high-order bit or bits subsequent thereto are the same as in the first embodiment and thus description will be omitted.

[0083] While the disclosure has been described above with reference to embodiments, the technical scope of the disclosure is not limited to the scopes described in the embodiments. It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the disclosure covers modifications and variations provided that they fall within the scope of the following claims and their equivalents.

[0084] It should be noted that the order of performing processes such as operations, sequences, steps, and stages in devices, systems, programs, and methods described in the claims, the specification, and the drawings can be realized in arbitrary order as long as “before,” “prior to,” or the like is not particularly explicitly described and an output of a previous process is not used for a subsequent process. Even when operation flows in the claims, the specification, and the drawings are described using “first,” “then,” or the like for the purpose of convenience, it is not essential to perform the operation flows in that order.