Switching of paralleled reverse conducting IGBT and wide bandgap switch

Abstract

A semiconductor module comprises reverse conducting IGBT connected in parallel with a wide bandgap MOSFET, wherein each of the reverse conducting IGBT and the wide bandgap MOSFET comprises an internal anti-parallel diode. A method for operating a semiconductor module with the method including the steps of: determining a reverse conduction start time, in which the semiconductor module starts to conduct a current in a reverse direction, which reverse direction is a conducting direction of the internal anti-parallel diodes; applying a positive gate signal to the wide bandgap MOSFET after the reverse conduction start time; determining a reverse conduction end time based on the reverse conduction start time, in which the semiconductor module ends to conduct a current in the reverse direction; and applying a reduced gate signal to the wide bandgap MOSFET a blanking time interval before the reverse conduction end time, the reduced gate signal being adapted for switching the wide bandgap MOSFET into a blocking state.

Claims

1. A method for operating a semiconductor module with a reverse conducting IGBT connected in parallel with a wide bandgap MOSFET, wherein each of the reverse conducting IGBT and the wide bandgap MOSFET comprises an internal anti-parallel diode, the method comprising the steps of: determining a reverse conduction start time, in which the semiconductor module starts to conduct a current in a reverse direction, which reverse direction is a conducting direction of the internal anti-parallel diodes; applying a positive gate signal to the wide bandgap MOSFET after the reverse conduction start time; determining a reverse conduction end time based on the reverse conduction start time, in which the semiconductor module ends to conduct a current in the reverse direction, wherein the reverse conduction end time is determined by adding an offset to the reverse conduction start time; and applying a reduced gate signal to the wide bandgap MOSFET a blanking time interval before the reverse conduction end time, the reduced gate signal being adapted for switching the wide bandgap MOSFET into a blocking state.

2. The method of claim 1, wherein the positive gate signal is applied to the wide bandgap MOSFET a blanking time interval after the reverse conduction start time.

3. The method of claim 1, wherein a reduced gate signal for the reverse conducting IGBT is maintained between the reverse conduction start time and the reverse conduction end time, the reduced gate signal being adapted for switching the reverse conducting IGBT into a blocking state.

4. The method of claim 1, further comprising: applying a positive gate signal to the reverse conducting IGBT an extraction time interval prior to the blanking time interval before the reverse conduction end time; applying a reduced gate signal to the reverse conducting IGBT the blanking time interval before the reverse conduction end time.

5. The method of claim 1, wherein the blanking time interval is lower than 14 μs.

6. The method of claim 1, wherein the extraction time interval is between 10 μs and 90 μs.

7. The method of claim 1, wherein the positive gate signal of the reverse conducting IGBT has a voltage higher than a threshold voltage of the reverse conducting IGBT.

8. The method of claim 1, wherein the positive gate signal of the wide bandgap MOSFET has a voltage higher than a threshold voltage of the wide bandgap MOSFET.

9. The method of claim 1, wherein a reduced gate signal of the reverse conducting IGBT is at least one of: a voltage less than or equal to equal 0 V; and a voltage lower than a threshold voltage of the reverse conducting IGBT.

10. The method of claim 1, wherein the reduced gate signal of the wide bandgap MOSFET is at least one of: a voltage less than or equal to equal 0 V; and a voltage lower than a threshold voltage of the wide bandgap MOSFET.

11. The method according to claim 1, wherein the reverse conducting IGBT is a Si based BIGT having an IGBT and a reverse conducting IGBT combined in one chip.

12. The method according to claim 1, wherein the wide band-gap MOSFET is based on SiC or GaN.

13. The method of claim 2, wherein a reduced gate signal for the reverse conducting IGBT is maintained between the reverse conduction start time and the reverse conduction end time, the reduced gate signal being adapted for switching the reverse conducting IGBT into a blocking state.

14. The method of claim 2, further comprising: applying a positive gate signal to the reverse conducting IGBT an extraction time interval prior to the blanking time interval before the reverse conduction end time; applying a reduced gate signal to the reverse conducting IGBT the blanking time interval before the reverse conduction end time.

15. The method of claim 2, wherein the blanking time interval is lower than 14 μs.

16. The method of claim 2, wherein the extraction time interval is between 10 μs and 90 μs.

17. The method of claim 2, wherein the positive gate signal of the reverse conducting IGBT has a voltage higher than a threshold voltage of the reverse conducting IGBT.

18. The method of claim 2, wherein the positive gate signal of the wide bandgap MOSFET has a voltage higher than a threshold voltage of the wide bandgap MOSFET.

19. A semiconductor module, comprising: a reverse conducting IGBT with an internal anti-parallel diode; a wide bandgap MOSFET connected in parallel with the reverse conducting IGBT, the wide bandgap MOSFET having an internal anti-parallel diode; and a controller for providing a gate signal for the reverse conducting IGBT and a different gate signal for the wide bandgap MOSFET; wherein the semiconductor module is configured for performing the following operations based on processing by the controller: determine a reverse conduction start time, in which the semiconductor module starts to conduct a current in a reverse direction, which reverse direction is a conducting direction of the internal anti-parallel diodes; apply a positive gate signal to the wide bandgap MOSFET after the reverse conduction start time; determine a reverse conduction end time based on the reverse conduction start time, in which the semiconductor module ends to conduct a current in the reverse direction, wherein the reverse conduction end time is determined by adding an offset to the reverse conduction start time; and apply a reduced gate signal to the wide bandgap MOSFET a blanking time interval before the reverse conduction end time, the reduced gate signal being adapted for switching the wide bandgap MOSFET into a blocking state.

20. A half bridge comprising two semiconductor modules according to claim 19 in series.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The subject-matter of the invention will be explained in more detail in the following text with reference to exemplary embodiments which are illustrated in the attached drawings.

(2) FIG. 1 schematically shows a perspective view of a cell of a reverse conducting IGBT.

(3) FIG. 2 schematically shows a perspective view of a cell of a SiC MOSFET.

(4) FIG. 3 schematically shows a cross-section through a BIGT.

(5) FIG. 4 schematically shows a half-bridge according to an embodiment of the invention.

(6) FIG. 5 shows a diagram with gate signals according to an embodiment of the invention.

(7) FIG. 6 shows a diagram with gate signals according to a further embodiment of the invention.

(8) FIG. 7 shows a diagram with gate signals according to a further embodiment of the invention.

(9) FIG. 8 shows a diagram with characteristic curves for a reverse conducting IGBT or BIGT.

(10) FIG. 9 shows a diagram with characteristic curves for a SiC MOSFET.

(11) The reference symbols used in the drawings, and their meanings, are listed in summary form in the list of reference symbols. In principle, identical parts are provided with the same reference symbols in the figures.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

(12) FIG. 1 shows a cell of a reverse conducting IGBT (insulated gate bipolar transistor) 10. The reverse conducting IGBT 10 is composed of a plurality of these cells, which are all provided in one chip substrate.

(13) On a first end (collector side), the reverse conducting IGBT 10 comprises a collector 12 in the form of a first planar terminal and on a second end (emitter side) opposing the first end, the reverse conducting IGBT 10 comprises an emitter 14 in the form of a second planar terminal. Further, neighboring the second planar terminal, the reverse conducting IGBT 10 comprises a gate 16 for controlling reverse conducting IGBT 10. Adjacent to the gate 16, an n+-doped region 18 in form of a source layer and a p-doped region 20 in form of a well layer are arranged, which are at least partially embedded in an n-doped base layer 22. The n-base layer 22 adjoins an n+ higher doped buffer layer 24, which in turn adjoins a p-doped region 26 (collector layer) and an n-doped region 28 (shorts) arranged between the n-buffer layer 24 and the first planar terminal 12 forming an internal integrated diode 30 between the collector 12 and the emitter 14 to conduct currents in the reverse direction (i.e. from the emitter 14 to the collector 12).

(14) FIG. 2 shows a cell of a SiC MOSFET 32. The SiC MOSFET 32 is composed of a plurality of these cells, which are all provided in one chip substrate.

(15) The SiC MOSFET 32 comprises on a first end a drain 34 in the form of a first planar terminal 34, and on a second end opposing the first end a source 36 in the form of a second planar terminal 36. A gate 38 for controlling the SiC MOSFET 32 neighbors the second planar terminal 36. Adjacent to the gate 38, the SiC MOSFET 32 comprises an n+-doped region 40 and a p-doped region 42, which are at least partially embedded in an n-base layer 44. Between the n-base layer 44 and the first planar terminal 34, an n+-doped layer or n+-doped substrate 46 is arranged.

(16) The SiC MOSFET 32 comprises an internal body diode 48 formed of the layers between the source and the drain.

(17) FIG. 3 shows a cross-section through a BIGT (bi-mode IGBT) 10′, which is composed of a reverse conducting IGBT region 50 and an ordinary IGBT region 52 (having a large pilot p doped region 26 in the central part of the device on the collector side). The reverse conducting IGBT region 50 is composed of cells as shown in FIG. 1 (with alternating n and p doped regions 28, 26). The region 52 is composed of cells as the cell of FIG. 1 without the n-doped region 28 (i.e. only with p doped region 26). Exemplarily, the ordinary IGBT region 52 is surrounded by alternating smaller p doped regions 26 and n doped regions 28.

(18) FIG. 4 shows a half-bridge 54 composed of two semiconductor modules or more general semiconductor modules 56 connected in series. Each of the semiconductor modules 56 provides a controllable switch for connecting a midpoint 58 between the semiconductor modules 56 with a positive or negative voltage of a voltage source 60, such as a DC link.

(19) Each of the semiconductor modules 56 comprises a reverse conducting IGBT 10 or IGBT 10′ connected in parallel to a SiC MOSFET 32. Here and in the following, the SiC MOSFET 32 may be replaced with other wide bandgap MOSFET devices based on other wide bandgap semiconductor substrates such as GaN. The semiconductor switches 10, 10′, 32 provide with their collector 12 and drain 34 an upper output for the respective semiconductor module 56 and with their emitter 14 and source 36 a lower output for the respective semiconductor module 56. Due to the internal anti-parallel diodes 30, 48, a separate free-wheeling diode is not necessary.

(20) The gates 16, 38 are connected with a gate controller 62 for the respective semiconductor module 56, which is adapted for providing different gate signals for the semiconductor switches 10, 10′, 32. For example, the gate controller 62 may be mechanically attached to the same substrate to which the two semiconductor switches 10, 10′, 32 are bonded.

(21) The gate controller 62 may receive switching signals from a superordinated controller 64, which, for example, controls an inverter, the half-bridge is a part of. The switching signals of the controller 64 may be transformed into gate signals for the semiconductor switches 10, 10′, 32 by the gate controller 62.

(22) FIGS. 5, 6 and 7 show three diagrams with possible gate signals V.sub.GE and V.sub.GS that may be applied to the reverse conducting IGBT 10, 10′ and the wide bandgap MOSFET 32.

(23) The upper part of the diagrams show the voltage U.sub.R at the outputs of the semiconductor module 56, which may be seen as the reverse voltage across the diodes 30, 48. Before a reverse conduction start time t.sub.S, the voltage U.sub.R is positive (the voltage is reverse for the diodes 30, 48), since both diodes 30, 48 are blocking. Here, the reverse current I.sub.R flowing through the semiconductor module 56 is 0, i.e. in the direction from the lower output of the semiconductor module 56 (at the emitter and source of the switches 10, 10′ and 32) to the upper outputs (at the collector and drain). After a reversal of the voltage applied to the semiconductor module 56, the voltage U.sub.R becomes substantially 0, since the diodes 30, 48 become conducting and a current I.sub.R flows through the semiconductor module 56 in the reverse direction.

(24) This stays substantially the same, until the voltage applied to the semiconductor module 56 changes direction again at a reverse conduction end time t.sub.E. After the reverse conduction end time t.sub.E, the voltage U.sub.R becomes equal to the voltage applied to the semiconductor module 56, since the diodes 30, 48 block again. For a short time, the reverse current I.sub.R becomes negative, due to a depletion or extraction of charge carriers stored in the n-base or drift region of the switches 10, 10′, 32. After that, the reverse current I.sub.R becomes 0, i.e. no current is flowing through the semiconductor module 56.

(25) The reverse conduction start time t.sub.S and the reverse conduction end time t.sub.E may be determined by the gate controller 62 with measurements inside the semiconductor module 56, for example by measuring and extrapolating the voltage across the semiconductor module 56. Since the voltage across the module depends on the switching states of all the semiconductor modules 56 in the half-bridge, it also may be possible that the times t.sub.S and t.sub.E are determined from switching signals from the other semiconductor module 56 by the gate controller 62 and/or the controller 64.

(26) For example, the reverse conduction start time t.sub.S of the lower module or switch 56 of FIG. 4 may be the switching time, when the upper module or switch 56 is switched into an on state. Analogously, the reverse conduction end time t.sub.E of the lower module or switch 56 of FIG. 4 may be the switching time, when the upper module or switch 56 is switched into an off state. The reverse conduction end time t.sub.E of the lower module or switch 56 of FIG. 4 may be the reverse conduction start time t.sub.S of the upper module or switch 56 of FIG. 4 and vice versa. It has to be noted that the method as described herein, which is applied between the reverse conduction start time t.sub.S and the reverse conduction end time t.sub.E is applied to a module or switch 56 in an off state. Additionally, it has to be noted that with the method the reverse conducting IGBT 10 or IGBT 10′ and/or the SiC MOSFET 32 may be in a conducting state, although the module or switch 56 composed of them is in an off state, and vice versa.

(27) In all three methods for operating the semiconductor module 56 depicted in FIGS. 5, 6 and 7, the gate signal of the wide bandgap MOSFET 32 is switched to a positive voltage for substantially the complete time interval between the reverse conduction start time t.sub.S and the reverse conduction end time t.sub.E.

(28) A positive gate signal V.sub.GS is applied to the wide bandgap MOSFET 32 after the reverse conduction start time t.sub.S, in particular a blanking time t.sub.bl interval after the reverse conduction start time t.sub.S. The positive gate signal V.sub.GS is maintained before the reverse conduction end time t.sub.E, in particular, a blanking time t.sub.bl interval after the reverse conduction start time t.sub.S. After that, a reduced gate signal V.sub.GS is applied to the wide bandgap MOSFET 32 the blanking time interval t.sub.bl before the reverse conduction end time t.sub.E.

(29) The blanking time intervals t.sub.bl, which may have the same or different lengths, may have a length of few μs, such as about 10 μs, and/or may be used for preventing a phase-short and/or a shoot-through between different semiconductor modules 56.

(30) The positive gate signal V.sub.GS, which may be defined by the voltage between gate and source of the wide bandgap MOSFET 32, may be higher than a positive threshold voltage for switching the wide bandgap MOSFET 32, such as +15 V.

(31) The reduced gate signal V.sub.GS may be substantially 0 V or less, for example less than a positive threshold voltage of the wide bandgap MOSFET 32, such as −15 V.

(32) The switching of the wide bandgap MOSFET 32 in such a way has the advantage that the conduction losses of the wide bandgap MOSFET 32 and its internal diode 48 are reduced. This will be explained in more detail with respect to FIG. 9.

(33) As shown in FIG. 5, it may be possible that the reverse conducting IGBT 10, 10′ is switched analogously to the wide bandgap MOSFET 32.

(34) A positive gate signal V.sub.GE is applied to the reverse conducting IGBT 10, 10′ after the reverse conduction start time t.sub.S, in particular, a blanking time t.sub.bl interval after the reverse conduction start time t.sub.S. The positive gate signal V.sub.GE is maintained before the reverse conduction end time t.sub.E, in particular, a blanking time t.sub.bl interval after the reverse conduction start time t.sub.S. After that, a reduced gate signal V.sub.GE is applied to the reverse conducting IGBT 10, 10′ the blanking time interval t.sub.bl before the reverse conduction end time t.sub.E.

(35) The positive gate signal V.sub.GE, which may be defined by the voltage between gate and emitter of the reverse conducting IGBT 10, 10′, may be higher than a positive threshold voltage for switching the reverse conducting IGBT 10, 10′, such as +15 V.

(36) The reduced gate signal V.sub.GE may be substantially 0 V or less, for example less than a positive threshold voltage of the reverse conducting IGBT 10, 10′, such as −15 V.

(37) The control of the reverse conducting IGBT 10, 10′ may be called standard control, which however may cause a high on-state voltage drop of the internal diode 30 due to the extraction of the electrons through the inversion channel and hence less plasma inside the device. This behavior will be explained in more detail with respect to FIG. 8.

(38) Contrary to this, in so called MOS gate control, as shown in FIG. 6, a reduced gate signal V.sub.GE is applied during most of the time interval between t.sub.S and t.sub.E, which usually results in a low on-state voltage drop of the internal diode 30. This behavior will be explained in more detail with respect to FIG. 8.

(39) The reduced gate signal V.sub.GE may be maintained until an extraction time interval to and a blanking time interval t.sub.bl before the reverse conduction end time t.sub.E.

(40) The extraction time interval t.sub.e and the blanking time interval t.sub.bl before the reverse conduction end time t.sub.E, a positive gate signal V.sub.GE is applied to the reverse conducting IGBT 10, 10′. The blanking time t.sub.bl interval before the reverse conduction end time t.sub.E, a reduced gate signal V.sub.GE is again applied to the reverse conducting IGBT 10, 10′.

(41) Thus, during a relatively short time interval t.sub.e shortly before the reverse conduction end time t.sub.E, the reverse conducting IGBT is provided with a positive gate signal V.sub.GE. This does not much contribute to conduction losses (slightly increases) but may reduce reverse recovery losses considerably during turn-off (or reverse recovery) of the internal diode 30. The extraction time interval may have a length of few tens of μs.

(42) As shown in FIG. 7, it may be that the extraction time interval t.sub.e may be completely omitted for the reverse conducting IGBT 10, 10′ and/or that the reduced gate signal V.sub.GE applied to the reverse conducting IGBT 10, 10′ may be maintained. In such a way, a conduction of the internal body diode 48 of the wide bandgap MOSFET 32 during the blanking time interval may be completely suppressed, if the voltage drop of the internal diode 30 of the reverse conducting IGBT 10, 10′ may be maintained below 2.5 V at full load current. Before the end time t.sub.E, i.e. during the blanking time t.sub.bl, the channel diode (i.e. the MOSFET operates in the 3.sup.rd quadrant meaning current flows from source to drain through the inversion channel) of the wide bandgap MOSFET 32 is off due to the applied gate signal V.sub.GS which is below positive threshold voltage and all the load current will flow through the reverse conducting IGBT 10, 10′. Hence, the reliability of the wide bandgap MOSFET 32 may be improved, since internal body diode effect is suppressed and so no bipolar degradation takes place.

(43) FIG. 8 shows an example of characteristic curves of an IGBT 10′ (1.82 cm.sup.2 active area) in diode-mode, i.e. during anti-parallel diode conduction. The voltage drop is depicted from right to left, the current through the IGBT 10′, i.e. through the internal diode 30, is depicted from top to bottom. The measurements have been conducted at a temperature of 125° C.

(44) At V.sub.GE=0 V (continuous line, MOS-channel is off), the voltage drop is smaller than at V.sub.GE=15 V (dotted line, MOS-channel is on). At a rated current of the IGBT 10′ of 62.5 A and a temperature 125° C., the voltage drop and therefore the conduction losses can be reduced by 33% with VGE=0 V compared to VGE=15 V.

(45) FIG. 9 shows a diagram analogous to FIG. 8 for a SiC MOSFET 32 (0.3 cm.sup.2 active area) in diode-mode at a temperature of 125° C. The dotted line corresponds to V.sub.GS=+15 V, the continuous line to V.sub.GS=0 V and the dashed line to V.sub.GS=−15 V. At V.sub.GS=0 V, initially the MOS-channel is off, but due to body-bias effects the MOS channel turns on at V.sub.DS>−1.5 V. At V.sub.GS=−15V, the MOS channel is off and the internal body diode conducts. It can be seen that at V.sub.GS=15V (MOS-channel is on) the on-state voltage drop is smaller than at V.sub.GE=0 V. At a rated current of 20 A and 125° C., the on-state voltage drop can be reduced by 50% with V.sub.GE=15 V compared to VGE=0 V.

(46) In general, a reverse conducting IGBT 10, 10′ has higher conduction losses for a positive gate signal, whereas as wide bandgap MOSFET 32 has higher conduction losses for a reduced gate signal.

(47) To increase the performance of the reverse conducting IGBT 10, 10′ in diode-mode, i.e. mainly during diode conduction, the gate signal V.sub.GE may be 0 V or negative (such as −15V or 0V, which may achieve a 33% reduction of conduction losses compared to a positive gate signal (such as V.sub.GE=15 V), whereas for the wide bandgap MOSFET 32 in diode-mode, the gate signal V.sub.GS may be positive (such as +15 V, which may achieve a 50% reduction of conduction losses compared to 0 V or a negative gate signal (such as V.sub.GS=0 V or −15 V).

(48) While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive; the invention is not limited to the disclosed embodiments. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art and practising the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word “comprising” does not exclude other elements or steps, and the indefinite article “a” or “an” does not exclude a plurality. A single processor or controller or other unit may fulfil the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. Any reference signs in the claims should not be construed as limiting the scope.

LIST OF REFERENCE SYMBOLS

(49) 10 reverse conducting IGBT 10′ BIGT 12 collector, first planar terminal 14 emitter, second planar terminal 16 gate 18 n+-doped region 20 p-doped region 22 n-base layer 24 n-buffer layer 26 p-doped region 28 n-doped region 30 reverse conducting diode, internal anti-parallel diode 32 SiC MOSFET 34 drain, first planar terminal 36 source, second planar terminal 38 gate 40 n+-doped region 42 p-doped region 44 n-base layer 46 n+-doped layer 48 reverse conducting diode, internal anti-parallel diode, internal body diode 50 reverse conducting IGBT region 52 ordinary IGBT region 54 half-bridge 56 semiconductor module/composed semiconductor switch 58 midpoint 60 voltage source 62 gate controller 64 superordinated controller U.sub.R reverse module voltage I.sub.R reverse module current t.sub.S reverse conduction start time t.sub.E reverse conduction end time V.sub.GE gate signal for reverse conducting IGBT V.sub.GS gate signal for wide bandgap MOSFET t.sub.bl blanking time interval t.sub.e extraction time interval