Method for a transfer print between substrates

Abstract

The transfer of devices or device components from a carrier substrate to a further carrier substrate or to a plurality of further carrier substrates can be performed with little effort (few transfer steps) to the at least one further carrier substrate. The method comprises producing first devices on the first carrier substrate in a two-dimensional grid. It comprises defining positions on the second carrier substrate on the basis of the two-dimensional grid for at least some of the first devices. It comprises releasing a plurality of the first devices from the first carrier substrate while maintaining the two-dimensional grid. Finally, the plurality of first devices are applied to the second carrier substrate in the defined positions while maintaining the two-dimensional grid or a multiple thereof in at least one of the two directions.

Claims

1. A method for transferring devices from a first carrier substrate (10) to a second carrier substrate (20), comprising: producing first devices (12) on the first carrier substrate in a two-dimensional grid; pre-defining positions on the second carrier substrate on the basis of the two-dimensional grid on the first carrier substrate and positions of second devices (22) produced and present on the second carrier substrate for at least some of the first devices (12); wherein the second devices (22) on the second carrier substrate are produced based on the two-dimensional grid such that the defined positions have a spatial relationship to the second devices required for a technical function thereof; wherein the second devices (22) are produced by applying CMOS process techniques; wherein the two-dimensional grid is determined on the basis of a width and length of one of the first devices and an intermediate space required for release thereof; releasing a plurality of the first devices (12) from the first carrier substrate while maintaining the two-dimensional grid and transferring the released first devices to the second carrier substrate; applying the plurality of transferred first devices to the second carrier substrate in the defined positions while maintaining the two-dimensional grid; wherein further first devices in the two-dimensional grid on the first carrier substrate, not yet released therefrom, are released, transferred and applied to the second carrier substrate while maintaining the same two-dimensional grid in not yet occupied but defined positions; and wherein two or more first devices are accommodated in at least some of the second devices and in the two-dimensional grid; and the release of a plurality of the first devices from the first carrier substrate and a transfer for applying the released plurality of first devices to the second carrier substrate is performed by use of a transfer stamp, a lower stamp surface thereof being adjusted to the two-dimensional grid.

2. The method according to claim 1, wherein pitches of the two-dimensional grid in two directions linearly independent of each other each corresponds to a sum of the width and length of one of the first devices, respectively, and a respective intermediate space between neighbored first devices, required for release thereof.

3. The method according to claim 2, wherein the pre-defined positions on the second carrier substrate correspond to integer multiples of the pitches of the two-dimensional grid in both directions.

4. The method according to claim 1, wherein positions on a further carrier substrate are defined on the basis of the two-dimensional grid for at least some of the first devices, and a plurality of first devices of the first carrier substrate are applied to the further carrier substrate in the defined positions while maintaining the two-dimensional grid.

5. The method according to claim 1, wherein the first devices on the first carrier substrate are produced based on the two-dimensional grid such that the defined positions have a spatial relationship to the second devices required for a technical function thereof in a combination with one or more first devices.

6. The method according to claim 5, wherein the first devices (12) are produced by applying CMOS process techniques, and are CMOS devices.

7. The method according to claim 4, wherein further devices on the further carrier substrate are produced based on the two-dimensional grid such that the defined positions have a spatial relationship to the further devices required for the technical function thereof, and wherein the further devices are produced by applying CMOS process techniques.

8. The method according to claim 4, wherein an arrangement of the positions on the second carrier substrate differs from an arrangement of the positions on the further carrier substrate.

9. The method according to claim 5, wherein positions on a further carrier substrate are defined on the basis of the two-dimensional grid for at least some of the first devices, and a plurality of first devices of the first carrier substrate are applied to the further carrier substrate in the defined positions while maintaining the two-dimensional grid; and wherein an arrangement of the positions on the second carrier substrate differs from an arrangement of the positions on the further carrier substrate.

Description

SUMMARY OF EMBODIMENTS

(1) Embodiments of the invention are illustrated by examples and not in a way that transfers or incorporates limitations from the Figures into the patent claims. Same reference numerals in the Figures indicate same or highly similar elements.

(2) FIG. 1 is a schematic view of a first carrier substrate with devices and intermediate spaces forming a two-dimensional grid which serves as a basis for the positioning of these devices on a second carrier substrate.

(3) FIG. 2 shows a second carrier substrate with second devices, for example in the form of circuits, and devices transferred from the first carrier substrate, wherein the enlarged section of FIG. 2a shows the positions and the transferred devices defined on the basis of the two-dimensional grid which is determined by the first devices on the first carrier substrate.

(4) FIG. 2a shows the enlarged section of FIG. 2.

(5) FIG. 3 shows a schematic vertical cross-section through a stamp 30 having an elastomeric lower surface 31 or such lower surface parts.

DETAILED DESCRIPTION OF EMBODIMENTS

(6) All examples of the invention allow that devices, e.g. CMOS circuits, are or have been produced on a receiving carrier substrate, e.g. a semiconductor wafer. Per circuit, one or more devices of a donor carrier substrate, e.g. a semiconductor wafer, can be positioned by transfer printing. The devices on the donor semiconductor wafer are used in a highly efficient manner, i.e. as completely as possible (in the sense of preferably all devices per carrier wafer).

(7) Per stamping procedure, as many devices as possible are transferred simultaneously and disposed simultaneously in a plurality of positions of the receiving carrier substrate in devices or circuits possibly present thereon.

(8) In an advantageous embodiment, the positions for the devices to be transferred on the receiving carrier substrate, e.g. the semiconductor wafer, are arranged exclusively in a grid, the pitches of which are defined in a first direction, e.g. the horizontal direction in the subsequently described Figures, and in a second direction linearly independent of the first direction, e.g. the vertical direction in the following illustration, by the sizes of the devices to be transferred and the intermediate space required for etching them free on the donor carrier substrate, e.g. a semiconductor wafer. The width of the intermediate space or scribing trench is predetermined by the technical requirements for etching free, e.g. the width required for etching a trench to the required depth, and for positioning the connection elements. This grid is used on the receiving carrier substrate for both, devices to be transferred in adjacent circuits and a plurality of devices to be transferred per circuit.

(9) In one embodiment, a distance between two positions and thus two devices to be transferred on the receiving carrier substrate in the first linearly independent direction, e.g. the horizontal direction, is defined as an integer multiple, with N=1, 2, 3, . . . , n, of the pitch in this direction. In an advantageous variant, the underlying pitch is the sum of the “horizontal” device dimension plus the horizontal intermediate space dimension. The distance between the second positions in the other linearly independent direction, i.e. the “vertical” direction, is defined as an integer multiple of the sum of the “vertical” device dimension plus the “vertical” intermediate space dimension.

(10) In one embodiment, the arrangement of the devices on the first carrier substrate is a grid preferably occupied in all positions and having the above-defined pitch.

(11) The arrangement of the devices applied by transfer printing on the receiving carrier substrate is a uniform grid across the entire wafer, wherein, however, only every m.sup.th position in the “horizontal” direction and every n.sup.th position in the “vertical” direction are occupied, wherein m, n=1, 2, 3, . . . applies.

(12) The arrangement of the devices to be transferred on a transfer device, e.g. a stamp 30 according to FIG. 3, is thus a uniform grid, wherein, corresponding to the defined positions, consequently only every m.sup.th position in the “horizontal” direction and every n.sup.th position in the “vertical” direction are occupied, wherein m, n=1, 2, 3, . . . applies. That is, in transfer printing, every m.sup.th device in the “horizontal” direction and every n.sup.th device in the “vertical” direction are transferred simultaneously. In the next printing procedure, this grid is shifted, for example, by one pitch and the next devices are transferred.

(13) A plurality of devices are transferred simultaneously per transfer procedure.

(14) The receiving (second) carrier substrate is completely printed in a few transfer printing procedures depending on the size of the stamp surface 31 available for the transfer. A maximum of devices can be removed from the (first) carrier substrate, as the donor carrier substrate, and be transferred. In particular, when the first carrier substrate has the same design, various arrangements can be printed on the second carrier substrate, i.e. carrier substrates with various devices, such as CMOS circuits, and with various device arrangements.

(15) FIG. 1 shows a first carrier substrate 10, e.g. in the form of a first semiconductor wafer, with devices 12 to be transferred. The devices 12 have a dimension X.sub.A in a first linear direction, which is referred to as the horizontal direction in the following, and a dimension Y.sub.A in a second linear direction, which is referred to as the vertical direction in the following. Vertically extending intermediate spaces 14 having a width X.sub.B and horizontally extending intermediate spaces 16 having a width Y.sub.B are defined by the requirements of etching free and positioning of the connection elements.

(16) FIG. 2 shows a second carrier substrate 20, e.g. in the form of a second semiconductor wafer, with second devices 22 arranged thereon, e.g. CMOS circuits. The CMOS circuits 22 each contain at least one device 24 positioned therein by transfer printing. The combination of device 22 and device 24 forms a micro-technical device so that the second carrier substrate comprises a plurality of micro-technical devices. After completion of the processing of the micro-technical devices, i.e. the combination of devices 22 and devices 24, they can be separated on the basis of known techniques so that e.g. corresponding circuit chips are obtained which comprise at least one transferred device and, in a further embodiment, a plurality of transferred devices 24, the positions of which are determined by the transfer strategy described above and below.

(17) The devices 24 basically correspond to the devices 12 after transfer thereof from the first carrier substrate 10 to the second carrier substrate 20 according to FIG. 2a, wherein edge areas of the devices 12 to be transferred may be modified due to the release procedure so that different reference numerals are used for the devices prior to release thereof and for the devices after transfer.

(18) FIG. 2a describes an embodiment, in which the pitch R.sub.X in the horizontal direction is equal to the sum of the device dimensions X.sub.A and the width of the intermediate space X.sub.B . . .
R.sub.X=N*(X.sub.A+X.sub.B) when N=1

(19) The pitch R.sub.Y in the vertical direction is an integer multiple of the sum of the device dimensions Y.sub.A and the width of the intermediate space Y.sub.B . . .
R.sub.X=N*(Y.sub.A+Y.sub.B) when N=2

(20) The devices 12 to be transferred in the topmost row of three of FIG. 1 are thus transferred to the topmost row of the devices 24 in FIG. 2a. The devices 12 to be transferred in the third row of three from the top in FIG. 1 are thus transferred to the second row from the top of the devices 24 in FIG. 2a.

(21) FIG. 3 shows the configuration for N=1 in the horizontal direction corresponding to FIG. 2a and a schematic vertical cross-section through a stamp 30 having an elastomeric lower surface 31 or such lower surface parts. Also, a substantial portion or the entire stamp can be made of a resilient, especially elastomeric material, i.e. more than at least the lower surface. It moves from the donor wafer to the receiving wafer and carries the devices 12 which it places onto the receiving wafer 20 after lowering thereof.

(22) During use thereof, it picks up devices 12—which adhere thereto due to adhesion forces—from the first wafer, lifts them off and transfers them. Adhesion of the devices 12 to be transferred and to be placed by printing (via “transfer printing”) to the lower stamp surface 31 (the bottom stamp area) is accomplished by means of a grid R.sub.X in the horizontal direction and by means of grid R.sub.Y in the vertical direction (not visible).

(23) The pitch R.sub.X in the horizontal direction is an integer multiple of the sum of the device dimensions X.sub.A and the width of the intermediate space X.sub.B, wherein N is a positive integer (N=1, 2, 3, . . . , n).
R.sub.X=N*(X.sub.A+X.sub.B) N=1, 2, 3 . . .

(24) The pitch R.sub.Y in the vertical direction (not shown) is an integer multiple of the sum of the device dimensions Y.sub.A and the width of the intermediate space Y.sub.B, wherein N is a positive integer (N=1, 2, 3, . . . , n).
R.sub.Y=N*(Y.sub.A+Y.sub.B) N=1, 2, 3 . . .

(25) The selection of the positions and thus the arrangement of the devices 24 placed by transfer printing (the respective distance between two devices 24 on the second carrier substrate 20) is performed using a dimension R.sub.X in the horizontal direction and using a dimension R.sub.Y in the vertical direction. In this embodiment, the dimension R.sub.X in the horizontal direction is an integer multiple of the sum of the device dimensions X.sub.A and the width of the intermediate space X.sub.B, wherein this sum forms the basic pitch of the two-dimensional grid in the first linearly independent direction, by means of which the devices 12 are arranged on the first carrier substrate 10.

(26) The dimension or position R.sub.X is thus an integer multiple of the basic pitch (X.sub.A+X.sub.B) . . .
R.sub.X=N*(X.sub.A+X.sub.B) N=1, 2, 3 . . .

(27) The dimension or position R.sub.Y in the vertical direction is an N-fold of the sum of the device dimensions Y.sub.A and the width of the intermediate space Y.sub.B in the second linearly independent direction. The dimension or position R.sub.Y is thus an integer multiple of the basic pitch (Y.sub.A+Y.sub.B).
R.sub.Y=N*(Y.sub.A+Y.sub.B) N=1, 2, 3 . . .

(28) The definition of positions for the devices 24 by means of the dimensions R.sub.X and R.sub.Y applies from device 24 to adjacent device 24, wherein the relevant devices may be located within a CMOS circuit 22, but also in adjacent circuits.

(29) In further examples, R.sub.X or R.sub.Y may also start with N=2, while the respective other grid still starts with N=1. Likewise, both grids may start with N=2, i.e. a positive integer “multiple” of the respective basic pitch.

(30) Due to the efficient transfer of the devices 12 (or 24) to second carrier substrates 20, which may have configurations differing from each other, but on which the positions of the transferred devices 24 are each defined by the dimensions R.sub.X and R.sub.Y, which are based on the same basic pitches, e.g. X.sub.A+X.sub.B and Y.sub.A+Y.sub.B, for all second carrier substrates, efficiently combined micro-technical devices can be produced with little effort, as compared to conventional transfer techniques. GaN devices, e.g. high-voltage HEMTs, can be integrated into CMOS structures. Thus, first devices can be transferred from the first carrier substrate to the second carrier substrate (via transfer printing).

(31) Due to the examples of the invention, a transfer printing process can be made considerably more efficient and less expensive. In addition, in contrast to a monolithic integration, also processes producing critical dimensions of less than 0.6 μm can be used with integrated GaN devices.

(32) Conversely, also CMOS devices 12 can be lifted off, transferred and printed on the second carrier substrate. Also in this case, first devices are transferred from the first carrier substrate to the second carrier substrate (via transfer printing).

(33) Particularly preferably, GaN devices are transferred and printed on or in CMOS circuits via micro-transfer printing. Likewise, CMOS circuits or elements thereof can be printed on or between GaN devices.