Single-stage multi-input buck type low-frequency link's inverter with an external parallel-timesharing select switch

Abstract

A circuit structure of a voltage type single-stage multi-input low-frequency link inverter with an external parallel-timesharing select switch is formed by connecting a plurality of input filters connected to ground and a common output low-frequency isolation voltage-transformation filter circuit through a multi-input single-output high-frequency inverter circuit. Each input end of the multi-input single-output high-frequency inverter circuit is connected to an output end of each of the input filters in a manner of one-to-one correspondence. An output end of the multi-output single-input high-frequency inverter circuit and the output low-frequency isolation voltage-transformation filter circuit are connected. The multi-input single-output high-frequency inverter circuit includes an external multi-path parallel-timesharing select four-quadrant power switch circuit and a bidirectional power flow single-input single-output high-frequency inverter circuit successively connected in cascade.

Claims

1. A single-stage multi-input buck type low-frequency link's inverter with an external parallel-timesharing select switch, comprising: a plurality of input filters connected to a ground, a common output low-frequency isolation voltage-transformation filter circuit and a multi-input single-output high-frequency inverter circuit, wherein the plurality of input filters and the common output low-frequency isolation voltage-transformation filter circuit are connected by the multi-input single-output high-frequency inverter circuit; each input end of the multi-input single-output high-frequency inverter circuit is connected to an output end of each input filter in a manner of one-to-one correspondence; an output end of the multi-input single-output high-frequency inverter circuit is connected to an input end of a low-frequency transformer of the output low-frequency isolation voltage-transformation filter circuit, or an input end of an output filter inductor, wherein the input end of an output filter inductor is not connected to the low-frequency transformer, or the input end of an output filter; the multi-input single-output high-frequency inverter circuit comprises an external multi-path parallel-timesharing select four-quadrant power switch circuit and a bidirectional power flow single-input single-output high-frequency inverter circuit successively connected in cascade; the multi-input single-output high-frequency inverter circuit is equivalent to the bidirectional power flow single-input single-output high-frequency inverter circuit; each path of the external multi-path parallel-timesharing select four-quadrant power switch circuit comprises only one four-quadrant power switch and output ends of all paths of the external multi-path parallel-timesharing select four-quadrant power switch circuit are connected in parallel; the output low-frequency isolation voltage-transformation filter circuit comprises the low-frequency transformer and the output filter connected successively in cascade, or comprises the output filter inductor, the low-frequency transformer and an output filter capacitor connected successively in cascade, or comprises the output filter and the low-frequency transformer connected successively in cascade; the multi-input single-output high-frequency inverter circuit of the single-stage multi-input buck type low-frequency link's inverter modulates the multi-path input DC voltage source U.sub.i1, U.sub.i2, . . . , U.sub.im into a bipolar two-state multi-level SPWM voltage wave or a unipolar three-state multi-level SPWM voltage wave, wherein an amplitude of the bipolar two-state multi-level SPWM voltage wave or the unipolar three-state multi-level SPWM voltage wave varies with variation of the input DC voltage; the bipolar two-state multi-level SPWM voltage wave or the unipolar three-state multi-level SPWM voltage wave passes through the low-frequency transformer and an output LC filter, or through the output filter inductor, the low-frequency transformer, and the output filter capacitor, or through the output filter inductor, the output filter capacitor, and the low-frequency transformer, to obtain a high-quality sinusoidal AC voltage or sinusoidal AC current on a single-phase AC passive load or a single-phase AC power grid, wherein n represents a path number of a plurality of input sources and n is a natural number more than 1; a circuit topology of the single-stage multi-input buck type low-frequency link's inverter comprises a push-pull circuit, a push-pull forward circuit, a half-bridge circuit, or a full-bridge circuit, wherein each of the push-pull circuit, the push-pull forward circuit, and the half-bridge circuit comprises n four-quadrant high-frequency power switches for withstanding bidirectional voltage stress and bidirectional current stress and two two-quadrant high-frequency power switches for withstanding unidirectional voltage stress and the bidirectional current stress, the full-bridge circuit comprises n four-quadrant high-frequency power switches for withstanding bidirectional voltage stress and bidirectional current stress and four two-quadrant high-frequency power switches for withstanding unidirectional voltage stress and the bidirectional current stress; an independent power supply system formed by the single-stage multi-input buck type low-frequency link's inverter employs an energy management control strategy of an instantaneous output voltage and input current feedback bipolar SPWM or unipolar SPWM master-slave power distribution, wherein output powers of 1.sup.nd, 2.sup.nd, . . . n−1.sup.th paths of input sources are fixed and a shortage of power needed by a load is supplied by the n.sup.th path of input sources; a grid-tied power generating system formed by the single-stage multi-input buck type low-frequency link's inverter employs an energy management control strategy of an input current instantaneous feedback bipolar SPWM or unipolar SPWM maximum power output of the 1.sup.st, 2.sup.nd, . . . n.sup.th paths of input sources; the single-stage multi-input buck type low-frequency link's inverter converts a plurality of connected-to-ground and unstable input DC voltages into a stable high-quality output AC needed by the load through a single-stage low-frequency isolation; the plurality of input sources supply electric power to the load simultaneously in a high-frequency switching period, or the plurality of input sources supply the electric power to the load in a time-sharing manner in the high-frequency switching period.

2. The single-stage multi-input buck type low-frequency link's inverter with the external parallel-timesharing select switch according to claim 1, wherein an output end of the single-stage multi-input buck type low-frequency link's inverter with the external parallel-timesharing select switch is connected in parallel to a single-stage isolation bidirectional charge/discharge converter of energy storage equipment to form the independent power supply system with a stable output voltage, and the independent power supply system is configured to make full use of energy of the plurality of input sources; the single-stage isolation bidirectional charge/discharge converter comprises the input filter, a high-frequency inverter, a high-frequency transformer, a cycloconverter and an output filter successively connected in cascade; the cycloconverter comprises a four-quadrant power switch for withstanding bidirectional voltage stress and bidirectional electric current stress; the independent power supply system employs the energy management control strategy of the maximum power output of a single-stage multi-input high-frequency link's inverter output voltage independent control loop circuit a plurality of input sources work in a maximum power outputting mode; a magnitude and a direction of a power flow of the single-stage isolation bidirectional charge/discharge converter are controlled by comparing a load power with a sum of maximum powers of the plurality of input sources in real time, to realize a smooth and seamless switch between a case of stabilizing a system output voltage and a case of charging/discharging of the energy storage equipment when a load power is larger than a sum of maximum powers of the plurality of input sources, the independent power supply system works in a second power supply mode where the energy storage equipment supplies the shortage of power for the load through the single-stage isolation bidirectional charge/discharge converter; a third power supply mode where the energy equipment individually supplies the load with the electric power is an extreme case of the second power supply mode; when the load power is lower than the sum of the maximum powers of the plurality of the input sources, the independent power supply system works in a first power supply mode where the rest of energy output by the plurality of input sources is supplied to charge the energy storage equipment through the single-stage isolation bidirectional charge/discharge converter; a current of the output filter inductor of the single-stage multi-input buck type low-frequency link's inverter and the output voltage have the same frequency and the same phase, and output an active power; the single-stage isolation bidirectional charge/discharge converter is controlled through an SPWM signal generated by crossing the error amplified signal of the output voltage and the voltage reference with the high-frequency carrier wave, and there is a phase difference θ between the current of the output filter inductor of the single-stage isolation bidirectional charge/discharge converter and the output voltage, wherein different phase differences θ are indicative of outputting the active power of different magnitudes and directions; when the load power is equal to the sum of the maximum powers of the plurality of the input sources, θ=90° and the active power output by the single-stage isolation bidirectional charge/discharge converter are zero; when the load power is larger than the sum of the maximum powers of the plurality of the input sources, the output voltage decreases, θ<90°, the single-stage isolation bidirectional charge/discharge converter outputs the active power, and the energy storage equipment supplies the shortage of power needed by the load; when the load power is smaller than the sum of the maximum powers of the plurality of the input sources, the output voltage increases, θ>90°, the single-stage isolation bidirectional charge/discharge converter outputs a minus active power, and the rest of the power of the plurality of input sources is supplied to charge the energy storage equipment.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 shows a two-stage new energy source distributed power supply system with output ends of a plurality of traditional unidirectional DC converter connected in parallel.

(2) FIG. 2 shows a two-stage new energy source distributed power supply system with output ends of a plurality of traditional unidirectional DC converter connected in series.

(3) FIG. 3 is a schematic block diagram of a novel single-stage multi-input inverter.

(4) FIG. 4 is a schematic block diagram of a single-stage multi-input buck type low-frequency link's inverter with an external parallel-timesharing select switch.

(5) FIG. 5 is a structural diagram showing a circuit of the single-stage multi-input buck type low-frequency link's inverter with an external parallel-timesharing select switch.

(6) FIG. 6 is a schematic oscillogram showing a steady state of a bipolar SPWM (sinusoidal pulse width modulation) control the single-stage multi-input buck type low-frequency link's inverter with an external parallel-timesharing select switch.

(7) FIG. 7 is a schematic oscillogram showing a steady state of a unipolar SPWM control of the single-stage multi-input buck type low-frequency link's inverter with an external parallel-timesharing select switch.

(8) FIG. 8 is a schematic diagram of a push-pull circuit of the topology embodiment 1 of the single-stage multi-input buck type low-frequency link's inverter with an external parallel-timesharing select switch.

(9) FIG. 9 is a schematic diagram of a push-pull forward circuit of the topology embodiment 2 of the single-stage multi-input buck type low-frequency link's inverter with an external parallel-timesharing select switch.

(10) FIG. 10 is a schematic diagram I of a half-bridge circuit of the topology embodiment 3 of the single-stage multi-input buck type low-frequency link's inverter with an external parallel-timesharing select switch.

(11) FIG. 11 is a schematic diagram II of the half-bridge circuit of the topology embodiment 4 of the single-stage multi-input buck type low-frequency link's inverter with an external parallel-timesharing select switch.

(12) FIG. 12 is a schematic diagram III of the half-bridge circuit of the topology embodiment 5 of the single-stage multi-input buck type low-frequency link's inverter with an external parallel-timesharing select switch.

(13) FIG. 13 is a schematic diagram I of a full-bridge circuit of the topology embodiment 6 of the single-stage multi-input buck type low-frequency link's inverter with an external parallel-timesharing select switch.

(14) FIG. 14 is a schematic diagram II a full-bridge circuit of the topology embodiment 7 of the single-stage multi-input buck type low-frequency link's inverter with an external parallel-timesharing select switch.

(15) FIG. 15 is a schematic diagram III a full-bridge circuit of the topology embodiment 8 of the single-stage multi-input buck type low-frequency link's inverter with an external parallel-timesharing select switch.

(16) FIG. 16 is a block diagram of energy management control showing an instantaneous output voltage and input current feedback bipolar SPWM master-slave power distribution of the single-stage multi-input buck type low-frequency link's inverter with an external parallel-timesharing select switch.

(17) FIG. 17 is a schematic oscillogram of the energy management control showing the instantaneous output voltage and input current feedback bipolar SPWM master-slave power distribution of the single-stage multi-input buck type low-frequency link's inverter with an external parallel-timesharing select switch.

(18) FIG. 18 is a block diagram of energy management control showing an instantaneous output voltage and input current feedback unipolar SPWM master-slave power distribution of the single-stage multi-input buck type low-frequency link's inverter with an external parallel-timesharing select switch.

(19) FIG. 19 is a schematic oscillogram of the energy management control showing the instantaneous output voltage and input current feedback unipolar SPWM master-slave power distribution of the single-stage multi-input buck type low-frequency link's inverter with an external parallel-timesharing select switch.

(20) FIG. 20 is a diagram of the single-stage multi-input buck type low-frequency link's independent power supply system with an external parallel-timesharing select switch, having the output end connected in parallel to a single-stage isolation bidirectional charge/discharge converter.

(21) FIG. 21 shows an energy management control strategy of a maximum power output of an output voltage independent control loop circuit having the single-stage isolation bidirectional charge/discharge converter.

(22) FIG. 22 is an oscillogram of an output voltage u.sub.o of the independent power supply system and electric currents hi and iii′ of an output filter inductor.

DETAILED DESCRIPTION OF THE EMBODIMENTS

(23) The technical solution of the present disclosure will be further described hereinafter with reference to the drawings and the embodiments of the specification.

(24) A single-stage multi-input buck type low-frequency link's inverter with an external parallel-timesharing select switch is formed by connecting a plurality of connected-to-ground input filters and a common output low-frequency isolation voltage-transformation filter circuit through a multi-input single-output high-frequency inverter circuit. Each input end of the multi-input single-output high-frequency inverter circuit is connected to an output end of each of the input filters in a manner of one-to-one correspondence. An output end of the multi-input single-output high-frequency inverter circuit is connected to an input end of a low-frequency transformer of the output low-frequency isolation voltage-transformation filter circuit, or an input end of an output filter inductor wherein the input end of the output filter inductor is not connected to the low-frequency transformer, or an input end of the output filter. The multi-input single-output high-frequency inverter circuit includes an external multi-path parallel-timesharing select four-quadrant power switch circuit and a bidirectional power flow single-input single-output high-frequency inverter circuit which are successively connected in cascade. The multi-input single-output high-frequency inverter circuit is equivalent to one bidirectional power flow single-input single-output high-frequency inverter circuit at any time. Each path of the external multi-path parallel-timesharing select four-quadrant power switch circuit includes only one four-quadrant power switch and output ends of all paths are connected to each other in parallel. The output low-frequency isolation voltage-transformation filter circuit includes the low-frequency transformer and the output filter, or includes the output filter inductor, the low-frequency transformer, and an output filter capacitor, or includes the output filter and the low-frequency transformer connected successively in cascade.

(25) A schematic block diagram, a circuit structure of the single-stage multi-input buck type low-frequency link's inverter with an external parallel-timesharing select switch, a steady-state schematic oscillogram of a bipolar SPWM control inverter and a unipolar SPWM control inverter are respectively shown in FIGS. 4, 5, 6, and 7. In FIGS. 4, 5, 6, and 7, U.sub.i1, U.sub.i2, . . . , U.sub.in are n (n is a natural number larger than 1) paths of input DC voltage sources. Z.sub.L is a single-phase output AC load (including a single-phase output DC passive load and a single-phase DC power grid load) and u.sub.0 and i.sub.0 are respectively a single-phase output alternating voltage and an alternating current. An n-input single-output high-frequency inverter circuit is composed of an external multi-path parallel-timesharing select four-quadrant power switch circuit and a bidirectional power flow single-input single-output high-frequency inverter circuit which are successively connected in cascade, wherein the external multi-path parallel-timesharing select four-quadrant power switch circuit is composed of n four-quadrant high-frequency power switches capable of withstanding bidirectional voltage stress and bidirectional current stress. The bidirectional power flow single-input single-output high-frequency inverter circuit is composed of a plurality of two-quadrant high-frequency power switches capable of withstanding a unidirectional voltage stress and a bidirectional current stress, which may employ power devices such as MOSFET, IGBT, GTR. In the dashed block (the ‘1’ end and ‘1′’ end are connecting ends), the output low-frequency isolation voltage-transformation filter circuit is composed of the low-frequency transformer and the output filter successively connected in cascade, or is composed of the output filter inductor, the low-frequency transformer, and the output filter capacitor (a primary-side leakage inductance of the low-frequency transformer can be absorbed and utilized by the output filter inductor or completely used to function as an output filter inductor) successively connected in cascade, or is composed of the output filter inductor, the output filter capacitor, and the low-frequency transformer successively connected in cascade. Due to space limitations, the drawings only show a circuit diagram of a LC output filter or the output filter capacitor applicable to a passive AC load, and do not show a circuit diagram of a LCL output filter applicable to the AC power grid load, or the output filter capacitor added with the output filter inductor. The n-path input filter may be the LC filter (which includes the filter inductors L.sub.i1, L.sub.i2, . . . , L.sub.in in the dashed block) or the filter capacitor (which does not include the filter inductors L.sub.i1, L.sub.i2, . . . , L.sub.in in the dashed block). When the LC filter is employed, n paths of input direct currents will be smoother. The n-input single-output high-frequency inverter circuit modulates the n-path input DC voltage source U.sub.i1, U.sub.i2, . . . , U.sub.in into a bipolar two-state or a unipolar three-state multi-level SPWM voltage wave, an amplitude of which varies with variation of the input DC voltage. The voltage wave passes through the low-frequency transformer T and the output filter L.sub.f-C.sub.f, or through the output filter inductor L.sub.f, the low-frequency transformer T, and the output filter capacitor C.sub.f, or through the output filter inductor L.sub.f, the output filter capacitor C.sub.f, and the low-frequency transformer T, to obtain a high-quality sinusoidal AC voltage u.sub.o or sinusoidal AC current i.sub.o on the single-phase AC passive load or the single-phase AC power grid. There are n input pulse currents of the n-input single-output high-frequency inverter circuit which pass through the input filters L.sub.i1-C.sub.i1, L.sub.i2-C.sub.i2, . . . , L.sub.in-C.sub.in or C.sub.i1, C.sub.i2, . . . , C.sub.in. Then smooth input direct currents I.sub.i1, I.sub.i2, . . . , I.sub.in are obtained in the n paths of input DC power supplies U.sub.i1, U.sub.i2, . . . , U.sub.in. It should be further noted that, when the output low-frequency isolation voltage-transformation filter circuit is composed of the low-frequency transformer and the output filter which are successively connected in cascade, amplitudes of the bipolar two-state and unipolar three-state multi-level SPWM voltage wave u.sub.AB in a +1 state are U.sub.i1N.sub.2/N.sub.1, U.sub.i2N.sub.2/N.sub.1, . . . , U.sub.inN.sub.2/N.sub.1, while an amplitude thereof in a +1 state is U.sub.inN.sub.2/N.sub.1 (it is designed for energy on an AC side to be fed back only through the n.sup.th path of the input source U.sub.in. Alternatively, energy on the AC side may be fed back through any other path of the input source.). When the output low-frequency isolation voltage-transformation filter circuit is composed of the output filter inductor, the low-frequency transformer, and the output filter capacitor that are successively connected in cascade; or is composed of the output filter inductor, the output filter capacitor and the low-frequency transformer that are successively connected in cascade, amplitudes of the bipolar two-state and unipolar three-state multi-level SPWM voltage wave u.sub.AB in the +1 state are U.sub.i1, U.sub.i2, . . . , U.sub.in, while an amplitude thereof in the −1 state is U.sub.in (it is designed for the energy on the AC side to be fed back only through the n.sup.th path of the input source Um. Alternatively, the energy on the AC side may be fed back through any other path of the input source.)

(26) The single-stage multi-input buck type low-frequency link's inverter with an external parallel-timesharing select switch is a buck inverter, which has n input sources connected in parallel and supplying the electric power in a time-sharing manner. Assuming amplitudes of output signals I.sub.1e, I.sub.2e, . . . , I.sub.(n-1)e of n−1 input source error amplifiers and an output signal u.sub.e of an output voltage error amplifier to be hem, I.sub.1em, I.sub.2em, I.sub.(n-1)em, U.sub.em, and an amplitude of a sawtooth carrier signal u.sub.c to be U.sub.cm. Corresponding modulation degrees are m.sub.1=I.sub.1em/U.sub.cm, m.sub.2=I.sub.2em/U.sub.cm, . . . , m.sub.n=U.sub.em/U.sub.cm, wherein 0≤m.sub.1, m.sub.2, . . . , m.sub.n≤1 and m.sub.1<m.sub.2<, . . . , <m.sub.n. The principle of the inverter is that a plurality of voltage type single-input inverters are superposed on the voltage of the output end, namely a relationship between the output voltage u.sub.o, the input DC voltage (U.sub.i1, U.sub.i2, . . . , U.sub.in), a turn ratio N.sub.2/N.sub.1 of the low-frequency transformer, and the modulation degrees (m.sub.1, m.sub.2, . . . , m.sub.n) can be expressed as u.sub.o=[(m.sub.1U.sub.i1+(m.sub.2−m.sub.1)U.sub.i2+ . . . +(m.sub.n−m.sub.n-1)U.sub.in)]N.sub.2/N.sub.1 (when the inverter is controlled by a unipolar SPWM) or u.sub.o=[(2m.sub.1−1)U.sub.i1+(2m.sub.2−2m.sub.1−1)U.sub.i2+ . . . +(2m.sub.a−2m.sub.n-1−1)U.sub.in)]N.sub.2/N.sub.1 (when the inverter is controlled by a bipolar SPWM). If proper modulation degrees m.sub.1, m.sub.2, . . . , m.sub.n and the turn ratio N.sub.2/N.sub.1 of the low-frequency transformer are given, u.sub.o may be larger than, equal to or lower than a sum of the input DC voltages U.sub.i1+U.sub.i2+ . . . +U.sub.in. The low-frequency transformer of the inverter not only enhances the safety, the reliability and the electromagnetic compatibility of the inverter in the course of operation, but also importantly matches the output voltage and the input voltage, thereby realizing the technical effect that the output voltage of the inverter may be larger than, equal to, or lower than the sum of the input DC voltages U.sub.i1+U.sub.i2+ . . . +U.sub.in, and broadens the field of application. Because 0<m.sub.1+(m.sub.2−m.sub.1)+ . . . +(m.sub.a−m.sub.n-1)<1 (when the inverter is controlled by the unipolar SPWM) and 0.5<m.sub.1+(m.sub.2−m.sub.1)+ . . . +(m.sub.n−m.sub.n-1)<1 (when the inverter is controlled by the bi-polar SPWM), u.sub.o<(U.sub.i1+U.sub.i2+ . . . +U.sub.in)N.sub.2/N.sub.1, namely the output voltage u.sub.o is always lower than a sum of products (U.sub.i1+U.sub.i2+ . . . +U.sub.in)N.sub.2/N.sub.1 of the input DC voltages (U.sub.i1, U.sub.i2, . . . , U.sub.in) and the turn ratio N.sub.2/N.sub.1 of the low-frequency transformer. Since the inverter has a single-stage circuit structure, a working frequency of the transformer of the inverter is equal to a frequency of the output voltage and the multi-path parallel-timesharing select four-quadrant power switch is located outside the high-frequency inverter circuit. These kind of inverters are referred to as a single-stage multi-input buck type (voltage type) low-frequency link's inverter with an external parallel-timesharing select switch. The n input sources of the inverter can supply electric power to the output AC load in a high-frequency switch period only in a time-sharing manner, wherein the modulation degrees may be equal (i.e. m.sub.1=m.sub.2= . . . =m.sub.n), or not equal (i.e. m.sub.1≠m.sub.2≠ . . . ≠m.sub.n).

(27) Since the single-stage multi-input buck type low-frequency link's inverter with an external parallel-timesharing select switch shares one bidirectional power flow single-input single-output high-frequency inverter circuit and one output low-frequency isolation voltage-transformation filter circuit, the single-stage multi-input buck type low-frequency link's inverter with an external parallel-timesharing select switch is essentially different from the circuit structure of the traditional multi-input inverter composed of the DC convertor and the inverter connected in two-stage cascade. Therefore, the inverter of the present disclosure is novel and creative. Moreover, the inverter has the following advantages: low-frequency isolation is performed on the output and the input; the multi-input power supply supplies electric power in a time-sharing manner; the circuit topology is simple; a single-stage power conversion is performed; a conversion efficiency of the single-stage power conversion is high (that means less energy losses); the output voltage can be flexibly configured; the output voltage ripple is small; the output capability is large; the cost is low; and the prospect for applications is vast. Thus, the inverter of the present disclosure is an ideal energy-saving and consumption-reducing single-stage multi-input inverter and is of greater value in the present era of an energy-saving and conservation-minded society that we strongly advocate.

(28) Embodiments of the topology family of the single-stage multi-input buck type low-frequency link's inverter with an external parallel-timesharing select switch are shown in FIGS. 8, 9, 10, 11, 12, 13, 14, and 15. As the circuit is shown in FIGS. 8-15, the external multi-path parallel-timesharing select four-quadrant power switch circuit is composed of n four-quadrant high-frequency power switches capable of withstanding the bidirectional voltage stress and the bidirectional current stress, The bidirectional power flow single-input single-output high-frequency inverter circuit is composed of a plurality of two-quadrant high-frequency power switches capable of withstanding the unidirectional voltage stress and the unidirectional current stress. As shown in FIGS. 8, 9, 10, 11, and 12, the push-pull circuit, the push-pull forward circuit, and the half-bridge circuit all include two two-quadrant high-frequency power switches. As shown in FIGS. 13, 14 and 15, the full-bridge circuit is composed of four two-quadrant high-frequency power switches. It should be further noted that, the circuits shown in FIGS. 8, 9, 10, 11, 12, 13, 14, and 15 show the case when the input inverter is the LC filter (as shown in FIGS. 10, 11, and 12, the input filter capacitors of the half-bridge circuit are two bridge arm capacitors C.sub.1 and C.sub.2), and fails to show a circuit in the case when the input filter is the capacitor filter. The push-pull forward circuit shown in FIG. 9 and the half-bridge circuits shown in FIGS. 10, 11, and 12 are merely applicable to the case when the voltages of n input power supplies are equal. The output low-frequency isolation voltage-transformation filter circuits of the half-bridge circuits I, II, III shown in FIGS. 10, 11, and 12 respectively are composed of the low-frequency transformer and the output filter which are successively connected in cascade, the output filter inductor and the low-frequency transformer which are successively connected in cascade and the output filter capacitor, the output filter and the low-frequency transformer which are successively connected in cascade. The output low-frequency isolation voltage-transformation filter circuits of the full-bridge circuits I, II, III shown in FIGS. 13, 14, and 15 respectively are composed of the low-frequency transformer and the output filter which are successively connected in cascade, the output filter inductor and the low-frequency transformer which are successively connected in cascade and the output filter capacitor, the output filter and the low-frequency transformer which are successively connected in cascade. The power switch voltage stresses of four topology embodiments of the single-stage multi-input buck type low-frequency link's inverter with an external parallel-timesharing select switch are shown in Table 1. In Table 1, U.sub.imax=max(U.sub.i1, U.sub.i2, . . . , U.sub.in), where N=1, 2, . . . , n. The push-pull circuit, and the push-pull forward circuit are applicable to a high-power low-voltage input inverter. The half-bridge circuit is applicable to a medium-power high-voltage input inverter. The full-bridge circuit is applicable a high-power high-voltage input inverter. The circuit topology family is applicable to convert a plurality of connected-to-ground and unstable input DC voltages into a kind of high-quality output AC with a stable voltage, which can be used to achieve a novel, fine-property, a promising single-stage multi-new energy source distributed power supply system, a plurality of input sources, such as photovoltaic cells 40-60 VDC/220V50HzAC or 115V400HzAC, 10 kw proton exchange membrane fuel cells 85-120V/220V50HzAC or 115V400HzAC, small and medium-sized household wind power generators 24-36-48 VDC/220V50HzAC or 115V400HzAC, large-sized wind power generators 510 VDC/220V50HzAC or 115V400HzAC and are used to supply electric power for the AC load or the AC power grid.

(29) TABLE-US-00001 TABLE 1 The power switch voltage stresses of four topology embodiments of the single-stage multi-input buck type low-frequency link's inverter with an external parallel-timesharing select switch. Circuit Voltage Power topology S.sub.s1, S.sub.s2, . . . , S.sub.sn S.sub.1, S.sub.2 S.sub.3, S.sub.4 Push-pull max|U.sub.iN − U.sub.i1|, 2U.sub.imax / circuit max|U.sub.iN − Push-pull forward U.sub.i2|, . . . , 2U.sub.imax / circuit max|U.sub.iN − U.sub.in| Half-bridge U.sub.imax / circuit Full- Bipolar U.sub.imax bridge SPWM circuit Unipolar U.sub.i1 − (U.sub.i1 + SPWM U.sub.i2 + . . . + U.sub.in)/2n, U.sub.i2 − (U.sub.i1 + U.sub.i2 + . . . + U.sub.in)/ 2n, . . . , U.sub.in − (U.sub.i1 + U.sub.i2 + . . . + U.sub.in)/2n

(30) The energy management control strategy is crucial to a power supply system combined with a plurality of new energy sources. Due to a plurality of input sources and corresponding power switch units, a plurality of duty ratios are required/needed to be controlled, namely there are a plurality of control degrees of freedom, which make it possible for energy management of the plurality of new energy sources. The proposed energy management control strategies of the inverter should simultaneously have three functions which are energy management of the input sources, maximum power point tracking (MDPT) of new energy source generating equipment including the photovoltaic cell and a wind power generator, and controlling of the output voltage (current). In some cases, it is further required to charge/discharge control of the accumulator and to have a system with smooth and seamless switching between different power supplying modes. The proposed inverter employs two different energy management modes. The energy management mode I, is a master-slave distribution method, wherein the power needed by the load is supplied as much as possible by the 1.sup.st, 2.sup.nd, . . . n−1.sup.th paths of the input sources of a main power supply equipment. When the input electric currents of the 1.sup.st, 2.sup.nd, . . . n−1.sup.th paths of the input sources are determined, the input powers of the 1.sup.st, 2.sup.nd, . . . n−1.sup.th paths of the input sources are determined accordingly. A shortage of the power needed by the load is supplied by the n.sup.th path of the input source of the power supply equipment, without the addition of accumulator power storage equipment. The energy management mode II, is a maximum power inputting method, wherein the 1.sup.st, 2.sup.nd, . . . , n.sup.th paths of the input sources supply the maximum power to the load, which eliminates the accumulator power storage equipment and satisfies requirements of the grid-tied power generating system to make full use of the energy. One output end is connected in parallel to an accumulator charge/discharge device to realize the stability of the output voltage of the independent power supply system. When n paths of the input voltages of the new energy sources are all determined, the input powers of the 1.sup.st, 2.sup.nd, . . . n.sup.th paths of the input sources can be controlled by controlling the input currents of the 1.sup.st, 2.sup.nd, . . . n.sup.th paths of the input sources.

(31) The single-stage multi-input buck type low-frequency link's inverter with an external parallel-timesharing select switch employs the energy management control strategy of an instantaneous output voltage and input current feedback bipolar SPWM or unipolar SPWM master-slave power distribution to form the independent power supply system, or employs the energy management control strategy of an input current instantaneous feedback bipolar SPWM or unipolar SPWM maximum power output to form the grid-tied power generating system. The energy management control block diagrams and control schematic waveforms of an output voltage and the input current feedback bipolar SPWM or unipolar SPWM master-slave power distribution when the powers of the 1.sup.st, 2.sup.nd, . . . n−1.sup.th paths of input energy sources are fixed and the short power needed by the load is supplied by the n.sup.th path of input sources are respectively shown in FIGS. 16, 17, 18, and 19. The 1.sup.st, 2.sup.nd, . . . n−1.sup.th paths of input current feedback signals, I.sub.i1f, I.sub.i2f, . . . , I.sub.i(n-1)f of the inverter and reference current signals I.sub.i1r, I.sub.i2r, . . . , I.sub.i(n-1)r obtained by computing the 1.sup.st, 2.sup.nd, . . . n−1.sup.th paths of input sources through a maximum power point are compared and magnified by a proportional-integral controller. The magnified error signals I.sub.1e, I.sub.2e, . . . , I.sub.(n-1)e are respectively multiplies by the sinusoidal synchronizing signals and then pass through absolute value circuits 1, 2, . . . , n−1 to obtain |i.sub.1e|, |i.sub.2e|, . . . , |i.sub.(n-1)e|. An output voltage feedback signal u.sub.of of the inverter and a reference sinusoidal voltage u.sub.r are compared and magnified by the proportional-integral controller. The magnified error signal u.sub.e passes through the absolute value circuit n to obtain |u.sub.1e|. The |i.sub.1e|, |i.sub.2e|, . . . , |.sub.(n-1)e|, and |u.sub.e| respectively cross with a sawtooth carrier wave u.sub.c, while it is considered to output the voltage gating signal and pass through a proper combinational logic circuit to obtain the power switch control signals u.sub.gss1, u.sub.gss2, . . . , u.sub.gssn, u.sub.gs1, u.sub.gs2, u.sub.gs3, u.sub.gs4. The 1.sup.st, 2.sup.nd, . . . n−1.sup.th paths of current regulators and an n.sup.th voltage regulator work respectively and individually. The 1.sup.st, 2.sup.nd, . . . n−1.sup.th paths of current regulators are used to realize the maximum power outputting of the 1.sup.st, 2.sup.nd, . . . n−1.sup.th paths of the input sources. The n.sup.th voltage regulator is used to realize the stability of the inverter output voltage. The n paths of input sources collectively supply electric power to the load. When the input voltage or the load varies, the error voltage signal |u.sub.e| and the error current signals |i.sub.1e|, |i.sub.2e|, . . . , |i.sub.(n-1)e| are altered by adjusting a reference voltage u.sub.r and the current references i.sub.i1r, i.sub.i2r, . . . i.sub.i(n-1)r, or adjusting a feedback voltage u.sub.of and feedback currents i.sub.i1f, i.sub.i2f, . . . , i.sub.i(n-1)f, thereby altering the modulation degrees m.sub.1, m.sub.2, . . . , m.sub.n. Therefore, the output voltages and the output currents (output powers) of the inverter can be adjusted and stabilized.

(32) As shown in FIGS. 16-19, the n.sup.th path of input sources is designed as an input current feedback to control the input current to form the energy management control strategy of the input current instantaneous feedback bipolar, or the unipolar SPWM maximum power output. The current reference signals I.sub.i1r, I.sub.i2r, . . . , I.sub.inr obtained by respectively performing MPPT on the 1.sup.st, 2.sup.nd, . . . n.sup.th paths of the input current feedback signals of the inverter I.sub.i1f, I.sub.i2f, . . . , I.sub.inf along with the 1.sup.st, 2.sup.nd, . . . n.sup.th paths of input source are compared and amplified by a PI controller. The error amplified signals I.sub.1e, I.sub.2e, . . . , I.sub.ne are respectively multiplies by the sinusoidal synchronizing signal and pass through the absolute value circuit 1, 2, . . . , n to obtain |i.sub.1e|, |i.sub.2e|, . . . , |i.sub.ne|. The |.sub.ie|, |i.sub.2e|, . . . , |i.sub.ne| respectively cross with the sawtooth carrier wave, while it is considered to output the voltage gating signal, and then pass through the proper combinational logic circuits to obtain the power switch control signals u.sub.gss1, u.sub.gss2, . . . , u.sub.gssn, u.sub.gs1, u.sub.gs2, u.sub.gs3, u.sub.gs4.

(33) As shown in FIG. 17 and FIG. 19, the bipolar and the unipolar SPWM control principal waveforms indicate the high-frequency switching period Ts, the turn-on time T.sub.on1, T.sub.on2, . . . , T.sub.onn of the 1.sup.st, 2.sup.nd, . . . n.sup.th paths of the input sources in a certain high-frequency switching period Ts, and the total turn-on time T.sub.on=T.sub.on1+T.sub.on2+ . . . +T.sub.onn. The total turn-on time T.sub.on varies sinusoidally in an output voltage period. Additionally, as for the H-bridge circuits I, II, and III shown in FIGS. 10, 11, and 12, a half of each input AC voltage value (U.sub.i1/2, U.sub.i2/2, . . . , U.sub.in/2) should be substituted into an equation of a voltage transfer ratio for calculation.

(34) In order to form the independent power supply system capable of making full use of energy of the multi-input sources, a plurality of input sources should work in the maximum power input mode and needs to be equipped with the energy storage equipment to realize the stability of the output voltage, namely the output end of the inverter is connected in parallel to one single-stage isolation bidirectional charge/discharge converter, as shown in FIG. 20. The single-stage isolation bidirectional charge/discharge converter is composed of the input inverter (L.sub.i and C.sub.i, or C.sub.i), the high-frequency inverter, the high-frequency transformer, the cycloconverter, and the output filter, which are successively connected in cascade. The cycloconverter is composed of the four-quadrant high-frequency power switch capable of withstanding the bidirectional voltage stress and the bidirectional current stress. When the single-stage isolation bidirectional charge/discharge converter is performing a forward energy transfer (discharging of the energy storage equipment) and a backward energy transfer (charging of the energy storage equipment), the single-stage isolation bidirectional charge/discharge converter is respectively equivalent to a single-stage high-frequency link DC-AC converter or a single-stage high-frequency link AC-DC converter.

(35) The independent power supply system employs the energy management control strategy of the maximum power output of a single-stage multi-input high-frequency link's inverter output voltage independent control loop circuit. When a load power expressed as P.sub.o=U.sub.oI.sub.o is larger than a sum of maximum powers P.sub.1max+P.sub.2max+ . . . +P.sub.nmax of a plurality of the input sources, the energy storage equipment such as the accumulator and the supercapacitor supply the shortage of the power for the load through the single-stage isolation bidirectional charge/discharge converter (i.e. in power supply mode II, or the energy equipment individually supplies the load with the electric power, i.e. power supply mode III, which is an extreme case of the power supply mode II.). When a load power P.sub.o=U.sub.oI.sub.o is lower than the sum of the maximum powers P.sub.1max+P.sub.2max++P.sub.nmax of a plurality of the input sources, the rest of the energy output by the plurality of input sources is supplied to charge the energy storage equipment through the single-stage isolation bidirectional charge/discharge converter (i.e. the power supply mode I.). Taking a resistive load as an example, a power flow direction control of the single-stage isolation bidirectional charge/discharge converter is illustrated hereinafter and is shown in FIG. 22. As for the output filter capacitor C.sub.f, C.sub.f′ and the load Z.sub.L, a parallel connection of the output end of the single-stage multi-input buck type low-frequency link's inverter with an external parallel-timesharing select switch and the output end of single-stage isolation bidirectional charge/discharge converter is equivalent to a parallel superposition of two electric current sources. As the energy management control strategy shown in FIG. 21, it can be known that an output filter inductor electric current i.sub.Lf of the single-stage multi-input buck type low-frequency link's inverter with an external parallel-timesharing select switch and the output voltage u.sub.o have the same frequency and the same phase, and output the active power. The charge/discharge converter is controlled through an SPWM signal generated by crossing the error amplified signal u.sub.oe of the output voltage u.sub.o and the voltage reference u.sub.oref with the high-frequency carrier wave. There is a phase difference θ between the output filter inductor electric current i.sub.Lf′ of the charge/discharge converter and u.sub.o. Different phase differences θ are indicative of outputting the active power of different magnitudes and directions. When P.sub.o=P.sub.1max+P.sub.2max+ . . . +P.sub.nmax, θ=90° and the active power output by the charge/discharge converter are zero, the charge/discharge converter is in a no-load state. When P.sub.o>P.sub.1max+P.sub.2max+ . . . +P.sub.nmax, u.sub.o decreases and θ<90°. The charge/discharge converter outputs the active power and the energy storage equipment supplies power to the load. Therefore, the energy storage equipment supplies the shortage of the power needed by the load. When P.sub.o<P.sub.1max+P.sub.2max+ . . . +P.sub.nmax, u.sub.o increases and θ>90°. The charge/discharge converter outputs a minus active power and the load feeds back energy to the energy storage. Therefore, the rest of the power of the plurality of input sources is supplied to charge the energy storage equipment. When θ=180°, the energy fed back to the energy storage equipment by the load is maximum. Therefore, the energy management control strategy can control the magnitude and direction of the power flow of the single-stage isolation bidirectional charge/discharge converter in real time according to the relative magnitude of P.sub.o and P.sub.1max+P.sub.2max+ . . . +P.sub.nmax, which realizes that the system can smoothly and seamlessly switch between three power supply modes.