SPATIAL LIGHT MODULATOR (SLM) COMPRISING INTEGRATED DIGITAL-TO-ANALOG CONVERTERS

Abstract

Arrangement for controlling micromechanical actuators, including a digital-to-analog converter and a plurality of micromechanical actuators; wherein the micromechanical actuators are coupled to a connecting structure; wherein the digital-to-analog converter is configured to provide a voltage to be applied to the connecting structure by an adjustable capacitive voltage division that is dependent on a digital input value of the digital-to-analog converter, wherein the digital-to-analog converter is configured to directly include a capacitance of the connecting structure in the capacitive voltage division.

Claims

1. Arrangement for controlling micromechanical actuators, comprising the following features: a digital-to-analog converter; and a plurality of micromechanical actuators; wherein the micromechanical actuators are coupled to a connecting structure; wherein the digital-to-analog converter is configured to provide a voltage to be applied to the connecting structure by an adjustable capacitive voltage division that is dependent on a digital input value of the digital-to-analog converter, wherein the digital-to-analog converter is configured to directly incorporate a capacitance of the connecting structure into the capacitive voltage division.

2. Arrangement as claimed in claim 1, wherein the connecting structure comprises a connecting line and a plurality of switching transistors connected between the connecting line and storage capacitors associated with the respective micromechanical actuators.

3. The arrangement as claimed in claim 2, wherein the connecting line is passively coupled to a plurality of capacitors that serve to provide adjustable voltage division.

4. Arrangement as claimed in claim 2, wherein the connecting line is DC-coupled or directly coupled to a plurality of switched capacitors of the digital-to-analog converter.

5. Arrangement as claimed in claim 2, wherein the digital-to-analog converter is configured to incorporate the capacitance of the connecting line and of semiconductor regions coupled into the capacitive voltage division toward a reference potential.

6. Arrangement as claimed in claim 1, wherein the digital-to-analog converter and the micromechanical actuators are arranged on a semiconductor chip.

7. Arrangement as claimed in claim 1, wherein the micromechanical actuators are arranged inside a spatial light modulator.

8. Arrangement as claimed in claim 2, wherein the micromechanical actuators are arranged in columns, wherein a plurality of actuators in one column are coupled to a common connecting structure.

9. Arrangement as claimed in claim 2, wherein a first portion of the actuators in an actuator column are coupled to a first column line, and wherein a second portion of the actuators in the actuator column are coupled to a second column line, and wherein the arrangement is configured to alternately couple the first column line and the second column line to switched capacitors of the digital-to-analog converter or to simultaneously couple them to two different digital-to-analog converters.

10. Arrangement as claimed in claim 2, wherein the digital-to-analog converter comprises a first group of capacitors whose first terminals are DC-coupled and whose second terminals may be connected to at least two different reference potentials, as a function of a digital value; wherein the digital-to-analog converter comprises a second group of capacitors whose first terminals are DC-coupled and whose second terminals may be connected to at least two different reference potentials, as a function of a digital value; wherein the first terminals of the first group of capacitors are DC-coupled to the connecting structure; wherein the first terminals of the second group of capacitors are coupled to the first terminals of the first group of capacitors via a first coupling capacitor; wherein the digital-to-analog converter comprises a first reset switch adapted to couple the first terminals of the capacitors of the first group of capacitors to an associated reference potential; wherein the digital-to-analog converter comprises a second reset switch adapted to couple the first terminals of the capacitors of the second group of capacitors to an associated reference potential.

11. Arrangement as claimed in claim 2, wherein the digital-to-analog converter comprises a first group of capacitors whose first terminals are DC-coupled and whose second terminals may be connected to at least three different reference potentials, as a function of a digital value, the selection of the reference potentials depending on at least two bits of a digital value, wherein the digital-to-analog converter comprises a second group of capacitors whose first terminals are DC-coupled and whose second terminals may be connected to at least three different reference potentials, as a function of a digital value; wherein the first terminals of the first group of capacitors are DC-coupled to the connecting structure; wherein the first terminals of the second group of capacitors are coupled to the first terminals of the first group of capacitors via a first coupling capacitor; wherein the digital-to-analog converter comprises a first reset switch adapted to couple the first terminals of the capacitors of the first group of capacitors to an associated reference potential; wherein the digital-to-analog converter comprises a second reset switch adapted to couple the first terminals of the capacitors of the second group of capacitors to an associated reference potential.

12. Arrangement as claimed in claim 10, wherein the second group of capacitors comprises fewer different capacitances than does the first group of capacitors.

13. Arrangement as claimed in claim 10, wherein the digital-to-analog converter comprises a third group of capacitors whose first terminals are DC-coupled and whose second terminals may be connected to at least two different reference potentials, as a function of a digital value; wherein the first terminals of the third group of capacitors are coupled to the first terminals of the second group of capacitors via a second coupling capacitor, wherein the digital-to-analog converter comprises a third reset switch adapted to couple the first terminals of the capacitors of the third group of capacitors to an associated reference potential.

14. Arrangement as claimed in claim 10, wherein the capacitance values of the first group of capacitors are stepped in a binary manner, and the capacitance values are multiples of a basic capacitance; wherein the capacitance values of the second group of capacitors are again stepped in a binary manner and are multiples of the basic capacitance, wherein a maximum capacitance value present in the second group of capacitors is, at the most, half the maximum capacitance value present in the first group of capacitors.

15. Arrangement as claimed in claim 10, wherein the capacitance values of the first group of capacitors are stepped in a binary manner and are multiples of the basic capacitance; wherein the capacitance values of the second group of capacitors are again binary stepped and comprise a multiple of the basic capacitance, wherein a maximum capacitance value in the second group of capacitors is, at the most, a quarter of the maximum capacitance value present in the first group of capacitors.

16. Arrangement as claimed in claim 5, wherein a first reset switch may couple the connecting structure to a reference potential.

17. Arrangement as claimed in claim 9, wherein precharging of the capacitance of the connecting structure and/or of the capacitors of the first group of capacitors occurs during an initialization phase as a function of a digital value, while other switched capacitors are precharged to data-independent voltages; wherein subsequently, data-dependent connecting of the second terminals of the capacitors of the first group of capacitors and of the second group of capacitors to one of two or more different reference voltages takes place.

18. Arrangement as claimed in claim 9, wherein the arrangement comprises a plurality of connecting structures, wherein in an initialization phase associated with providing an analog value on the first connecting structure, at least a first one of the connecting structures is precharged to a potential that is below a target potential for the first connecting structure; in an initialization phase associated with providing an analog value on the second connecting structure, at least a second one of the connecting structures is precharged to a potential that is above a target potential for the second connecting structure; wherein after completion of the initialization phase associated with providing an analog value on the first connecting structure, the second terminals of the capacitors are connected to corresponding reference potential lines in a data-dependent manner so as to raise the potential of the first connecting structure to a target potential for the first connecting structure; wherein after completion of the initialization phase associated with providing an analog value on the second connecting structure, the second terminals of the capacitors are connected to corresponding reference potential lines in a data-dependent manner to decrease the potential of the first connecting structure to a target potential for the second connecting structure.

19. Arrangement as claimed in claim 5, wherein a multiplexer is provided in the arrangement, said multiplexer selectively coupling the switched capacitances of the digital-to-analog converter to different connecting structures and/or column lines.

20. Arrangement as claimed in claim 5, wherein the arrangement is configured to use the connecting structure as a temporary storage for a charge, and to at least partially transfer the charge stored on the connecting structure to an actuator or to a storage capacitance associated with the actuator following disconnection of the switched capacitances of the digital-to-analog converter from the connecting structure.

21. Method of controlling micromechanical actuators in an arrangement comprising a plurality of micromechanical actuators coupled to a connecting structure, wherein a voltage present at the connecting structure is determined by an adjustable capacitive voltage division that is dependent on a digital input value, and wherein a capacitance of the connecting structure is directly incorporated into the capacitive voltage division.

22. A non-transitory digital storage medium having a computer program stored thereon to perform the method of controlling micromechanical actuators in an arrangement comprising a plurality of micromechanical actuators coupled to a connecting structure, wherein: a voltage present at the connecting structure is determined by an adjustable capacitive voltage division that is dependent on a digital input value, and wherein a capacitance of the connecting structure is directly incorporated into the capacitive voltage division, when said computer program is run by a computer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Embodiments of the present invention will be detailed subsequently referring to the appended drawings, in which:

[0043] FIG. 1 schematically shows a spatial light modulator comprising analog data inputs as well as an external control circuit in accordance with conventional technology,

[0044] FIG. 2 schematically shows an inventive spatial light modulator comprising digital data inputs,

[0045] FIG. 3 schematically shows a DRAM structure of an analog spatial light modulator,

[0046] FIG. 4 schematically shows a circuit diagram of a conventional digital-to-analog converter comprising output operational amplifier,

[0047] FIG. 5 schematically shows a circuit diagram of a D/A converter of an inventive control circuit,

[0048] FIG. 6 schematically shows a diagram of the useful reference voltage as a function of a column capacitance,

[0049] FIG. 7 schematically shows a column structure of a spatial light modulator in two embodiments,

[0050] FIG. 8 schematically shows a circuit diagram of a D/A converter comprising reduced capacitances,

[0051] FIG. 9 schematically shows a circuit diagram of a D/A converter comprising initialization of the column capacitance by one of several reference voltages,

[0052] FIG. 10 schematically shows a circuit diagram of a D/A converter comprising several reference voltages, and

[0053] FIG. 11 schematically shows a circuit diagram of a D/A converter comprising three reference voltages and initialization of the column capacitance.

DETAILED DESCRIPTION OF THE INVENTION

[0054] The invention will be explained in more detail below with reference to several embodiments.

[0055] FIG. 1 schematically shows an externally controlled spatial light modulator 80, which is indicated as a two-dimensional matrix/SLM matrix 100 in a common design. The external control circuit comprising a plurality of external digital-to-analog converters/DACs 103, serves to change the elevations and/or tilts of a plurality of micromirrors. The micromirrors, also referred to as pixels, change their respective elevations and/or tilts via appropriately controlled micromechanical actuators. The external digital-to-analog converters/DACs 103 are controlled by digital signals via a control computer 150 and provide corresponding analog signals (voltages) at their outputs. The analog voltages are then applied to column lines 201 of the SLM matrix 100 via an analog SLM interface 160 through its analog multiplexers 106.

[0056] In addition to the actual desired load—the micromechanical actuator—other parasitic loads are exemplified as supply lines 102, bond pads 104. The bond pads 104 are surfaces of a semiconductor element that are to be contacted which serve, for example, to connect the supply lines 102. Furthermore, ESD protection circuits (not shown) may also act as a further parasitic load, for example. The components listed, for example, are mainly responsible for the fact that due to their mere sizes and capacitances, a compact overall design of the spatial light modulator SLM comprising a corresponding control circuit is made more difficult.

[0057] FIG. 2 shows an inventive embodiment of a spatial light modulator 81 comprising a digital SLM interface 260. The digital SLM interface 260 of this embodiment in turn has a plurality of digital input stages 261 provided for receiving digital signals (voltages/currents) that may be fed directly from digital output stages 170 of the control computer 150 via the supply lines 102. In addition, a plurality of digital-to-analog converters 262 are arranged in the digital SLM interface 260. The digital-to-analog converters 262 enable the SLM matrix 100 to be controlled via its column lines 201 with analog voltage values.

[0058] FIG. 3 schematically illustrates an exemplary sub-region of an SLM matrix 100 having six identical memory cells, each corresponding to one of six pixels of the SLM matrix 100. One of these memory cells of the depicted sub-region, which corresponds to a pixel, is shown shaded in gray, on the basis of a corresponding DRAM structure. Under each micromechanical actuator/pixel, such an electronic random access memory device is arranged. An analog DRAM cell comprising a transistor, e.g. a pixel transistor 203, and a storage capacitance/storage capacitor 205, stores an address voltage value until a next refresh. The DRAM structure shown shaded in gray is further characterized by an actuator capacitance and a pn junction capacitance 207. The pn junction capacitance 207 occurs at the material transition in semiconductor crystals between regions of opposite doping of the pixel transistor 203.

[0059] For example, an analog voltage is written into the SLM matrix 100 row by row. For this purpose, all gates of the pixel transistors 203 of a row are opened while the column lines 201 and, thus, the sources of the pixel transistors 203 each have the desired voltages at the same time. When the gates of the pixel transistors 203 are closed, the applied voltages are stored in the capacitances of the pixel cells of this row. All the pixel transistor sources of a column are connected to the column line 201. The total capacitance of such a column line 201 is mainly determined by the pn capacitance 207 of a so-called source region of the pixel transistors 203 and therefore increases as the size of the array increases.

[0060] FIG. 5 shows a circuit diagram of a digital-to-analog converter 400 of an inventive control circuit for controlling micromechanical actuators. The circuit diagram corresponds to a region of an SLM chip between a digital data interface and the micromechanical actuators. A digital-to-analog converter is also referred to as a DAC.

[0061] FIG. 5 shows a special form of digital-to-analog converter, namely a so-called charge scaling DAC, the capacitance of the SLM column line here being directly incorporated as a useful capacitance into the capacitive voltage dividers with the existing charge scaling capacitances, and no operational amplifiers (OPVs) being used, as is the case with conventional digital-to-analog converters.

[0062] FIG. 4 shows a circuit diagram of such a conventional digital-to-analog converter (DAC) 300 comprising an operational amplifier (OPV) 302 having a reference voltage V.sub.ref. Such a DAC 300 might alternatively be implemented with resistor strings or current mirrors, in which case it would exhibit considerably higher power dissipation. In contrast, the digital-to-analog converter 300 shown here, like the DAC 400 of FIG. 5, is based on a so-called charge scaling concept, which has capacitances with which comparatively low-loss operation is possible.

[0063] The digital-to-analog converter of FIG. 4 has a so-called unity-gain OPV 302 as an impedance converter at the output so as to provide a load-independent voltage. This OPV 302 additionally involves higher power consumption, which may increase as a function of speed during operation. In addition, other factors such as linearity and transient response should be considered in this case, where a disadvantageous behavior of the conventional digital-to-analog converters becomes apparent. Furthermore, OPVs may also be very susceptible to mismatch in the differential input stage. This may be of particular importance since hundreds of OPVs are integrated in parallel here, which may greatly reduce the yield in the assembly process/manufacturing process, for example.

[0064] In accordance with the embodiment, to enable a compact design of the overall system comprising a digital interface, the digital-to-analog converters 400 are integrated on the SLM chip together with the digital-to-analog converter of FIG. 5. In this context, power consumption may be kept as low as possible so that the voltages that may be used for the micromirrors can be generated at the highest possible frame rates while still keeping heat generation at a moderate level. The size of the column capacitance C.sub.col 420, the voltage and the refresh rate result in minimum power consumption. Due to the integrated DACs, as little additional energy as possible should be consumed.

[0065] The embodiment of the digital-to-analog converter 400 of FIG. 5 corresponds to an SLM chip comprising an integrated digital data interface and charge scaling DACs. Here, the capacitance of the SLM column line is directly incorporated into the capacitive voltage dividers, and no OPVs are required. This may save, without sacrificing accuracy, potential power dissipation of operational amplifiers since the loads to be served by the digital-to-analog converters are small and known with a high degree of accuracy, as well as all being virtually the same size.

[0066] In order that a desired voltage on the column capacitance C.sub.col 420 may be achieved, a higher reference voltage dependent on the ratio of DAC unit capacitance C to C.sub.col may be applied to a so-called cascode charge scaling DAC comprising charge scaling capacitances, but not requiring an OPV, as according to FIG. 5, as can be seen from the following equation.

[00001]$V_{r.Math.e.Math.f}=V_{\mathrm{col}.Math..Math.\_.Math..Math.\max }.Math.\frac{C_{D.Math.A.Math.C}+C_{c.Math.o.Math.l}}{C_{D.Math.A.Math.C}}=V_{\mathrm{col}.Math..Math.\_.Math.\max }.Math.\frac{1.Math.6.Math.C+C_{c.Math.o.Math.l}}{1.Math.6.Math.C}.fwdarw..Math.\frac{V_{r.Math.e.Math.f}}{V_{\mathrm{col}.Math..Math.\_.Math.\max }}=1+\frac{C_{c.Math.o.Math.l}}{C}$

[0067] This may initially worsen the power balance, but if the capacitances are large enough, less power is converted than is the case with additional OPV, and the reference voltage is allowed to be less. If the reference voltage is increased in terms of proportion, the column voltage V.sub.col that is achieved will depend on the switched capacitance of the DAC in a directly linear manner, as shown in the following equation.

[00002]$V_{c.Math.o.Math.l}=V_{r.Math.e.Math.f}.Math.\frac{C_{\mathrm{DAC}.Math..Math.\_.Math..Math.\mathrm{on}.Math..Math.\_.Math..Math.\mathrm{bits}}}{C_{c.Math.o.Math.l}+C_{\mathrm{DAC}.Math..Math.\_.Math..Math.\mathrm{all}.Math..Math.\_.Math..Math.\mathrm{bits}}}$

[0068] In this respect, FIG. 6 shows the dependence of the voltage that may be used on the ratio of the (DAC) unit capacitance to the column capacitance in a diagram.

[0069] FIG. 7 shows an embodiment in which a possibility for reducing the size of the charge scaling capacitances is illustrated. By dividing the columns, the capacitance of the column line is halved while the speed of the digital-to-analog converter remains the same. This measure may also halve the capacitance of the digital-to-analog converter's capacitors without involving the need to increase the reference voltage.

[0070] This may advantageously reduce a layout area that may be used on the SLM chip. However, this arrangement involves an analog multiplexer 707 as an additional electronic component. Another advantage of this arrangement, in addition to saving layout area on the SLM chip, also allows the power converted in the SLM chip to be reduced by about half.

[0071] Said division may involve dividing the columns in more than two sections. As a limitation, care may be taken to ensure that the additional column lines are routed through the pixel cell. For very high partial factors, for example, increased constructional effort would be useful, caused by the additional column lines and the multiplexer 707 that may additionally be used.

[0072] FIG. 8 shows another embodiment of a digital-to-analog converter 800, with which a further reduction of the useful total capacitance is made possible. This allows further reduction of power dissipation and layout area on the SLM chip. Here, the low-order bits of the cascode circuit are replaced by a C/2C chain or by a two-bit cascode circuit. With equal precision, a capacitance of only approx. 2.17 C per bit may be used here, whereas more than 4 C per bit may be used in the four-bit cascode circuit shown in FIG. 5.

[0073] Here, 4/3 C is selected as the coupling capacitor C.sub.s 1104, since this results in a uniform gradation of the analog values as the data value increases. Deviating values of the coupling capacitor C.sub.s 1104 here might lead to uneven steps in the resulting voltages. Suitable calibration may then provide for increased precision.

[0074] In general, the optimum value of the coupling capacitor is n/(n−1) C, where n denotes the number of different possible values of the lower-order stage of the circuit that is to be coupled; for example, n=4 for the two-bit stages in FIG. 5.

[0075] In order to keep the previously described increase in the reference voltage within appropriate limits, the high-order bits of the cascode circuit should not be replaced by corresponding circuits of the low-order bits in this embodiment. The larger capacitances of this area having the high-order bits in the cascode circuit allow the reference voltage to be limited.

[0076] FIG. 9 shows a further embodiment of a digital-to-analog converter 900, in which a further improvement in performance characteristics may be achieved. This effect may be achieved by precharging the column capacitance 420 to a partial voltage during the initialization phase of the DAC.

[0077] In this embodiment, four reference voltages are provided that may be switched in via reset and preset switches. One of these, usually the smallest, may again be the circuit ground. In a first step, the load capacitance is initially precharged to the next lower reference voltage of a target value in accordance with the two most significant data bits, while the capacitors of the load divider circuit are reset by a short-circuit to ground.

[0078] After opening the initialization switches (reset and preset), in a second step the capacitors of the load divider circuit are charged with one of the reference voltages or held at ground, in accordance with the remaining data bits. Since only a fraction of the output voltage range has to be served at the load capacitance in this second step, the highest of the reference voltages may be smaller, or the capacitance of the capacitors may be dimensioned to be lower.

[0079] In this embodiment, it should be noted that the plurality of reference voltages should be provided in a correspondingly stable and loadable manner. Provision of these fixed reference voltages is performed by the control circuit, wherein a certain power dissipation and a possibly increased expenditure in terms of circuitry should be taken in to account. This involves a sufficient number of bond pads on the SLM chip to be available with precision in every part of the SLM chip, and the number of Interface lines may be increased. However, for more complex SLM chips comprising millions of micromirrors, the advantages of this embodiment have priority.

[0080] As an alternative to the embodiment of FIG. 9, the load divider circuit may also be operated at one of the reference voltages for initializing the column line, which saves provision of a further reference voltage.

[0081] Alternatively, the load capacitance may be precharged to the next higher reference voltage while the remaining data bits have their reference voltage applied to them. In the second step, depending on the digital value to be converted, short-circuit to ground was then applied to the corresponding data bits. Taken by itself, this alternative is equivalent to the previous version, but if, in an SLM chip comprising a very large number of pixels, all data values typically occur on an equal basis, simultaneous utilization of both versions—for example, alternating column by column—may on average considerably reduce the dynamic load on the reference voltages, while it is possible to increase precision.

[0082] FIG. 10 refers to a variant of a digital-to-analog converter 1000 having, for example, four reference voltages 1002. In this embodiment, the reference voltages are used in all stages of the load divider circuit. This means that fewer stages are needed in the charge divider circuit since each of these stages now represents more than one data bit. They are not fully charged and discharged in each clock cycle, which may reduce power dissipation while precision may be increased.

[0083] Alternatively, a different number n of reference voltages may be used. The optimal value of the coupling capacitor 1104 is again n/(n−1) C, although deviating values might lead to uneven steps in the resulting voltages. Suitable calibration may provide for increased precision in this case.

[0084] FIG. 11 shows an embodiment of a digital-to-analog converter 1100, where, again, several reference voltages 1102 are available. These are used here as in FIG. 10 for controlling the DAC steps, and also simultaneously as in FIG. 9 for initializing the load capacitance. The advantages of both above variants may thus be combined.

[0085] While this invention has been described in terms of several embodiments, there are alterations, permutations, and equivalents which fall within the scope of this invention. It should also be noted that there are many alternative ways of implementing the methods and compositions of the present invention. It is therefore intended that the following appended claims be interpreted as including all such alterations, permutations and equivalents as fall within the true spirit and scope of the present invention.