Electro-optically active device

Abstract

A silicon based electro-optically active device and method of producing the same. The silicon based electro-optically active device comprising: a silicon-on-insulator (SOI) waveguide; an electro-optically active waveguide including an electro-optically active stack within a cavity of the SOI waveguide; and a lined channel between the electro-optically active stack and the SOI waveguide, the lined channel comprising a liner; wherein the lined channel is filled with a filling material with a refractive index similar to that of a material forming a sidewall of the cavity, to thereby form a bridge-waveguide in the channel between the SOI waveguide and the electro-optically active stack.

Claims

1. A silicon based electro-optically active device comprising: a silicon-on-insulator (SOI) waveguide; an electro-optically active waveguide including an electro-optically active stack within a cavity of the SOI waveguide; and a lined channel between the electro-optically active stack and the SOI waveguide, the lined channel comprising a liner, wherein the lined channel is filled with a filling material with a refractive index similar to that of a material forming a sidewall of the cavity, to thereby form a bridge-waveguide in the lined channel between the SOI waveguide and the electro-optically active stack, and wherein the liner comprises a first sidewall between the SOI waveguide and the filling material, the first sidewall comprising a material different from a material of the SOI waveguide.

2. The silicon based electro-optically active device of claim 1, wherein the liner is formed of silicon nitride.

3. The silicon based electro-optically active device of claim 1, wherein a lowest surface of sidewalls of the lined channel and a top surface of a portion of the liner located in a base of the lined channel are aligned with a top surface of a buried oxide layer of the SOI waveguide.

4. The silicon based electro-optically active device of claim 1, wherein the liner has a thickness of at least 200 nm no more than 280 nm.

5. The silicon based electro-optically active device of claim 1, wherein the electro-optically active stack includes a multiple quantum well region.

6. The silicon based electro-optically active device of claim 1, wherein the filling material is amorphous silicon.

7. The silicon based electro-optically active device of claim 1, wherein the filling material is silicon-germanium (SiGe).

8. The silicon based electro-optically active device of claim 1, wherein the electro-optically active stack has a parallelogramal or trapezoidal geometry.

9. The silicon based electro-optically active device of claim 1, further comprising an epitaxial cladding layer located in-between a silicon substrate of the SOI waveguide and the electro-optically active stack which forms the electro-optically active waveguide, the epitaxial cladding layer having a refractive index less than that of a buffer layer in the electro-optically active stack.

10. The silicon based electro-optically active device of claim 9, wherein an epitaxial material of the epitaxial cladding layer is silicon.

11. The silicon based electro-optically active device of claim 9, wherein an epitaxial material of the epitaxial cladding layer is silicon-germanium (SiGe).

12. A method of producing the silicon based electro-optically active device of claim 1, the method having the steps of: providing the silicon-on-insulator (SOI) waveguide; etching the cavity in the SOI waveguide through a BOX layer of the SOI waveguide; epitaxially growing the electro-optically active stack within the cavity, and etching the electro-optically active stack to form the electro-optically active waveguide, wherein the epitaxially grown electro-optically active stack has a facet in a region adjacent to the sidewall of the cavity; etching the region to thereby remove the facet and produce a channel between the sidewall and the electro-optically active stack; lining the channel with the liner to provide the lined channel; and filling the lined channel with the filling material which has the refractive index similar to that of the material forming the sidewall so that the filling material forms the bridge-waveguide in the channel between the SOI waveguide and the electro-optically active stack.

13. The method of claim 12, wherein the liner is formed of silicon nitride.

14. The method of claim 12, wherein the liner has a thickness of at least 200 nm no more than 280 nm.

15. The method of claim 12, wherein the electro-optically active stack includes a multiple quantum well region.

16. The method of claim 12, wherein the filling material that the lined channel is filled with comprises amorphous silicon.

17. The method of claim 12, wherein the filling material that the lined channel is filled with comprises silicon-germanium (SiGe).

18. The method of claim 12, wherein the step of filling the lined channel is carried out by plasma-enhanced chemical vapour deposition.

19. The method of claim 12, wherein the step of filling the lined channel is carried out by hot-wire chemical vapour deposition.

20. The method of claim 12, further including a step of planarizing the filling material through chemical-mechanical polishing.

21. The method of claim 12, wherein: the electro-optically active stack has a second facet in a second region adjacent to an opposite sidewall of the cavity, the step of etching the region also removes the second region to thereby remove the second facet and produce a second channel between the opposite sidewall and the electro-optically active stack, and the step of filling the lined channel also fills the second channel with amorphous silicon.

22. The method of claim 21, wherein the silicon based electro-optically active device is a quantum-confined Stark effect based electro-absorption modulator.

23. The method of claim 22, wherein the electro-optically active stack includes a buffer layer, and the method includes adjusting a height of the buffer layer such that an optical mode in the modulator matches an optical mode in the SOI waveguide.

24. The method of claim 12, wherein the electro-optically active stack is grown such that it has a parallelogramal or trapezoidal geometry in the cavity.

25. The method of claim 12, wherein the step of etching a cavity in a part of the SOI waveguide includes the step of etching the SOI waveguide up to or beyond a base of its buried oxide (BOX) layer to create a box-less region.

26. The method of claim 25, further comprising the step of growing a cladding layer within the cavity, the cladding layer having a refractive index which is less than the refractive index of a buffer layer of the electro-optically active stack.

27. A silicon based electro-optically active device comprising: a silicon-on-insulator (SOI) waveguide; an electro-optically active waveguide including an electro-optically active stack within a cavity of the SOI waveguide; and a lined channel between the electro-optically active stack and the SOI waveguide, the lined channel comprising a liner, wherein the lined channel is filled with a filling material with a refractive index similar to that of a material forming a sidewall of the cavity, to thereby form a bridge-waveguide in the lined channel between the SOI waveguide and the electro-optically active stack, and wherein the liner comprises a first sidewall between the SOI waveguide and the filling material, the first sidewall comprising a material different from the filling material.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Embodiments of the invention will now be described by way of example with reference to the accompanying drawings in which:

(2) FIG. 1 shows a device according to the prior art;

(3) FIG. 2 shows a top-down perspective view of a device according to the present invention;

(4) FIGS. 2A-2D show various cross-sections of the device shown in FIG. 2; and

(5) FIGS. 3(A)-3(Q)A show various manufacturing steps according to the present invention.

DETAILED DESCRIPTION AND FURTHER OPTIONAL FEATURES

(6) FIG. 2 shows a device 200 according to the present invention. FIG. 2A shows a cross-sectional view of the device along the line A-A′, FIG. 2B shows a cross-sectional view of the device along the line B-B′, FIG. 2C shows a cross-sectional view of the device along the line C-C′, and FIG. 2D shows a cross-sectional view of the device along the line D-D′.

(7) Broadly, the device comprises a waveguide formed of a rib disposed on top of a slab which extends from one end of the device to the other, in the x direction indicated in the figure. The entire device resides on a silicon substrate 201, which in places is covered with a buried oxide layer 202. The buried oxide layer may be around 400 nm thick, as measured from an uppermost surface of the silicon substrate in the y direction.

(8) Light enters the device via an input port of input waveguide 250. The input waveguide 250 comprises a rib portion 203a which is on top of a slab portion 207a. In this example, both are formed from silicon. Light in the waveguide is guided in direction x i.e. into the plane of FIG. 2B. As is most clearly shown in FIG. 2B, the rib portion 203a has a width, as measured in the y direction, of around 2.5 μm. The rib may have a thickness, measured in the y direction from an uppermost part of the slab portion, of around 0.6 μm. The slab may have a thickness, measured in the y direction from an uppermost part of the buried oxide layer, of around 0.4 μm. The input waveguide sits on top of the buried oxide layer 202 which is, in turn, on top of the silicon substrate 201. The optical mode of the input waveguide is such that the majority of the light is contained within the rib portion 203a, with a minor portion of the light being contained with the slab portion 207a.

(9) Light is guided by the input waveguide 250 from an input port to an output port which is adjacent to a channel. The channel comprises: a first sidewall liner 204a, a filling material 205, and a second sidewall liner 204b. A cross-sectional view of the channel, along the line C-C′, is shown in FIG. 2C. As can be seen, the filling material comprises a rib portion 205a and a slab portion 205c. The dimensions of the filling material substantively match the dimensions of the input waveguide where the input waveguide provides the output port. Beneath the filling material is a first bottom liner 204e, a second bottom liner is located in a second channel located on an opposite side of the device as discussed below. The first and second bottom liners may have a thickness of around 400 nm. The first sidewall liner, the second sidewall liner, and the first bottom liner are all formed of silicon nitride (SiN), for example Si.sub.3N.sub.4. The length of the channel in the x direction is around 3 μm. Below the first bottom liner 204e is a layer 242, which forms a part of the optically active stack discussed below.

(10) The light passes through the channel, which acts as a bridge-waveguide, and enters an optically active stack 210. The stack may have a length, as measured in the x direction and from one channel to the next, of around 80 μm. The stack in this example comprises, from a bottom most layer to an uppermost layer (in a direction away from silicon substrate 201): 242: 400 nm tall transit buffer layer formed of Si.sub.0.8Ge.sub.0.2; 240: 400 nm tall P type buffer layer formed of Si.sub.0.18Ge.sub.0.82; 238: 15 nm tall spacer layer formed of Si.sub.0.18Ge.sub.0.82; 236: 188 nm tall multiple quantum well layer, which comprises 8 Ge quantum wells each 10 nm tall with a 12 nm barrier layer between each, the barrier being formed of Si.sub.0.33Ge.sub.0.67, there may be 9 barrier layers; 234: 15 nm tall spacer layer formed of Si.sub.0.18Ge.sub.0.82; 232: 300 nm tall N layer formed of Si.sub.0.18Ge.sub.0.82 doped to a concentration of 1×10.sup.18 cm.sup.−3; and 230: 80 nm tall N+ layer formed of Si.sub.0.8Ge.sub.0.82 doped to a concentration of >1×10.sup.19 cm.sup.−3.

(11) The dopant species in the N and N+ layers may be phosphorus. Such a stack can provide a quantum-confined Start effect with a peak Δα/alpha of 0.95 at a 1310 nm operating wavelength at 60° C. with 2V bias. The absorption coefficient (cm.sup.−1) at 1310 nm of the multiple quantum well layer may be 320. The multiple quantum well layer may have a refractive index at 1310 nm of around 4.0531. In contrast, the refractive index of the α-silicon fill may be around 3.4.

(12) The optically active stack may be an electro-optically active stack. For example, the optically active stack may be operable as a quantum confined Stark effect modulator.

(13) Detailed parameters of one example are shown in Table 1 below:

(14) TABLE-US-00001 TABLE 1 absorption Doping index coeffictient concentration index real image (k) (cm−1) Layer # Name Thickness (nm) Composition Doping type (cm{circumflex over ( )}3) (n)@1310 nm @1310 nm @1310 nm 230 N-layer 80 Si0.8Ge0.2 N, phosphorus .sup. >1E19 3.6041 0.00001 1 232 N-layer 300 Si0.18Ge0.82 N, phosphorus 1.00E+18 4.0313 0.00083 80 234 spacer 15 Si0.18Ge0.82 uid 4.0313 0.00063 60 236 Barrier 12 Si0.33Ge0.67 uid 4.0531 0.00334 320 236 QW 10 Ge uid 236 Barrier 12 Si0.33Ge0.67 uid 236 QW 10 Ge uid 236 Barrier 12 Si0.33Ge0.67 uid 236 QW 10 Ge uid 236 Barrier 12 Si0 33Ge0.67 uid 236 QW 10 Ge uid 236 Barrier 12 Si0.33Ge0.67 uid 236 QW 10 Ge uid 236 Barrier 12 Si0.33Ge0.67 uid 236 QW 10 Ge uid 236 Barrier 12 Si0.33Ge0.67 uid 236 QW 10 Ge uid 236 Barrier 12 Si0.33Ge0.67 uid 236 QW 10 Ge uid 236 Barrier 12 Si0.33Ge0.67 uid 238 spacer 15 Si0.18Ge0.82 uid 4.0313 0.00063 60 240 Buffer layer 400 Si0.18Ge0.82 P, Boron 1.00E+18 4.0313 0.00073 70 242 Transit buffer 400 Si0.8Ge0.2 uid 3.6041 0.00000 0 Si-sub Si substrate — Si 3.5111 0.00000 0 MQW@0 V 4.0531 0.00334 320 MQW@2 V 4.0531 0.00650 624

(15) The transit buffer layer 242 extends at least part of the way under the channel, as shown most clearly in FIG. 2A. Moreover, both the transit buffer layer 242 and the P type buffer layer extend in the z direction further than the other layers so as to provide a slab to the optically active region as shown most clearly in FIG. 2D. The optically active stack 210 therefore provides a waveguide, including a rib portion formed of layers 238-230 and a slab portion formed of layers 240 and 242. A width of the rib portion, as shown in FIG. 2D, is around 2.5 μm.

(16) In some examples the optically active stack is connected to one or more electrodes, and may be operated as a modulator e.g. an electro-absorption modulator.

(17) After passing through the optically active stack 210, the light passes through a second channel which is formed of a third sidewall liner 204c, a second filling materially 205b and 205d, and a fourth sidewall liner 204d. The structure of the second channel is substantively identical to the first.

(18) After passing through the second channel, the light enters output waveguide 260 which comprises a rib portion 203b on top of a slab portion 207b. The light may then exit the device via an output port in the output waveguide. The output waveguide is generally similar to the input waveguide, and conceptually the device can be considered bi-directional (in that the input waveguide could be the output waveguide and vice versa).

(19) Shown in FIGS. 2A-2D, but not in FIG. 2, is upper insulating layer 206. This upper insulating layer is formed, for example, from silicon dioxide (SiO.sub.2) and can function to passivate the device. It is omitted from FIG. 2 for clarity.

(20) FIGS. 3(A)-3(N) show various manufacturing steps along the same A-A′ plane as FIG. 2A. FIG. 3(A) shows a first manufacturing step according to the present invention. A silicon-on-insulator wafer is provided, which comprises a silicon substrate 201, on top of which is a buried oxide (e.g. Si).sub.2) layer 302. On top of the buried oxide layer is a silicon layer 301, which may be around 1.1 μm-1.5 μm tall (as measured in the y direction from an upper surface of the buried oxide layer to an upper surface of the silicon layer).

(21) Next, as shown in FIG. 3(B), a cavity 303 is etched into the device. The cavity extends to an upper surface 304 of the silicon substrate 201 and includes removal of at least a portion of the buried oxide layer, resulting in first 202a and second 202b buried oxide layers located either side of the cavity. Similarly, a portion of the silicon layer is removed and so first 401a and second 401b silicon portions are provided either side of the cavity 303.

(22) Next, as shown in FIG. 3(C), a first precursor optically active stack 310a is epitaxially deposited onto the now etched silicon-on-insulator wafer. The epitaxial deposition occurs in n stages, where n corresponds to the number of layers in the precursor optically active stack. However, during deposition the precursor optically active stack epitaxially grows from all exposed surfaces. Therefore, not only is there the desirable growth from the upper surface 304 of the silicon substrate, but also from the side walls of the first 401a and second 401b silicon portions and also from the upper surface of these silicon portions. Therefore, facet defects 305a and 305b result which can cause significant signal loss if left in the device. These faceted regions can be understood as resulting from a curvature in each of the layers of the precursor optically active stack.

(23) Subsequent to the step shown in FIG. 3(C), a silicon nitride layer 306 is deposited over the uppermost surface of the first precursor optically active stack 310a. This is shown in FIG. 3D. The silicon nitride layer may be formed of Si.sub.3N.sub.4.

(24) Next, as shown in FIG. 3(E), the device undergoes a chemical-mechanical planarization process. This removes the portions of the first precursor optically active stack 310a which extend above the cavity formed previously as well as a part of each of the silicon portions 401a and 401b. Around 20 nm of the silicon nitride layer 307 is retained. The planarization process and/or a subsequent etching process are performed so that the height of the first 401a and second 401b silicon portions is around 1 μm.

(25) As a next step, a silicon dioxide hard mask 308 is deposited over the upper surface of the device. The result of this is shown in FIG. 3(F).

(26) Subsequently, as shown in FIG. 3(G), photoresists 309a, 309b, and 309c are provided over the upper surface of the device. Gaps 311a and 311b are provided in the photoresists above the facet defect regions 305a and 305b. Seen from a top-down view, the photoresist would be as a single layer with two rectangular gaps above the respective facet defect regions. This photoresist may be provided by depositing a single layer of photoresist, and then removing the material necessary to form the rectangular gaps e.g. via e-beam r optical photolithography.

(27) FIG. 3(H) shows the result of a subsequent step, where the areas not covered by the photoresist have been etched and the photoresist then removed. The depth of this etching step is variable. In the example shown in FIG. 3(H), the etching removes around 240 nm of the 400 nm transit buffer, leaving first 242a and second 242b regions of the transit buffer which have a reduced thickness relative to the remaining transit buffer 242. In an alternative, shown in FIG. 3(H)(i) the etching removes all of the transit buffer not covered by the photoresist and may etch into the silicon substrate 201. The result in this example is a first 201a and second 201b exposed region of the silicon substrate. The etching also provides a first channel 312a and second channel 312b which bound two surfaces of the precursor optically active stack. In general, the etching depth depends on the thickness of the silicon nitride liner on the bottom of the channel in the next process step, to ensure the top surface of the silicon nitride liner is aligned with the top surface of the BOX layer.

(28) The first precursor optically active stack 310a and is now a second precursor optically active stack 310b, which is distinguished from the first by no longer including the facet defect regions 305a and 305b.

(29) After this etching step, the silicon dioxide hard mask 308 is removed and a 240 nm thick silicon nitride (e.g. Si.sub.3N.sub.4) sidewall is deposited on all exposed surfaces of the device. This is shown in FIG. 3(I), and provides a first 313a, second 313b, and third 313c upper liner (which will be removed) and also the sidewall liners 204a-204d as well as the first and second bottom liners 204e and 204f, whose top surfaces are aligned with the top surface of the BOX layer, as shown in FIG. 2A.

(30) Next, as shown in FIG. 3(J), amorphous silicon (also referred to as α-Si) is deposited to fill the remainder of the first 312a and second 312b channels. First 505a and second 505b bulk filling materials are provided, which will provide the filling material shown in FIG. 2A. However there is substantial amounts of bulk amorphous silicon not contained within the channels 312a and 312b, which should be removed.

(31) Therefore, as shown in FIG. 3(K) openings 314a-314c are etched into the amorphous silicon which is not present in the channels 312a and 312b. These openings increase the degree of uniformity obtained during a subsequent chemical-mechanical planarization (CMP) process the result of which is shown in FIG. 3(L). The CMP process is performed so that the upper liner portions 313a-313c are reduced to around 20 nm and the remaining amorphous silicon is substantively aligned with the upper liner portions 313a-313c.

(32) Next, as shown in FIG. 3(M), a further etching step is performed to bring an uppermost surface of the amorphous silicon into line with an uppermost surface of the second pre-precursor optically active stack. Moreover the upper liner portions 313a-313c are removed, and so an uppermost surface 230 of the second pre-cursor optically active stack 310b is exposed. After this, a second hard mask 315 is deposited over the uppermost surface.

(33) FIG. 3(N) shows a subsequent step from a top-down perspective, omitting the second hard mask 315 for clarity. A second photoresist 316 is provided over a central portion of the uppermost surface of the device, extending from one side to the other. The width of the second photoresist (measured in the z direction) defines the width of the resulting rib portion of the input waveguide, output waveguide, and optically active stack. FIGS. 3(N)A-3(N)C show, respectively, cross-sectional views along the lines A-A′, B-B′, and C-C′ in FIG. 3(N).

(34) The uncovered portions are then etched, and the result is shown in FIGS. 3(O)A-3(O)C. In FIG. 3(O)A, taken along the cross-section A-A′ of FIG. 3(N) after etching has been performed, shows the input waveguide now comprises the rib portion 203a and slab portion 207a shown in FIG. 2B. Similarly, FIG. 3(O)B, taken along the cross-section B-B′ of FIG. 3(N) after etching has been performed, shows the filling material now includes a rib portion 205b as well as slab portion 205c which is above the first bottom liner 204e. Further, FIG. 3(O)C, taken along the cross-section C-C′ of FIG. 3(N) after etching has been performed, shows that the second precursor optically active stack has become the optically active stack 210 shown in FIG. 2D.

(35) To provide the device shown in FIGS. 2-2D, the photoresist 316 is removed and bulk silicon dioxide provided to passivate the device.

(36) Further, optional, steps are shown in FIGS. 3(P)-3(Q)A, where one or more electrodes are connected to respective layers of the optically active stack.

(37) FIG. 3(P) shows the result of a further etching step, where one side of the optically active stack 210 is etched to remove a portion of the P type buffer layer 240, so that an upper surface of the transit buffer 242 is exposed. This is most clearly shown in FIG. 3(P)(A) which is a cross-section view of FIG. 3(P) taken along the lines C-C′. The view along cross-sections A-A′ and B-B′ remains substantively unchanged.

(38) Further to this, as shown in FIG. 3(Q) a first 601 and second 602 electrode as provided. As most clearly seen in FIG. 3(Q)A, a cross-section along the lines C-C′ of FIG. 3(Q), the first electrode 601 extends from a position adjacent to the optically active stack (but separated from the transit buffer layer 242 by upper insulating layer 206), up a sidewall of the optically active stack and through a via in the upper insulating layer 206 so as to form an electrical contact with N+ layer 230. Similarly, second electrode 602 extends through a second via in the upper insulting layer 206 to form an electrical contact with the P type buffer layer 240.

(39) When connected to electrodes, the device may be drivable with a voltage of between 0 and 2 V. Optical losses of devices according to the present invention are detailed in Table 2 below:

(40) TABLE-US-00002 TABLE 2 Si/a-Si a-Si/SiGe Interface Total Peak Δα/α Driving Voltage Active Length Active Loss Waveguide Mode MQW Waveguide Coupling Loss wavelength (V) (um) (dB) Mismatch Loss (dB) Mode Mismatch Loss (dB) Loss(dB) (dB) (nm) 0-2 80 5.654 0.052 0.229 0.110 6.044 1310 1-3 105 6.217 0.052 0.229 0.110 6.608 1330

(41) Various dimensions are illustrated on the figures, and should be taken as indications rather than definitive values.

(42) While the invention has been described in conjunction with the exemplary embodiments described above, many equivalent modifications and variations will be apparent to those skilled in the art when given this disclosure. Accordingly, the exemplary embodiments of the invention set forth above are considered to be illustrative and not limiting. Various changes to the described embodiments may be made without departing from the spirit and scope of the invention.

(43) All references referred to above are hereby incorporated by reference.