Micro panchromatic QLED array device based on quantum dot transfer process of deep silicon etching templates, and preparation method therefor
11050004 · 2021-06-29
Assignee
Inventors
- Bin Liu (Nanjing, CN)
- Di Jiang (Nanjing, CN)
- Junchi Yu (Nanjing, CN)
- Xuan Wang (Nanjing, CN)
- Danfeng Pan (Nanjing, CN)
- Zili Xie (Nanjing, CN)
- Yugang Zhou (Nanjing, CN)
- Dunjun Chen (Nanjing, CN)
- Xiangqian Xiu (Nanjing, CN)
- Rong Zhang (Nanjing, CN)
Cpc classification
H01L33/0095
ELECTRICITY
International classification
H01L33/00
ELECTRICITY
Abstract
A micro panchromatic QLED array device based on a quantum dot transfer process of deep silicon etching templates. Array-type square table structures pass through a p-type GaN layer and a quantum well active layer and are deep to an n-type GaN layer are disposed on a blue LED epitaxial wafer, wherein micro holes are formed through etching in the structures. Every 2*2 table structures constitute an RGB pixel unit. Among the four micro holes, three of the holes are filled with red light, green light and yellow light quantum dots respectively, and one of the holes emits blue light/is filled with a blue light quantum dot. Micro holes in a silicon wafer are formed through etching with a deep silicon etching technology; the micro holes in the silicon wafer are aligned with quantum dot filling areas on a micro-LED.
Claims
1. A micro panchromatic QLED array device based on a quantum dot transfer process of deep silicon etching templates, wherein a substrate material of the micro panchromatic QLED array device is a standard blue LED epitaxial wafer or a standard violet LED epitaxial wafer; wherein the standard blue LED epitaxial wafer and the standard violet LED epitaxial wafer each comprising: a quantum well active layer on an n-type GaN layer, and a p-type GaN layer on the quantum well active layer; wherein array-type square table structures are formed by etching on the p-type GaN layer and the quantum well active layer until reaching the n-type GaN layer, wherein the array-type square table structures pass through the p-type GaN layer and the quantum well active layer and the array-type square table structures are deep to the n-type GaN layer; the array-type square table structures are mutually isolated; each of the square table structures constitutes a micro-LED; and micro holes are deep to the p-type GaN layer or the quantum well active layer or the n-type GaN layer, and the micro holes are formed through etching in each of the square table structures to form a micro hole array; the micro panchromatic QLED array device further comprises a p-type array electrode and an n-type electrode, wherein the p-type array electrode is evaporated on the p-type GaN layer of the micro hole array, and the n-type electrode is evaporated on the n-type GaN layer; every 2*2 square table structure of the array-type square table structures constitute an RGB pixel unit, wherein among four micro holes of each of the RGB pixel unit, a first micro hole of the four micro holes is filled with a red light quantum dot, a second micro hole of the four micro holes is filled with a green light quantum dot, a third micro hole of the four micro holes is filled with a yellow light quantum dot, and a fourth micro hole of the four micro holes emits a blue light or the fourth micro hole of the four micro holes is filled with a blue light quantum dot; in each of the RGB pixel unit, a rectangular isolation slot etched until reaching the n-type GaN layer is configured between every two adjacent ones of the square table structures, and the rectangular isolation slot is filled with a light absorption material for a light isolation, the light absorption material is separated from each of the square table structures by a dielectric layer; and each micro hole of the four micro holes is filled with the red light, green light, yellow light, or blue light quantum dot by each of the deep silicon etching templates.
2. The micro panchromatic QLED array device according to claim 1, wherein each of the deep silicon etching templates is formed by adopting a deep silicon etching technology to etch a silicon wafer through to form a hollow square hole structure and a “+”-shaped alignment mark, corresponding to a position of the micro holes filled with the red light, green light, yellow light, or blue light quantum dot, on a surface of the silicon wafer; the “+”-shaped alignment mark is also disposed at a corresponding position on a surface of a micro-LED array device to align each of the deep silicon etching templates with the micro-LED array device; and then, the micro panchromatic QLED array device is prepared through spin-coating of quantum dots, wherein the “+”-shaped alignment mark is disposed at each of four corners or diagonal corners or one corner of each array.
3. The micro panchromatic QLED array device according to claim 1, wherein a regional area with a configuration of the micro hole array is larger than or equal to 4 inches; a diameter of each of the micro holes is 20-100 μm; a cycle is 100-200 μm; an interval between the micro-LEDs is 80-100 μm; and a depth of each of the micro holes is 200 nm to 1.5 μm.
4. The micro panchromatic QLED array device according to claim 1, wherein the rectangular isolation slot is disposed between the two adjacent ones of the square table structures; the rectangular isolation slot has a width of 10-20 μm, a length of being equal to an edge length of each of the square table structures, and a depth of 950 nm; the rectangular isolation slot is filled with the light absorption material; and the light absorption material is a Vantablack or a silver.
5. A preparation method for the micro panchromatic QLED array device according to claim 1, comprising the following steps: 1) evaporating a dielectric layer on the standard blue LED epitaxial wafer or the standard violet LED epitaxial wafer by a PECVD technology; 2) spin-coating a surface of the dielectric layer with a photoresist layer and carrying out prebaking on the photoresist layer, using an ultraviolet lithography technology to transfer ordered square table array graphs on a photoetching plate, graphs of isolation slots for separating adjacent micro hole regions in the square table structures and graphs of “+”-shaped alignment marks between the two adjacent ones of the square table structures to the photoresist layer, and then carrying out development and post-baking; 3) using an RIE technology to introduce O.sub.2 to remove a few of photoresist residual layers in areas where most of a first photoresist is removed through development, using a PVD process to evaporate a metal mask layer, and then carrying out stripping to remove the photoresist layer and a metal film layer on the photoresist layer and obtain an area of an ordered metal square table array graphs, isolation slot graphs and “+”-shaped alignment mark graphs; 4) using the RIE technology to carry out a longitudinal etching of the dielectric layer with a first metal as a first mask, and transferring a metal square table array structure, an isolation slot structure and a “+”-shaped alignment mark structure to the dielectric layer; 5) using an ICP technology to carry out an anisotropic etching of the p-type GaN layer and the quantum well active layer with a second metal as a second mask, and transferring the metal square table array structure, the isolation slot structure between the adjacent micro hole regions and the “+”-shaped alignment marks between the two adjacent ones of the square table structures to the n-type GaN layer; 6) using a wet etching method to remove the metal mask layer and the dielectric layer on the metal square table array structure and the “+”-shaped alignment marks between the two adjacent ones of the square table structures, forming GaN square table array structures, wherein the GaN square table array structures are mutually isolated and repairing an etching damage on a GaN and side walls of a quantum well; 7) preparing a micro hole structure, wherein the PECVD technology is firstly adopted to evaporate the dielectric layer on each of the GaN square table array structures, the surface of the dielectric layer is spin-coated with a second photoresist, and prebaking is carried out on the surface of the dielectric layer; the ultraviolet lithography technology and the photoetching plate are adopted to realize an overlaying on the second photoresist of the metal square table array structure to form micro hole graphs; the RIE technology is adopted at first to etch the dielectric layer, then the ICP technology is adopted to etch the p-type GaN layer; and finally the micro hole array is obtained, wherein a depth of each micro hole is etched to the p-type GaN layer, the quantum well active layer or the n-type GaN layer; 8) using the wet etching method to remove the dielectric layer on the metal square table array structure and the second photoresist left on the dielectric layer, and repairing the etching damage on the GaN and surfaces and the side walls of the quantum well; 9) evaporating the dielectric layer again on the standard blue LED epitaxial wafer; 10) preparing an n-type electrode, wherein the surface of the dielectric layer is spin-coated with a third photoresist and the ultraviolet lithography technology is adopted to overlay an n-type electrode graph on the photoetching plate to the third photoresist; the RIE technology is adopted, the dielectric layer is etched with the third photoresist as a third mask, and the n-type electrode graph is transferred to the n-type GaN layer; the PVD process is adopted to evaporate a first metal layer as the n-type electrode; then, the third photoresist and the metal film layer on the third photoresist layer are stripped and removed, and a sample is cleaned and dried; and a thermal annealing is carried out to realize an ohmic contact between the first metal layer and the n-type GaN; 11) preparing a p-type electrode, wherein spin-coating of a fourth photoresist layer is carried out again, and the ultraviolet lithography technology and the photoetching plate are adopted to realize overlaying on the fourth photoresist to form a p-type electrode graph; the RIE technology is adopted to etch a dielectric layer film with the fourth photoresist as a fourth mask, and the p-type electrode graph is transferred to the p-type GaN layer; then the PVD process is adopted to evaporate a second metal layer as the p-type electrode; the wet etching is adopted to remove the fourth photoresist and the metal film layer on the photoresist layer, and the sample is cleaned and dried; and the thermal annealing is carried out to realize an ohmic contact between the second metal layer and the p-type GaN; 12) filling the isolation slot with the light absorption material, carrying out spin-coating of a fifth photoresist, and using the ultraviolet lithography technology and the photoetching plate to realize overlaying on the fifth photoresist to form an isolation slot graph; carrying out spin-coating of a layer of the light absorption material on a surface of the sample, wherein the light absorption material enters the isolation slot in regions without the fifth photoresist; and then using the wet etching to remove the fifth photoresist and the light absorption material on the surface of the sample, and cleaning and drying the sample; and 13) using the quantum dot transfer process of the deep silicon etching templates to fill the four micro holes with red light, green light, or yellow light quantum dots.
6. The preparation method for the micro panchromatic QLED array device according to claim 5, wherein the deep silicon etching templates are fabricated at first in step 13) and a method for fabricating the deep silicon etching templates comprises: 1) intercepting a silicon wafer, wherein the silicon wafer is equal to or slightly larger than a square table array, spin-coating a surface of the silicon wafer with an AZ4620 positive photoresist, carrying out prebaking on the surface of the silicon wafer, using the ultraviolet lithography technology to transfer a photoetching plate surface graph to the surface of the silicon wafer, and then carrying out development and post-baking; and 2) using the photoresist as a fifth mask and using a deep silicon etching technology to etch the silicon wafer through, forming a hollow square hole structure and a “+”-shaped alignment mark at positions corresponding to the four micro holes filled with the red light, green light, or yellow light quantum dots on the surface of the silicon wafer, making a red light, green light, or yellow light deep silicon etching template, and etching the “+”-shaped alignment mark at a corresponding position on the surface of the sample as well.
7. The preparation method for the micro panchromatic QLED array device according to claim 6, wherein the hollow square hole structure in the deep silicon etching template has an edge length of 90-180 μm, and a depth of being larger than or equal to a thickness of the silicon wafer; the silicon wafer is etched through; the thickness of the silicon wafer is 200-500 μm; and the “+”-shaped alignment mark in the deep silicon etching template and the “+”-shaped alignment mark in the micro panchromatic QLED array device have a maximum length of 40 μm, and a maximum width of 20 μm.
8. The preparation method for the micro panchromatic QLED array device according to claim 7, wherein filling the four micro holes with the quantum dots in step 13) comprises the following steps: 1) placing any one of the red light, green light, or yellow light deep silicon etching templates on the micro-LEDs, and aligning the “+”-shaped alignment mark on the silicon wafer with a “+”-shaped photoetching mark on a micro-LED array under a microscope; 2) spin-coating the micro-LED array with the quantum dots with a corresponding color by a hole-shaped structure on the deep silicon etching template, drying the micro-LED array device spin-coated with the quantum dots, and taking down the deep silicon etching template; and 3) using the deep silicon etching templates of other two colors to repeat steps 1) and 2) twice to fill the four micro holes of each of the RGB pixel unit with quantum dots of the other two colors, thereby preparing and forming the QLED array device.
9. The preparation method for the micro panchromatic QLED array device according to claim 8, wherein the n-type electrode is a metal Ti or Al or Ni or Au; when the p-type electrode is the metal Ni or Au; a thickness of the dielectric layer is 150-250 nm, with a material of SiO.sub.2; and a thickness of the metal mask layer is 30-100 nm, with a material of Ni.
10. The preparation method for the micro panchromatic QLED array device according to claim 5, wherein the red light, green light, or yellow light quantum dots are CdSe/ZnS quantum dots with an II-VI core shell structure or perovskite CsPbBr.sub.3 quantum dots.
11. The micro panchromatic QLED array device according to claim 2, wherein the rectangular isolation slot is disposed between the two adjacent ones of the square table structures; the rectangular isolation slot has a width of 10-20 μm, a length of being equal to an edge length of each of the square table structures, and a depth of 950 nm; the rectangular isolation slot is filled with the light absorption material; and the light absorption material is a Vantablack or a silver.
12. The micro panchromatic QLED array device according to claim 3, wherein the rectangular isolation slot is disposed between the two adjacent ones of the square table structures; the rectangular isolation slot has a width of 10-20 μm, a length of being equal to an edge length of each of the square table structures, and a depth of 950 nm; the rectangular isolation slot is filled with the light absorption material; and the light absorption material is a Vantablack or a silver.
13. The preparation method for the micro panchromatic QLED array device according to claim 5, wherein each of the deep silicon etching templates is formed by adopting a deep silicon etching technology to etch a silicon wafer through to form a hollow square hole structure and a “+”-shaped alignment mark, corresponding to a position of the micro holes filled with the red light, green light, yellow light, or blue light quantum dot, on a surface of the silicon wafer; the “+”-shaped alignment mark is also disposed at a corresponding position on a surface of a micro-LED array device to align each of the deep silicon etching templates with the micro-LED array device; and then, the micro panchromatic QLED array device is prepared through spin-coating of quantum dots, wherein the “+”-shaped alignment mark is disposed at each of four corners or diagonal corners or one corner of each array.
14. The preparation method for the micro panchromatic QLED array device according to claim 5, wherein a regional area with a configuration of the micro hole array is larger than or equal to 4 inches; a diameter of each of the micro holes is 20-100 μm; a cycle is 100-200 μm; an interval between the micro-LEDs is 80-100 μm; and a depth of each of the micro holes is 200 nm to 1.5 μm.
15. The preparation method for the micro panchromatic QLED array device according to claim 5, wherein the rectangular isolation slot is disposed between the two adjacent ones of the square table structures; the rectangular isolation slot has a width of 10-20 μm, a length of being equal to an edge length of each of the square table structures, and a depth of 950 nm; the rectangular isolation slot is filled with the light absorption material; and the light absorption material is a Vantablack or a silver.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
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DETAILED DESCRIPTION OF THE EMBODIMENTS
(24) The technical solutions in the embodiments of the present invention are clearly and completely described in the following with reference to the accompanying drawings in the embodiments of the present invention. Apparently, the embodiments described are merely some rather than all of the embodiments of the present invention. All other embodiments obtained by persons of ordinary skill in the art based on the embodiments in the present invention without making creative efforts shall fall within the protection scope of the present invention.
Embodiment 1 A Micro Panchromatic QLED Array Device Based on a Quantum Dot Transfer Process of Deep Silicon Etching Templates
(25) In the present embodiment, an epitaxial wafer structure selected for a substrate material is shown in
(26) A specific preparation method for a micro-LED array device is as follows:
(27) (1) As shown in
(28) (2) As shown in
(29) (3) A reactive ion etching (RIE) technology is adopted and O.sub.2 is introduced at a gas flow rate of 10 sccm, pressure intensity of 3 Pa and a power of 50 W. A residual layer of the photoresist is removed within 20 seconds. Then, a physical vapor deposition (PVD) process is adopted to evaporate metal Ni of 30 nm thick as a mask 8 on the surface of a sample. As shown in
(30) (4) As shown in
(31) (5) As shown in
(32) (6) As shown in
(33) (7) As shown in
(34) (8) As shown in
(35) (9) As shown in
(36) (10) An n-type electrode is prepared. The surface of the sample is spin-coated with a photoresist layer 12, and prebaking is carried out under 90° C. for 10 minutes. The ultraviolet lithography technology is adopted to overlay an n-type electrode graph on the photoetching plate to the photoresist. Development is carried out. Post-baking under 110° C. is carried out for 1 minute. Then, as shown in
(37) (11) A p-type electrode is prepared. As shown in
(38) (12) The isolation slots are filled with light absorption materials. As shown in
(39) A preparation method for a hole-shaped deep silicon etching template in a quantum dot transfer process of deep silicon etching templates includes the following steps:
(40) (1) A deep silicon etching template is prepared. The surface of a cleaned 200 μm thick silicon wafer 18 is spin-coated with an AZ4620 positive photoresist 19, and prebaking is carried out under 95° C. for 4 minutes. Then, an ultraviolet lithography technology is adopted to transfer graphs of periodical square holes in the surface of a photoetching plate and “+”-shaped alignment marks on four corners of each array to the surface of the silicon wafer. Development is carried out. Post-baking under 110° C. is carried out for 5 minutes. The edge length of the square holes is 90 μm. The rectangular “+”-shaped alignment marks are 40 μm long and 20 μm wide, as shown in
(41) (2) The photoresist is taken as a mask. A deep silicon etching technology is adopted. Gases C.sub.4F.sub.8 and SF.sub.6 are introduced into a reaction chamber for etching for 42 minutes and 40 seconds. The silicon wafer is etched through. Hollow square hole-shaped structures and “+”-shaped alignment marks are formed on the surface of the silicon wafer, as shown in
(42) A quantum dot transfer process of deep silicon etching templates includes the following steps:
(43) (1) A deep silicon etching template is placed above micro-LEDs. A “+”-shaped alignment mark on a silicon wafer and a “+”-shaped photoetching alignment mark on a micro-LED array are aligned under a microscope, as shown in
(44) (2) A red light quantum dot, a green light quantum dot and a yellow light quantum dot of CdSe/ZnS with an II-VI core shell structure are dissolved in a methylbenzene solvent respectively. Then, the surface of the deep silicon etching template is spin-coated with a red light quantum dot solution 20. The quantum dots enter the micro-LED array device via square holes in the deep silicon etching template. The micro-LEDs spin-coated with the quantum dots and the deep silicon etching template are placed on a 60° C. drying table for drying. As shown in
(45) (3) According to the preparation method of the hole-shaped deep silicon etching template, the positions of square micro holes in the deep silicon etching template are changed. Two new deep silicon etching templates are prepared. Step (1) and step (2) are repeated twice. As shown in
(46) Certainly, as for the present embodiment, filling sequences of the red light/green light/yellow light quantum dots can be randomly replaced, which will not bring any influence on quality and performance of the device.
(47) As for the present embodiment, the “+”-shaped alignment marks can also be disposed at diagonal corners or any corner of the device and the silicon wafer.
Embodiment 2 A Micro Panchromatic QLED Array Device Based on a Quantum Dot Transfer Process of Deep Silicon Etching Templates
(48) In the present embodiment, an epitaxial wafer structure selected for a substrate material is shown in
(49) A specific preparation method for a micro-LED array device is as follows:
(50) (1) As shown in
(51) (2) As shown in
(52) (3) A reactive ion etching (RIE) technology is adopted and O.sub.2 is introduced at a gas flow rate of 10 sccm, pressure intensity of 3 Pa and a power of 50 W. A residual layer of the photoresist is removed within 20 seconds. Then, a physical vapor deposition (PVD) process is adopted to evaporate metal Ni of 30 nm thick as a mask 8 on the surface of a sample. As shown in
(53) (4) As shown in
(54) (5) As shown in
(55) (6) As shown in
(56) (7) As shown in
(57) (8) As shown in
(58) (9) As shown in
(59) (10) An n-type electrode is prepared. The surface of the sample is spin-coated with a photoresist layer 12, and prebaking is carried out under 90° C. for 10 minutes. The ultraviolet lithography technology is adopted to overlay an n-type electrode graph on the photoetching plate to the photoresist. Development is carried out. Post-baking under 110° C. is carried out for 1 minute. Then, as shown in
(60) (11) A p-type electrode is prepared. As shown in
(61) (12) The isolation slots are filled with light absorption materials. As shown in
(62) A preparation method for a hole-shaped deep silicon etching template in a quantum dot transfer process of deep silicon etching templates includes the following steps:
(63) (1) A deep silicon etching template is prepared. The surface of a cleaned 400 μm thick silicon wafer 18 is spin-coated with an AZ4620 positive photoresist 19, and prebaking is carried out under 95° C. for 4 minutes. Then, an ultraviolet lithography technology is adopted to transfer graphs of periodical square holes in the surface of a photoetching plate and “+”-shaped alignment marks on four corners of each array to the surface of the silicon wafer. Development is carried out. Post-baking under 110° C. is carried out for 5 minutes. The edge length of the square holes is 134 μm. The rectangular “+”-shaped alignment marks are 40 μm long and 20 μm wide, as shown in
(64) (2) The photoresist is taken as a mask. A deep silicon etching technology is adopted. Gases C.sub.4F.sub.8 and SF.sub.6 are introduced into a reaction chamber for etching for 57 minutes and 12 seconds. The silicon wafer is etched through. Hollow square hole-shaped structures and “+”-shaped alignment marks are formed on the surface of the silicon wafer, as shown in
(65) A quantum dot transfer process of deep silicon etching templates includes the following steps:
(66) (1) A deep silicon etching template is placed above micro-LEDs. A “+”-shaped alignment mark on a silicon wafer and a “+”-shaped photoetching alignment mark on a micro-LED array are aligned under a microscope, as shown in
(67) (2) A red light quantum dot, a green light quantum dot and a yellow light quantum dot of CdSe/ZnS with an II-VI core shell structure are dissolved in a methylbenzene solvent respectively. Then, the surface of the deep silicon etching template is spin-coated with a red light quantum dot solution 20. The quantum dots enter the micro-LED array device via square holes in the deep silicon etching template. The micro-LEDs spin-coated with the quantum dots and the deep silicon etching template are placed on a 60° C. drying table for drying. As shown in
(68) (3) According to the preparation method of the hole-shaped deep silicon etching template, the positions of square micro holes in the deep silicon etching template are changed. Two new deep silicon etching templates are prepared. Step (1) and step (2) are repeated twice. As shown in
(69) Certainly, as for the present embodiment, filling sequences of the red light/green light/yellow light quantum dots can be randomly replaced, which will not bring any influence on quality and performance of the device.
(70) As for the present embodiment, the “+”-shaped alignment marks can also be disposed at diagonal corners or any corner of the device and the silicon wafer.
Embodiment 3 A Micro Panchromatic QLED Array Device Based on a Quantum Dot Transfer Process of Deep Silicon Etching Templates
(71) In the present embodiment, an epitaxial wafer structure selected for a substrate material is shown in
(72) A specific preparation method for a micro-LED array device is as follows:
(73) (1) As shown in
(74) (2) As shown in
(75) (3) A reactive ion etching (RIE) technology is adopted and O.sub.2 is introduced at a gas flow rate of 10 sccm, pressure intensity of 3 Pa and a power of 50 W. A residual layer of the photoresist is removed within 20 seconds. Then, a physical vapor deposition (PVD) process is adopted to evaporate metal Ni of 100 nm thick as a mask 8 on the surface of a sample. As shown in
(76) (4) As shown in
(77) (5) As shown in
(78) (6) As shown in
(79) (7) As shown in
(80) (8) As shown in
(81) (9) As shown in
(82) (10) An n-type electrode is prepared. The surface of the sample is spin-coated with a photoresist layer 12, and prebaking is carried out under 90° C. for 10 minutes. The ultraviolet lithography technology is adopted to overlay an n-type electrode graph on the photoetching plate to the photoresist. Development is carried out. Post-baking under 110° C. is carried out for 1 minute. Then, as shown in
(83) (11) A p-type electrode is prepared. As shown in
(84) (12) The isolation slots are filled with light absorption materials. As shown in
(85) A preparation method for a hole-shaped deep silicon etching template in a quantum dot transfer process of deep silicon etching templates includes the following steps:
(86) (1) A deep silicon etching template is prepared. The surface of a cleaned 500 μm thick silicon wafer 18 is spin-coated with an AZ4620 positive photoresist 19, and prebaking is carried out under 95° C. for 4 minutes. Then, an ultraviolet lithography technology is adopted to transfer graphs of periodical square holes in the surface of a photoetching plate and “+”-shaped alignment marks on diagonal corners of each array to the surface of the silicon wafer. Development is carried out. Post-baking under 110° C. is carried out for 5 minutes. The edge length of the square holes is 180 μm. The rectangular “+”-shaped alignment marks are 40 μm long and 20 μm wide, as shown in
(87) (2) The photoresist is taken as a mask. A deep silicon etching technology is adopted. Gases C.sub.4F.sub.8 and SF.sub.6 are introduced into a reaction chamber for etching for 95 minutes and 20 seconds. The silicon wafer is etched through. Hollow square hole-shaped structures and “+”-shaped alignment marks are formed on the surface of the silicon wafer, as shown in
(88) A quantum dot transfer process of deep silicon etching templates includes the following steps:
(89) (1) A deep silicon etching template is placed above micro-LEDs. A “+”-shaped alignment mark on a silicon wafer and a “+”-shaped photoetching alignment mark on a micro-LED array are aligned under a microscope, as shown in
(90) (2) A red light quantum dot, a green light quantum dot and a yellow light quantum dot of CdSe/ZnS with an II-VI core shell structure are dissolved in a methylbenzene solvent respectively. Then, the surface of the deep silicon etching template is spin-coated with a red light quantum dot solution 20. The quantum dots enter the micro-LED array device via square holes in the deep silicon etching template. The micro-LEDs spin-coated with the quantum dots and the deep silicon etching template are placed on a 60° C. drying table for drying. As shown in
(91) (3) According to the preparation method of the hole-shaped deep silicon etching template, the positions of the square micro holes in the deep silicon etching template are changed. Two new deep silicon etching templates are prepared. Step (1) and step (2) are repeated twice. The micro holes of each RGB pixel unit are filled with a green light quantum dot solution 21 and a yellow light quantum dot solution 22, so that four-color display of each RGB pixel point is realized. A schematic diagram of a cross section of the device obtained is shown in
(92) Certainly, as for the present embodiment, filling sequences of the red light/green light/yellow light quantum dots can be randomly replaced, which will not bring any influence on quality and performance of the device.
(93) As for the present embodiment, the “+”-shaped alignment marks can also be disposed at four corners or any corner of the device and the silicon wafer.
Embodiment 4 A Micro Panchromatic QLED Array Device Based on a Quantum Dot Transfer Process of Deep Silicon Etching Templates
(94) In the present embodiment, an epitaxial wafer structure selected for a substrate material is a standard violet LED epitaxial wafer with a p-n structure, which includes a sapphire substrate 1; a GaN buffer layer 2 growing on the sapphire substrate; an n-type GaN layer 3 growing on the buffer layer; a quantum well active layer 4 growing on the n-type GaN layer; and a p-type GaN layer 5 growing on the quantum well active layer.
(95) A specific preparation method for a micro-LED array device is as follows:
(96) (1) A plasma enhanced chemical vapor deposition (PECVD) technology is adopted to evaporate a 250 nm thick SiO.sub.2 dielectric layer 6 on a In.sub.xGa.sub.1-xN/GaN quantum well blue LED epitaxial wafer. A growth mode of SiO.sub.2 with the PECVD is as follows: a mixed gas of 5% SiH.sub.4/N.sub.2 and N.sub.2O is introduced into a reaction chamber, wherein flow rates are 100 sccm and 450 sccm, respectively. Under the conditions of pressure intensity of 300 mTorr, a power of 10 W and a temperature of 350° C., SiO.sub.2 is deposited on the surface of the epitaxial wafer through a reaction of SiH.sub.x+O.fwdarw.SiO.sub.2 (+H.sub.2) for the duration of 11 minutes and 50 seconds.
(97) (2) The SiO.sub.2 dielectric layer is spin-coated with a photoresist 7, and prebaking is carried out under 90° C. for the duration of 10 minutes; then, an ultraviolet lithography technology is adopted to transfer graphs on a photoetching plate to the photoresist, so that ordered square table array graphs, graphs of rectangular isolation slots which divide adjacent micro hole regions in square tables, and “+”-shaped alignment marks on diagonal corners of each array between the adjacent square tables are formed; then development is carried out; and post-baking is carried out under 110° C. for 1 minute.
(98) (3) A reactive ion etching (RIE) technology is adopted and O.sub.2 is introduced at a gas flow rate of 10 sccm, pressure intensity of 3 Pa and a power of 50 W. A residual layer of the photoresist is removed within 20 seconds. Then, a physical vapor deposition (PVD) process is adopted to evaporate metal Ni of 50 nm thick as a mask 8 on the surface of a sample. An evaporation rate is 0.5 A/s. Then, an acetone solution is adopted for ultrasonic treatment for 10 minutes to strip the photoresist layer 7 and the metal Ni film 8 on the photoresist layer. A large area of the ordered square table array graphs, the graphs of the rectangular isolation slots between the adjacent micro holes and “+”-shaped alignment marks between the adjacent tables are obtained. An interval between the adjacent tables is 100 μm; the width of the isolation slots is 20 μm; and the maximum length of the “+”-shaped alignment marks is 40 μm, and the maximum width of the “+”-shaped alignment marks is 20 μm.
(99) (4) The RIE technology is adopted to introduce a mixed gas of CF.sub.4 and O.sub.2 into the reaction chamber, wherein flow rates of the gases are CF.sub.4: 30 sccm and O.sub.2: 10 sccm; the power is 150 W; pressure intensity is 4 Pa; and the etching duration is 5 minutes. With metal Ni as the mask, longitudinal etching is carried out on the dielectric layer SiO.sub.2. Metal square table structures, rectangular isolation slot structures between the adjacent micro holes and the “+”-shaped alignment marks between the adjacent square tables are transferred to the dielectric layer 6.
(100) (5) An inductivity coupled plasma (ICP) technology is adopted to introduce a mixed gas of Cl.sub.2 and BCl.sub.3 into the reaction chamber. With metal 8 and the dielectric layer 6 as the mask, anisotropic etching is carried out on the p-type GaN layer 5 and the quantum well layer 4 till the n-type GaN layer 3, so that a large area of the mutually isolated square table structures, the rectangular isolation slots between the adjacent micro holes and the “+”-shaped alignment marks between the adjacent square tables are formed. Etching conditions are as follows: Cl.sub.2: 24 sccm; BCl.sub.3: 3 sccm; the ICP power is 600 W; the RF power is 10 W; the pressure intensity is 6.5 mTorr; the duration is 9 minutes and 30 seconds; the etching depth is about 950 nm; and an interval between adjacent micro-LEDs formed is 100 μm.
(101) (6) Wet etching is adopted to remove the metal mask layer 8 and the dielectric layer 6. Specifically, the sample is soaked in a nitric acid aqueous solution and a buffer oxide etchant (BOE) in succession, wherein one duration is 1 minute and the other duration is 40 seconds, respectively. The soaking process can also reduce etching damage on GaN and side walls of the quantum well.
(102) (7) The PECVD technology is adopted to evaporate a 250 nm thick SiO.sub.2 dielectric layer 9 as a mask. A mixed gas of 5% SiH.sub.4/N.sub.2 and N.sub.2O is introduced into the reaction chamber, wherein flow rates are 100 sccm and 450 sccm, respectively, the pressure intensity is 300 mTorr, the power is 10 W, the temperature is 350° C., and the duration is 11 minutes and 50 seconds. A SiO.sub.2 layer is deposited on the surface of the sample through a reaction of SiH.sub.x+O.fwdarw.SiO.sub.2 (+H.sub.2). Then the surface of the sample is spin-coated with a photoresist layer 10, and prebaking is carried out under 90° C. for 10 minutes. Then the ultraviolet lithography technology and a photoetching plate are adopted for overlaying on the photoresist to form a micro hole graph with the diameter of 100 and a cycle of 200 μm. Development is carried out. Post-baking is carried out under 110° C. for 1 minute. Then, the RIE technology is adopted to introduce a mixed gas of CF.sub.4 and O.sub.2 into the reaction chamber, wherein flow rates of the gases are CF.sub.4: 30 sccm and O.sub.2: 10 sccm; the power is 150 W; the pressure intensity is 4 Pa; and the etching duration is 5 minutes. A photoresist 10 is used as a mask for longitudinal etching of the dielectric layer SiO.sub.2 6. The ICP technology is adopted to introduce a mixed gas of Cl.sub.2 and BCl.sub.3 into the reaction chamber. The photoresist 10 and the dielectric layer 9 are taken as masks for anisotropic etching of the p-type GaN layer 5. Etching conditions are as follows: Cl.sub.2: 24 sccm; BCl.sub.3: 3 sccm; the ICP power is 600 W; the RF power is 10 W; the pressure intensity is 6.5 mTorr; the duration is 15 minutes; and the etching depth is about 1.5 μm. A micro hole array with the diameter of 100 μm, a cycle of 200 μm and a depth of 1.5 μm is obtained.
(103) (8) Wet etching is used. The sample is soaked in the BOE for 1 minute. The SiO.sub.2 dielectric layer 9 and a residual photoresist layer 10 on the dielectric layer are removed. In addition, etching damage on GaN and the surface and side walls of the quantum well is reduced.
(104) (9) The PECVD technology is adopted to evaporate a 250 nm thick SiO.sub.2 dielectric layer 11 on the surface of the sample. A mixed gas of 5% SiH.sub.4/N.sub.2 and N.sub.2O is introduced into the reaction chamber, wherein flow rates are 100 sccm and 450 sccm, respectively, the pressure intensity is 300 mTorr, the power is 10 W, the temperature is 350° C., and the duration is 11 minutes and 50 seconds. A SiO.sub.2 layer is deposited on the surface of the sample through a reaction of SiH.sub.x+O.fwdarw.SiO.sub.2 (+H.sub.2).
(105) (10) An n-type electrode is prepared. The surface of the sample is spin-coated with a photoresist layer 12, and prebaking is carried out under 90° C. for 10 minutes. The ultraviolet lithography technology is adopted to overlay an n-type electrode graph on the photoetching plate to the photoresist. Development is carried out. Post-baking under 110° C. is carried out for 1 minute. Then, the RIE technology is adopted to introduce a mixed gas of CF.sub.4 and O.sub.2 into the reaction chamber, wherein flow rates of the gases are CF.sub.4: 30 sccm and O.sub.2: 10 sccm; the power is 150 W; the pressure intensity is 4 Pa; and the etching duration is 5 minutes. The photoresist 12 is taken as a mask for etching a SiO.sub.2 dielectric layer film 11. The n-type electrode graph is transferred to n-type GaN 3. The PVD process is adopted to successively evaporate four metals of Ti, Al, Ni and Au on the surface of the sample, with thicknesses of 100 nm, 150 nm, 200 nm and 400 nm respectively, and a product is taken as an n-type electrode 13. Then, an acetone ultrasonic technology is adopted to strip the photoresist 12 and the metal film 13 on the photoresist layer. The sample is cleaned and dried. In the end, thermal annealing is carried out under N.sub.2, a temperature of 750° C. and a duration of 30 seconds. In this way, ohmic contact between the metal Ti/Al/Ni/Au and the n-type GaN is realized.
(106) (11) A p-type electrode is prepared. The surface of the sample is spin-coated with a photoresist layer 14, and prebaking is carried out under 90° C. for 10 minutes. The ultraviolet lithography technology is adopted to overlay a p-type electrode graph on the photoetching plate to the photoresist. Development is carried out. Post-baking under 110° C. is carried out for 1 minute. The RIE technology is adopted to introduce a mixed gas of CF.sub.4 and O.sub.2 into the reaction chamber, wherein flow rates of the gases are CF.sub.4: 30 sccm and O.sub.2: 10 sccm; the power is 150 W; the pressure intensity is 4 Pa; and the etching duration is 5 minutes. The photoresist 14 is taken as a mask for etching a SiO.sub.2 dielectric layer film 9. The p-type electrode graph is transferred to p-type GaN 3. The PVD process is adopted to successively evaporate two metals of Ni and Au on the surface of the sample, with thicknesses of 250 nm and 300 nm respectively, and a product is taken as a p-type electrode 15. An acetone ultrasonic technology is adopted to strip the photoresist 14 and the metal film 15 on the photoresist layer. The sample is cleaned and dried. In the end, thermal annealing is carried out under Na, a temperature of 750° C. and a duration of 30 seconds. In this way, ohmic contact between the metal Ni/Au and the p-type GaN is realized.
(107) (12) The isolation slots are filled with light absorption materials. The surface of the sample is spin-coated with a photoresist layer 16 again, and prebaking is carried out under 90° C. for 10 minutes. The ultraviolet lithography technology and the photoetching plate are adopted for overlaying on the photoresist to form graphs of the rectangular isolation slots. Development is carried out. Post-baking under 110° C. is carried out for 1 minute; the surface of the sample is spin-coated with a layer of light absorption material silver 17, and the light absorption material enters the isolation slots in regions without the photoresist; then, through wet etching, the sample is soaked in the BOE for 1 minute, the photoresist 16 and the light absorption material 17 thereon are removed. The sample is cleaned and dried.
(108) A preparation method for a hole-shaped deep silicon etching template in a quantum dot transfer process of deep silicon etching templates includes the following steps:
(109) (1) A deep silicon etching template is prepared. The surface of a cleaned 500 μm thick silicon wafer 18 is spin-coated with an AZ4620 positive photoresist 19, and prebaking is carried out under 95° C. for 4 minutes. Then, an ultraviolet lithography technology is adopted to transfer graphs of periodical square holes in the surface of a photoetching plate and “+”-shaped alignment marks on diagonal corners of each array to the surface of the silicon wafer. Development is carried out. Post-baking under 110° C. is carried out for 5 minutes. The edge length of the square holes is 180 μm. The rectangular “+”-shaped alignment marks are 40 μm long and 20 μm wide.
(110) (2) The photoresist is taken as a mask. A deep silicon etching technology is adopted. Gases C.sub.4F.sub.8 and SF.sub.6 are introduced into a reaction chamber for etching for 95 minutes and 20 seconds. The silicon wafer is etched through. Hollow square hole-shaped structures and “+”-shaped alignment marks are formed on the surface of the silicon wafer.
(111) A quantum dot transfer process of deep silicon etching templates includes the following steps:
(112) (1) A deep silicon etching template is placed above micro-LEDs. A “+”-shaped alignment mark on a silicon wafer and a “+”-shaped photoetching alignment mark on a micro-LED array are aligned under a microscope.
(113) (2) A blue light quantum dot, a red light quantum dot, a green light quantum dot and a yellow light quantum dot of perovskite CsPbBr.sub.3 are dissolved in a methylbenzene solvent respectively. Then, the surface of the deep silicon etching template is spin-coated with a blue light quantum dot solution. The quantum dots enter the micro-LED array device via square holes in the deep silicon etching template. The micro-LEDs spin-coated with the quantum dots and the deep silicon etching template are placed on a 60° C. drying table for drying. The deep silicon etching template is removed; and on the micro-LED array device, only one of RGB pixel points is coated with the blue light quantum dot.
(114) (3) According to the preparation method of the hole-shaped deep silicon etching template, the positions of the square micro holes in the deep silicon etching template are changed. Three new deep silicon etching templates are prepared. Step (1) and step (2) are repeated three times. The micro holes of each RGB pixel unit are filled with a red light quantum dot solution, a green light quantum dot solution and a yellow light quantum dot solution, so that four-color display of each RGB pixel point is realized. A schematic diagram of a cross section of the device obtained is shown in
(115) Certainly, as for the present embodiment, filling sequences of the red light/green light/yellow light quantum dots can be randomly replaced, which will not bring any influence on quality and performance of the device.
(116) As for the present embodiment, the “+”-shaped alignment marks can also be disposed at four corners or any corner of the device and the silicon wafer.
(117) In the present embodiments of the present invention, square holes are taken as the hollow holes of the deep silicon etching templates. In fact, it is feasible to make the hollow holes into rectangular holes or round holes or elliptic holes. It is only necessary to note that the holes are sized to completely expose the micro holes to be filled with the quantum dots and guarantee that the micro holes to be filled with the quantum dots of other colors are not exposed.
(118) The foregoing embodiments are preferred implementations of the present invention, but the implementations of the present invention is not limited by the foregoing embodiments. Any other changes, modifications, replacements, combinations, or simplification made without departing from the spirit essence and principle of the present invention shall be regarded as equivalent substitutions and shall fall within the protection scope of the present invention.