Differential circuit calibration apparatus and method

Abstract

An apparatus for calibrating a differential circuit that includes a differential integrator having an input, a gain, and an output connected to a comparator. The differential integrator output is chargeable to a threshold prior to an integration period. The differential integrator integrates the input during the integration period such that the differential integrator output goes toward zero from the threshold. The comparator detects the output of the differential integrator reaching zero. The apparatus includes a closed-loop gain trim circuit to perform a coarse calibration to adjust and set the gain of the differential integrator and a reference generator that generates the threshold to which the differential integrator output is pre-charged. The reference generator is trimmable during a fine calibration to adjust and set the threshold to correct for residual gain error in the differential circuit remaining after the coarse calibration is performed.

Claims

1. An apparatus for calibrating a differential circuit that includes a differential integrator having an input, a gain, and an output connected to a comparator, wherein the differential integrator output is chargeable to a threshold prior to an integration period, wherein the differential integrator integrates the input during the integration period such that the differential integrator output goes toward zero from the threshold, wherein the comparator detects the output of the differential integrator reaching zero, the apparatus comprising: a closed-loop gain trim circuit to perform a coarse calibration to adjust and set the gain of the differential integrator; a reference generator that generates the threshold to which the differential integrator output is pre-charged; and wherein the reference generator is trimmable during a fine calibration to adjust and set the threshold to correct for residual gain error in the differential circuit remaining after the coarse calibration is performed.

2. The apparatus of claim 1, wherein the input of the differential integrator senses a current drawn from a voltage source/supply; and wherein the differential circuit is operable to detect the over-threshold condition of an average current drawn from the voltage source/supply if the comparator detects the output of the differential integrator reaches zero.

3. The apparatus of claim 2, wherein after the coarse calibration and fine calibration are performed, the differential circuit is configured to detect the over-threshold condition of the average current drawn from the voltage source/supply with a range of error less than 0.3%.

4. The apparatus of claim 2, wherein the input of the differential integrator senses the current drawn from the voltage source/supply across a sense resistor; wherein a resistance value of the sense resistor is configurable to a plurality of different values; and wherein the threshold generated by the reference generator is scalable to a plurality of different values corresponding to the plurality of different configurable resistance values of the sense resistor.

5. The apparatus of claim 1, wherein the fine calibration is performed by sourcing a known current value to the differential circuit for a known value of the integration period and adjusting the threshold in an iterative manner until successive transitions of the output of the comparator are detected.

6. The apparatus of claim 1, wherein the reference generator comprises a trimmable digital-to-analog converter (DAC).

7. The apparatus of claim 6, wherein the fine calibration applies a successive approximation register (SAR) algorithm to the trimmable DAC.

8. The apparatus of claim 6, wherein the reference generator is programmable to a plurality of different values of the threshold; and wherein the coarse calibration and fine calibration are performed at a single programmed value of the plurality of different values of the threshold.

9. The apparatus of claim 8, wherein resistive elements of the DAC are accurately sized to achieve a range of error less than 0.3% for detection of an over-threshold condition for each of the plurality of different values of the threshold after performance of the coarse calibration and fine calibration at the single value.

10. The apparatus of claim 1, wherein the coarse calibration comprises adjusting and setting a capacitance of an integrating capacitor of the differential integrator or an integrating resistor of the differential integrator.

11. The apparatus of claim 1, wherein single-ended outputs of the differential integrator concurrently cross a common mode reference when the output of the differential integrator reaches the zero value; wherein the reference generator converts the common mode reference to the threshold; and wherein the reference generator is trimmable during the fine calibration to adjust and set the threshold by adjusting and setting the common mode reference.

12. The apparatus of claim 1, wherein the reference generator is adjustable to support a plurality of different values of the integration period.

13. A method for calibrating a differential circuit that includes a differential integrator having an input, a gain, and an output connected to a comparator, wherein the differential integrator output is chargeable to a threshold prior to an integration period, wherein the differential integrator integrates the input during the integration period such that the differential integrator output goes toward zero from the threshold, wherein the comparator detects the output of the differential integrator reaching zero, the method comprising: performing, in a closed-loop manner, a coarse calibration to adjust and set the gain of the differential integrator; and performing a fine calibration of a trimmable reference generator that generates the threshold to which the differential integrator output is pre-charged by adjusting and setting the threshold to correct for residual gain error in the differential circuit remaining after the coarse calibration is performed.

14. The method of claim 13, wherein the input of the differential integrator senses a current drawn from a voltage source/supply; and wherein the differential circuit is operable to detect the over-threshold condition of an average current drawn from the voltage source/supply if the comparator detects the output of the differential integrator reaches zero.

15. The method of claim 14, wherein after the coarse calibration and fine calibration are performed, the differential circuit is configured to detect the over-threshold condition of the average current drawn from the voltage source/supply with a range of error less than 0.3%.

16. The method of claim 14, wherein the input of the differential integrator senses the current drawn from the voltage source/supply across a sense resistor; wherein a resistance value of the sense resistor is configurable to a plurality of different values; and wherein the threshold generated by the reference generator is scalable to a plurality of different values corresponding to the plurality of different configurable resistance values of the sense resistor.

17. The method of claim 13, wherein said performing the fine calibration comprises sourcing a known current value to the differential circuit for a known value of the integration period and adjusting the threshold in an iterative manner until successive transitions of the output of the comparator are detected.

18. The method of claim 13, wherein the reference generator comprises a trimmable digital-to-analog converter (DAC).

19. The method of claim 18, wherein said performing the fine calibration comprises applying a successive approximation register (SAR) algorithm to the trimmable DAC.

20. The method of claim 18, wherein the reference generator is programmable to a plurality of different values of the threshold; and wherein said performing the coarse calibration and the fine calibration are performed at a single programmed value of the plurality of different values of the threshold.

21. The method of claim 20, wherein resistive elements of the DAC are accurately sized to achieve a range of error less than 0.3% for detection of an over-threshold condition for each of the plurality of different values of the threshold after performance of the coarse calibration and fine calibration at the single value.

22. The method of claim 13, wherein said performing the coarse calibration comprises adjusting and setting a capacitance of an integrating capacitor of the differential integrator or an integrating resistor of the differential integrator.

23. The method of claim 13, wherein single-ended outputs of the differential integrator concurrently cross a common mode reference when the output of the differential integrator reaches the zero value; wherein the reference generator converts the common mode reference to the threshold; and wherein said performing a fine calibration by adjusting and setting the threshold comprises adjusting and setting the threshold by adjusting and setting the common mode reference.

24. The method of claim 13, wherein the reference generator is adjustable to support a plurality of different values of the integration period.

25. A non-transitory computer-readable medium having instructions stored thereon that are capable of causing or configuring an apparatus for calibrating a differential circuit that includes a differential integrator having an input, a gain, and an output connected to a comparator, wherein the differential integrator output is chargeable to a threshold prior to an integration period, wherein the differential integrator integrates the input during the integration period such that the differential integrator output goes toward zero from the threshold, wherein the comparator detects the output of the differential integrator reaching zero, wherein the instructions cause or configure the apparatus to perform operations comprising: performing, in a closed-loop manner, a coarse calibration to adjust and set the gain of the differential integrator; and performing a fine calibration of a trimmable reference generator that generates the threshold to which the differential integrator output is pre-charged by adjusting and setting the threshold to correct for residual gain error in the differential circuit remaining after the coarse calibration is performed.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a block diagram of an example system in accordance with embodiments of the present disclosure.

(2) FIG. 2 is a circuit diagram of a current sense system, or path, and a graph illustrating operation thereof according to an embodiment of the average current detector of FIG. 1.

(3) FIG. 3 is a circuit diagram of the current sense system of FIG. 2 and a graph illustrating coarse trim of the gain of the differential integrator of FIG. 2 according to embodiments of the present disclosure.

(4) FIG. 4 is a circuit diagram of the current sense system of FIG. 2 and a graph illustrating fine trim of the gain of the differential integrator of FIG. 2 according to embodiments of the present disclosure.

(5) FIG. 5 is a circuit diagram of the comparator reference generator of the current sense system of FIG. 2 according to embodiments of the present disclosure.

(6) FIG. 6 is a circuit diagram of the reference generator of the current sense system mentioned with respect to FIG. 2 according to embodiments of the present disclosure.

(7) FIG. 7 is a graph illustrating effects of the coarse and fine calibration of the gain of the differential integrator of FIG. 2 according to embodiments of the present disclosure.

(8) FIG. 8 is a flowchart illustrating a method of coarse and fine calibration according to embodiments of the present disclosure.

(9) FIG. 9 is a flowchart illustrating in more detail a method of fine calibration according to embodiments of the present disclosure.

DETAILED DESCRIPTION

(10) FIG. 1 is a block diagram of an example system 10 in accordance with embodiments of the present disclosure. The example system 10 has an average current detector 12, a charge pump 14, and an amplifier 19. The charge pump 14 includes charge pump switches 16 and charge pump logic 18. A supply current I.sub.VP is fed into the charge pump 14. In the embodiment of FIG. 1, a power supply (e.g., a battery) supplies a voltage V.sub.P to provide the supply current I.sub.VP. The supply current I.sub.VP is closely monitored by the average current detector 12 and regulated. The charge pump 14 provides a boost voltage V.sub.BST that further helps power the amplifier 19. In the example of FIG. 1, the amplifier 19 may drive a speaker 17.

(11) The average current detector 12 includes a differential integrator INT whose output is provided to a comparator COMP whose operation is described in more detail below. A sense resistor R.sub.SNS of the average current detector 12 senses the supply current I.sub.VP. In one embodiment, the sense resistor R.sub.SNS is a resistor whose resistance is highly temperature-insensitive (e.g., tantalum resistor, tantalum nitride resistor, or other low temperature coefficient resistor). The terminals of the sense resistor R.sub.SNS are coupled to respective inputs of the differential integrator INT through a pair of integrating resistors R.sub.INT. A pair of integrating capacitors C.sub.INT connect inputs to outputs of the differential integrator INT. More specifically, a first integrating capacitor C.sub.INT connects the non-inverting input to the inverting output of the differential integrator INT and a second integrating capacitor C.sub.INT connects the inverting input to the non-inverting output, as shown in FIG. 2. The differential integrator INT integrates the supply current I.sub.VP over a switching cycle, or integration period T.

(12) The gain for the differential integrator INT is calibrated by the calibration method and apparatus in accordance with embodiments of the present disclosure so that high accuracy requirements for providing the average current are satisfied. The calibration of the gain is performed by both a coarse trim and a fine trim that are applied on the gain of the differential integrator INT. In one embodiment, after the coarse and fine calibration are performed, the average current in the integration period may be known with greater than 1% accuracy.

(13) FIG. 2 is a circuit diagram of a current sense (ISNS) system 22, or path, and a graph illustrating operation thereof according to an embodiment of the average current detector 12 of FIG. 1. The current sense system 22 includes four main sub-blocks: a differential integrator INT (e.g., differential integrator INT of FIG. 1), a comparator COMP (e.g., comparator COMP of FIG. 1), a comparator reference generator 52 (see FIG. 5, for example), and a single-ended reference generator 62 (see FIG. 6, for example). The single-ended reference generator 62 generates a single-ended common mode reference voltage V.sub.CM. The comparator reference generator 52 generates a differential comparator reference threshold V.sub.TH+ and V.sub.TH− based on the single-ended common mode reference voltage V.sub.CM. The supply current I.sub.VP (e.g., of FIG. 1) generated by a supply voltage V.sub.P is detected or sensed by a sense resistor R.sub.SNS (e.g., R.sub.SNS of FIG. 1). The differential integrator INT integrates the voltage sensed across the sense resistor R.sub.SNS over one integration period. The output V.sub.OUT_INT of the differential integrator INT is then compared by the comparator COMP to a set differential comparator reference threshold V.sub.TH+−V.sub.TH− to determine whether the supply current I.sub.VP integrated over the integration period exceeds the threshold. The inverting output of the differential integrator INT is connected to the non-inverting input V.sub.IN_COMP+ of the comparator COMP, and the non-inverting output of the differential integrator INT is connected to the inverting input V.sub.IN_COMP− of the comparator COMP.

(14) As shown in the embodiment of FIG. 2, each integrating capacitor C.sub.INT comprises a pair of integrating capacitors C.sub.INT, or flycaps. During an integrating period, a first flycap of the pair is connected across the differential integrator INT to perform integration while the second flycap of the pair is connected to the comparator reference generator 52 to be pre-charged to its threshold value (V.sub.TH+ or V.sub.TH−). During the next integrating period, a second flycap is connected across the differential integrator INT to perform integration while the first flycap is connected to the comparator reference generator 52 to be pre-charged to its threshold value (V.sub.TH+ or V.sub.TH−). This operation continues in a ping-pong fashion for each pair of integrating capacitors C.sub.INT. Thus, at the start of the integration period, the integrating capacitors C.sub.INT are pre-charged, or refreshed, differentially to V.sub.TH+−V.sub.TH−, i.e., the comparator reference threshold, as shown in the graph. More specifically, the non-inverting input V.sub.IN_COMP+ of the comparator COMP is pre-charged to V.sub.TH+, and the inverting input V.sub.IN_COMP− of the comparator COMP is pre-charged to V.sub.TH−. The graph illustrates detection of an instance of an over-threshold condition. As shown in the graph, once the integration period begins, V.sub.IN_COMP+ decreases from its pre-charged value of V.sub.TH+ until it crosses an input common mode value V.sub.IN_COMP_CM (which is the single-ended reference voltage V.sub.CM) and V.sub.IN_COMP− increases from its pre-charged value of V.sub.TH− until it crosses the input common mode value V.sub.IN_COMP_CM, at which point the value of the output V.sub.OUT_INT of the differential integrator INT is zero, which indicates the integrated value of the supply current I.sub.VP during the switching period has reached the comparator COMP reference threshold V.sub.TH+−V.sub.TH−. The output V.sub.OUT_COMP of the comparator COMP indicates when (and if) the integrated value of the supply current I.sub.VP has reached the comparator COMP reference threshold V.sub.TH+−V.sub.TH−. The value of the output V.sub.OUT_COMP is initially low and transitions to a high value when (after a delay of the comparator COMP) the comparator COMP inputs V.sub.IN_COMP+ and V.sub.IN_COMP− have crossed the common mode value V.sub.IN_COMP_CM, i.e., when the integrated supply current I.sub.VP has exceeded the comparator reference threshold V.sub.TH+−V.sub.TH−, which is when the output V.sub.OUT_INT of the differential integrator INT reaches zero.

(15) The magnitude of the integrated value of the supply current I.sub.VP by the differential integrator INT (i.e., excluding output inversion and pre-charging the comparator COMP input) is given by equation (1).

(16) $\begin{array}{cc}{V}_{\mathrm{OUT}\_\mathrm{INT}}=\frac{I_{\mathrm{VP}}*R_{\mathrm{SNS}}}{R_{\mathrm{INT}}*C_{\mathrm{INT}}*F_{\mathrm{SW}}}& \left(1\right)\end{array}$
where F.sub.SW is the switching frequency, which is the reciprocal of the integration period T.

(17) FIG. 3 is a circuit diagram of the current sense system 22 of FIG. 2 and a graph illustrating coarse trim of the gain of the differential integrator INT of FIG. 2 according to embodiments of the present disclosure. As shown in FIG. 3, a current source (rather than the charge pump 14 of FIG. 1, for example) is connected during calibration to draw a current I.sub.DC across the sense resistor R.sub.SNS. As also shown in FIG. 3, a successive approximation register (SAR) circuit receives the output V.sub.OUT_COMP of the comparator COMP. As also shown in FIG. 3, the capacitances of the integrating capacitors C.sub.INT of FIG. 2 are variable and may therefore be adjusted, or trimmed, so that a coarse range for the gain of the differential integrator INT is set. A control circuit (not shown) uses the SAR data in a closed-loop fashion to trim the capacitance of the integrating capacitors C.sub.INT. In an alternate embodiment, the capacitance of the integrating capacitors C.sub.INT may be trimmed linearly. By adjusting the capacitances of the integrating capacitors C.sub.INT, the gain of the differential integrator INT (which is essentially a function of the values of R.sub.SNS, R.sub.INT and C.sub.INT, as may be observed from equation (1) above and equation (3) below) is adjusted such that, in effect, the slope of the line representing the output V.sub.OUT_INT of the differential integrator INT going to a zero-crossing is adjusted and set, as shown in the graph of FIG. 3. More specifically, as shown in the graph, the output V.sub.OUT_INT of the differential integrator INT rises linearly over time from its initial pre-charged value of −V.sub.OFF to zero Volts over the integration period T, where V.sub.OFF is the comparator reference threshold V.sub.TH+−V.sub.TH−, as expressed in equation (2).
V.sub.OFF=V.sub.TH+−V.sub.TH−  (2)

(18) As shown, the output V.sub.OUT_INT of the differential integrator INT may vary according to the precision of the trimmable integrating capacitors C.sub.INT. In one embodiment, the gain of differential integrator INT may be adjusted by adjusting the capacitance of C.sub.INT such that the zero-crossing of the output V.sub.OUT_INT of the differential integrator INT may be calibrated to within a coarse range of plus or minus 3.5%. In an alternate embodiment, trimmable resistors may be employed in place of the trimmable integrating capacitors C.sub.INT in order to adjust the gain of differential integrator INT.

(19) The output V.sub.OUT_INT of the differential integrator INT is expressed in equation (3)

(20) $\begin{array}{cc}{V}_{\mathrm{OUT}\_\mathrm{INT}}=-V_{\mathrm{OFF}}+\frac{I_{\mathrm{DC}}*R_{\mathrm{SNS}}}{R_{\mathrm{INT}}}*\frac{1}{C_{\mathrm{INT}}}*T& \left(3\right)\end{array}$
where I.sub.DC is the current drawn across the sense resistor, R.sub.SNS is the resistance of the sense resistor, R.sub.INT is the resistance of the integrating resistors, C.sub.INT is the adjusted capacitance of the integrating capacitors, and T is the period over which the differential integrator INT integrates the current I.sub.DC. I.sub.DC and T are known quantities.

(21) By making adjustments to the capacitance value of integrating capacitors C.sub.INT and by, in effect, adjusting the slope of the respective line of the output V.sub.OUT_INT of differential integrator INT, a coarse range for the differential integrator gain is achieved. For example, by making a coarse trim, process variations for the components/elements used in the average current detector 12 are trimmed within a coarse range. However, for purposes of average current going into a charge pump (e.g., from current from a battery to a charge pump), the coarse range and coarse trim may not be enough to satisfy high accuracy requirements. Thus, further adjusting or tuning of the gain of the differential integrator INT may be needed. Therefore, a fine trim is also performed as described below.

(22) FIG. 4 is a circuit diagram of the current sense system 22 of FIG. 2 and a graph illustrating fine trim of the gain of the differential integrator INT of FIG. 2 according to embodiments of the present disclosure. FIG. 4, as well as equations (2) and (3), are used to illustrate the fine trim of the gain of the differential integrator. An offset V.sub.OFF, which is the comparator reference threshold V.sub.TH+−V.sub.TH−, at the output of the differential integrator INT exists. Based on the relationships within the equations, the offset V.sub.OFF of the output V.sub.OUT_INT of differential integrator INT is utilized and adjusted so errors that occur or exist after the coarse trim is performed are further corrected within a fine range. The fine trim on the offset V.sub.OFF corrects for residue gain errors of the coarse trim because the time of integration (e.g., t=0 to T) is fixed. In the example of FIG. 4, the fine range that is achieved for the gain is less than 0.3%. As shown in the graph, the output V.sub.OUT_INT of the differential integrator INT rises linearly from its initial pre-charged value—V.sub.OFF to zero Volts over the integration period T such that, in one embodiment, the fine range is accomplished by adjusting the offset V.sub.OFF to within plus or minus 3.5%. The adjustment of the offset V.sub.OFF in combination with the adjustment of the gain of the differential integrator INT may result in an ability of the current sense system 22 to detect an over-threshold condition of the integrated supply current I.sub.VP to within 0.3% accuracy. In other embodiments, accuracy may be further increased by employing circuit techniques such as sizing resistors and reducing amplifier noise.

(23) The offset V.sub.OFF is adjusted by adjusting the generated common mode reference V.sub.CM, e.g., as described in more detail below with respect to FIGS. 5 through 9. As shown in FIG. 4, the SAR data (the received output V.sub.OUT_COMP of the comparator COMP) is used to adjust the offset V.sub.OFF.

(24) FIG. 5 is a circuit diagram of the comparator reference generator 52 of the current sense system 22 of FIG. 2 according to embodiments of the present disclosure. The comparator reference generator 52 converts the common mode voltage reference V.sub.CM to the differential threshold voltage V.sub.TH+−V.sub.TH− to accomplish the fine trim of the differential integrator INT.

(25) The comparator reference generator 52 includes first and second operational amplifiers AMP1 and AMP2 that receive common mode voltage reference V.sub.CM on their non-inverting inputs. Amplifier AMP1 generates the positive threshold voltage V.sub.TH+, and amplifier AMP2 generates the negative threshold voltage V.sub.TH−. A feedback resistor R.sub.FB connects the output and the inverting input of amplifier AMP1. A stack of eight resistors R.sub.TH in series connect the outputs of AMP1 and AMP2. The inverting input of AMP2 is connected halfway down the stack of series resistors R.sub.TH. An offset resistor R.sub.OFFSET is connected between ground and the inverting input of amplifier AMP1 and is used to set the differential threshold voltage V.sub.TH+−V.sub.TH−, as described in more detail below. Finally, K DAC resistors R.sub.DAC in parallel are connected to the inverting input of amplifier AMP1 and by switches to ground. K specifies the number of closed switches, i.e., the number of connected DAC resistors R.sub.DAC. In the embodiment of FIG. 5, the value K is programmable between zero and 40 to generate 41 different threshold levels corresponding to a range of 1.6 A to 3.6 A in steps of 50 mA.

(26) The values of V.sub.TH+ and V.sub.TH− may be expressed by equations (4) and (5).

(27) $\begin{array}{cc}{V}_{\mathrm{TH}+}=V_{\mathrm{CM}}+V_{\mathrm{CM}}*R_{\mathrm{FB}}*\left(\frac{1}{R_{\mathrm{OFFSET}}}+\frac{K}{R_{\mathrm{DAC}}}\right)& \left(4\right)\\ V_{\mathrm{TH}-}=V_{\mathrm{CM}}-V_{\mathrm{CM}}*R_{\mathrm{FB}}*\left(\frac{1}{R_{\mathrm{OFFSET}}}+\frac{K}{R_{\mathrm{DAC}}}\right)& \left(5\right)\end{array}$
In one embodiment, to set a current level of 1.6 A, K=0; to set a current level of 3.6 A, K=40. Additionally, the feedback resistor R.sub.FB value is programmable to adjust the differential thresholds to support multiple switching frequencies, e.g., 1.5 MHz, 1.7 MHz, 2 MHz, 2.4 MHz, 3 MHz, and 4 MHz. In one embodiment, after calibration at 3.6 A, a plus or minus 30 mA accuracy is met at 1.6 A. In one embodiment the differential threshold voltage V.sub.OFF (i.e., V.sub.TH+−V.sub.TH−) may be scaled by factors of 0.75×, 0.5× and 0.25×, as shown in FIG. 5 to account for corresponding variations in the value of the sense resistor R.sub.SNS.

(28) FIG. 6 is a circuit diagram of the single-ended reference generator 62 of the current sense system 22 mentioned with respect to FIG. 2 according to embodiments of the present disclosure. The single-ended reference generator 62 generates the common mode reference voltage V.sub.CM in an adjustable fashion to accomplish fine trim of the gain of the differential integrator INT. A representative resistive digital-to-analog converter (DAC) to produce a single-ended voltage V.sub.CM is shown in FIG. 6.

(29) The single-ended reference generator 62 includes a fine trim decoder 64 that receives a digital trim code and responsively generates trim selection levels that are provided to a switch block 66 that outputs the single ended reference voltage V.sub.CM. In one embodiment, the trim code is a 6-bit code. The single-ended reference generator 62 also includes a current source connected between a voltage source V.sub.P (e.g., bandgap voltage) and a stack of series resistors that is connected to ground. Between each pair of resistors is a tap, which are denoted tap<0>, tap<1>, tap<2> through tap<n−1>, tap<n>. The taps are provided as inputs to the switch block 66 which selects the taps based on the trim selection levels to produce a summed voltage that is the single ended reference voltage V.sub.CM. The calibration sequence updates the trim code which updates the trim selection level which updates the value of the single ended reference voltage V.sub.CM, e.g., as described in more detail with respect to FIG. 9. The single ended reference voltage V.sub.CM is used by the comparator reference generator 52 of FIG. 5 to generate the differential threshold voltage V.sub.TH+−V.sub.TH− as described above.

(30) FIG. 7 is a graph illustrating effects of the coarse and fine calibration of the gain of the differential integrator INT of FIG. 2 according to embodiments of the present disclosure. The graph depicts current levels on the horizontal axis and the value of the reference generated by the comparator reference generator 52, i.e., the differential threshold voltage V.sub.TH+−V.sub.TH−, on the vertical axis. Subtracting equation (5) from equation (4), the differential threshold voltage V.sub.TH+−V.sub.TH− may be expressed by equation (6).

(31) $\begin{array}{cc}{V}_{\mathrm{TH}+}-V_{\mathrm{TH}-}=2*V_{\mathrm{CM}}*R_{\mathrm{FB}}*\left(\frac{1}{R_{\mathrm{OFFSET}}}+\frac{K}{R_{\mathrm{DAC}}}\right)& \left(6\right)\end{array}$

(32) Ideally, the differential threshold reference needs to be a value given by expression (7) to detect an integrated current at a threshold of 3.6 A, the differential threshold reference needs to be a value given by expression (8) to detect an integrated current at a threshold of 1.6 A, and the differential threshold reference needed to detect an integrated current at intervening threshold values is along the dotted line shown on the graph between these two points, which are given by equation (6).

(33) $\begin{array}{cc}2*V_{\mathrm{CM}}*R_{\mathrm{FB}}*\left(\frac{1}{R_{\mathrm{OFFSET}}}+\frac{40}{R_{\mathrm{DAC}}}\right)& \left(7\right)\\ 2*V_{\mathrm{CM}}*R_{\mathrm{FB}}*\left(\frac{1}{R_{\mathrm{OFFSET}}}\right)& \left(8\right)\end{array}$

(34) As shown on the graph by a line labeled pre-gain calibration, prior to gain calibration the slope and the offset of the line may vary significantly from the ideal line. However, advantageously, the slope and the offset of the line are much closer to the ideal line after the coarse and fine calibration are performed.

(35) Finally, although the current sense system 22 may be programmed to detect an over-threshold condition of the integrated supply current I.sub.VP for multiple current threshold values (e.g., via programmable K of FIG. 5), a single point calibration may be performed (e.g., at 3.6 A) that meets the accuracy requirements when the threshold is at a different point (e.g., 1.6 A). In order to meet the performance at the other current threshold values, the elements of the resistive DAC of the comparator reference generator 52 of FIG. 5 may need to be sized to meet the accuracy requirement. As shown in the graph, advantageously the accuracy may be met at all current levels (1.6 A through 3.6 A) even though only a single-point calibration (e.g., at 3.6 A) is performed.

(36) FIG. 8 is a flowchart illustrating a method of coarse and fine calibration according to embodiments of the present disclosure. Operation begins at block 802.

(37) At block 802, in a system (e.g., system 10 of FIG. 1) having a charge pump (e.g., charge pump 14 of FIG. 1), the charge pump is operated in a static mode to facilitate calibration. Operation proceeds to block 804.

(38) At block 804, a sense resistor path (e.g., of current sense path 22 of FIG. 2) is turned on. Operation proceeds to block 806.

(39) At block 806, a supply voltage (e.g., supply voltage V.sub.P of FIG. 2) level is maintained (e.g., a level from 3 to 5 Volts) at a corresponding flycap pin (e.g., C.sub.INT of FIG. 2). Operation proceeds to block 808.

(40) At block 808, a current is forced into the supply voltage pin (e.g., current I.sub.DC of FIG. 3 with a value of 3.6 A). Operation proceeds to block 812.

(41) At block 812, a coarse calibration is performed on the sense resistor path, e.g., obtaining a trim code of the variable capacitance integrating capacitors C.sub.INT of FIG. 3 to adjust and set the gain of differential integrator INT so that the output of the differential integrator INT crosses a zero value at the end of an integration period according to FIG. 3. The coarse calibration of block 812 may be performed in an iterative manner (e.g., according to a SAR algorithm) similar to that described below with respect to FIG. 9. Operation proceeds to block 814.

(42) At block 814, a fine calibration is performed on the current sense path 22, e.g., obtaining a trim code of the resistive DAC of the single-ended reference generator 62 of FIG. 6 that generates the single-ended reference voltage V.sub.CM, which is used by the comparator reference generator 52 of FIG. 5 to generate the differential comparator reference threshold V.sub.TH+ and V.sub.TH−, i.e., to adjust offset V.sub.OFF according to FIG. 4, to correct residual errors from the coarse calibration of the gain of the differential integrator INT at block 812. Operation proceeds to block 816.

(43) At block 816, the sense resistor path is turned off.

(44) FIG. 9 is a flowchart illustrating in more detail a method of fine calibration (e.g., operation at block 814 of FIG. 8) according to embodiments of the present disclosure. Operation begins at block 902.

(45) At block 902, an initial trim code is set for the resistive DAC of the single-ended reference generator 62 of FIG. 6 to generate the single-ended voltage reference (e.g., bandgap voltage) V.sub.CM. Operation proceeds to block 904.

(46) At block 904, the comparator reference generator 52 of FIG. 5 converts the single-ended voltage reference V.sub.CM to the differential comparator reference threshold V.sub.TH+ and V.sub.TH−. Operation proceeds to block 906.

(47) At block 906, the differential integrator INT integrates the current I.sub.DC (e.g., 3.6 A) for a full integration period T. Operation proceeds to decision block 908.

(48) At decision block 908, if the output V.sub.OUT_COMP of the comparator COMP is high, operation proceeds to block 912; otherwise, operation proceeds to block 914.

(49) At block 912, the trim code of the resistive DAC is increased to increase the level of the single-ended voltage reference V.sub.CM. Operation proceeds to decision block 916.

(50) At block 914, the trim code of the resistive DAC is decreased to decrease the level of the single-ended voltage reference V.sub.CM. Operation proceeds to decision block 916.

(51) At decision block 916, if there was a transition of the level of the output V.sub.OUT_COMP of the comparator COMP from the current instance of blocks 902 to blocks 908 to the previous instance of blocks 902 to blocks 908, which indicates the desired trim code has been obtained, operation proceeds to block 918; otherwise, operation returns to decision block 908 to continue iterating to search for the desired trim code.

(52) At block 918, the current trim code is saved as the final trim code.

(53) It should be understood—especially by those having ordinary skill in the art with the benefit of this disclosure—that the various operations described herein, particularly in connection with the figures, may be implemented by other circuitry or other hardware components. The order in which each operation of a given method is performed may be changed, unless otherwise indicated, and various elements of the systems illustrated herein may be added, reordered, combined, omitted, modified, etc. It is intended that this disclosure embrace all such modifications and changes and, accordingly, the above description should be regarded in an illustrative rather than a restrictive sense.

(54) Similarly, although this disclosure refers to specific embodiments, certain modifications and changes can be made to those embodiments without departing from the scope and coverage of this disclosure. Moreover, any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element.

(55) Further embodiments likewise, with the benefit of this disclosure, will be apparent to those having ordinary skill in the art, and such embodiments should be deemed as being encompassed herein. All examples and conditional language recited herein are intended for pedagogical objects to aid the reader in understanding the disclosure and the concepts contributed by the inventor to furthering the art and are construed as being without limitation to such specifically recited examples and conditions.

(56) This disclosure encompasses all changes, substitutions, variations, alterations, and modifications to the example embodiments herein that a person having ordinary skill in the art would comprehend. Similarly, where appropriate, the appended claims encompass all changes, substitutions, variations, alterations, and modifications to the example embodiments herein that a person having ordinary skill in the art would comprehend. Moreover, reference in the appended claims to an apparatus or system or a component of an apparatus or system being adapted to, arranged to, capable of, configured to, enabled to, operable to, or operative to perform a particular function encompasses that apparatus, system, or component, whether or not it or that particular function is activated, turned on, or unlocked, as long as that apparatus, system, or component is so adapted, arranged, capable, configured, enabled, operable, or operative.