Method and circuitry for open load detection

Abstract

In described examples, a method of determining whether there is an open load fault in a test circuit includes closing a first switch to couple an input voltage to a first LC filter in which a first capacitor is coupled to a ground, the first LC filter coupled to a first terminal coupled to the test circuit; and closing a second switch to couple the input voltage to a second LC filter in which a second capacitor is coupled to the ground, the second LC filter coupled to a second terminal coupled to the test circuit. After the LC filters charge to the input voltage, the second switch is opened, and the second capacitor is discharged across a discharge resistor for a specified discharge time. The voltage across the discharge resistor falling below a reference voltage indicates that there is an open load fault in the test circuit.

Claims

1. Circuitry for detecting an open load fault, comprising: an input voltage terminal configured to receive an input voltage; a first switch having a first terminal and second terminal wherein the first terminal is coupled to the input voltage terminal; a first inductor-capacitor (LC) filter having an input terminal and an output terminal wherein the input terminal is coupled to the second terminal of the first switch; a second switch having a first terminal and second terminal; a second LC filter having an input terminal and an output terminal; a discharge resistor having a first terminal and a second terminal wherein the first terminal is coupled to the output of the second LC filter; a first load terminal coupled to the output of the first LC filter, and a second load terminal coupled to the input of the second LC filter; a third switch having a first terminal and a second terminal wherein the first terminal is coupled to the second terminal of the discharge resistor and the second terminal is coupled to ground; a first voltage-divider resistor having a first terminal and a second terminal wherein the first terminal is coupled to the output of the second LC filter; a comparator having a first input, a second input and an output wherein the second input is coupled to the second terminal of the first voltage-divider resistor; a second voltage-divider resistor having a first terminal and a second terminal wherein the first terminal is coupled to the second terminal of the first voltage-divider resistor; a comparator switch having a first terminal and a second terminal wherein the first terminal is coupled to the second terminal of the second voltage-divider resistor and the second terminal is coupled to ground; and a reference voltage circuitry configured to produce a reference voltage and to provide the reference voltage to a second input of the comparator.

2. The circuitry of claim 1 further comprising: a control circuitry configured to control: the first switch to close until the first LC filter is charged to the input voltage, and the second switch to close until the second LC filter is charged to the input voltage; the first switch to remain closed, the second switch to open, and the third switch to close after the first and second LC filters are charged to the input voltage, and until a voltage across the discharge resistor remains constant; and the comparator switch to close for a period of time after the voltage across the discharge resistor remains constant; wherein the comparator is configured to output an Open Load Flag signal, the Open Load Flag signal indicating an open load fault in a test circuit, when a voltage at the second terminal of the first voltage-divider resistor is below the reference voltage while the comparator switch is closed.

3. The circuitry of claim 2, the reference voltage circuitry comprising: a first vref voltage-divider resistor coupled to the input voltage and to a reference voltage terminal, the reference voltage terminal coupled to the second input to the comparator and to a reference voltage switch; and a second vref voltage-divider resistor coupled to the ground and to the reference voltage switch; wherein the control circuitry is configured to control the reference voltage switch to close when it controls the comparator switch to close, and wherein the reference voltage circuitry is configured to provide the reference voltage from the reference voltage terminal to the comparator when the reference voltage switch is closed.

4. The circuitry of claim 3, wherein the first test voltage-divider resistor has a resistance R.sub.test_1, the second test voltage-divider resistor has a resistance R.sub.test_2, the first vref voltage divider-resistor has a resistance R.sub.vref_1, the second voltage-divider resistor has a resistance R.sub.vref_2, and the discharge resistor has a resistance R.sub.DIS; wherein the test circuit includes, in series between the first and second load terminals, a constant resistance R.sub.SPK and a resistance R.sub.OPEN corresponding to open load faults in the test circuit; wherein the comparator is configured to output the Open Load Flag as TRUE when the voltage at the test voltage terminal falls below a threshold voltage corresponding to a value of R.sub.OPEN of approximately R.sub.TH while the comparator switch is closed, R.sub.TH defined as: $R_{\mathrm{TH}}=\left(\frac{R_{\mathrm{vref}\_1}}{R_{\mathrm{vref}\_1}+R_{\mathrm{vref}\_2}}/\frac{R_{\mathrm{test}\_1}}{R_{\mathrm{test}\_1}+R_{\mathrm{test}\_2}}-1\right)\times R_{\mathrm{DIS}}.$

5. The circuitry of claim 4, wherein the control circuitry is configured to close the comparator switch for longer than a time t.sub.MIN corresponding to a minimum expected time for the voltage at the test voltage terminal to fall below R.sub.TH when there is an open load fault in the test circuit, t.sub.MIN being derived by using a minimum expected value of R.sub.OPEN when there is an open load fault in the test circuit, as follows: $k=\frac{R_{\mathrm{test}\_1}}{R_{\mathrm{test}\_1}+R_{\mathrm{test}\_2}}/\frac{R_{\mathrm{vref}\_1}}{R_{\mathrm{vref}\_1}+R_{\mathrm{vref}\_2}}$ $\tau =C_F\times \frac{R_{\mathrm{DIS}}\times \left(R_{\mathrm{OPEN}}+R_{\mathrm{SPK}}\right)}{R_{\mathrm{DIS}}+\left(R_{\mathrm{OPEN}}+R_{\mathrm{SPK}}\right)}$ where C.sub.F=capacitance of the capacitor in the first LC filter and capacitance of the capacitor in the second LC filter, and $\mathrm{tMIN}=-\tau \times \ln \left[k+\left(k-1\right)\times \frac{R_{\mathrm{DIS}}}{R_{\mathrm{OPEN}}}\right].$

6. The circuitry of claim 1, wherein an inductance of the first LC filter equals an inductance of the second LC filter.

7. The circuitry of claim 1, wherein a capacitance of the first LC filter equals a capacitance of the second LC filter.

8. The circuitry of claim 1, wherein a resistance of the discharge resistor is greater than a resistance of the test circuit when there is not an open load fault in the test circuit.

9. The circuitry of claim 1, wherein the reference voltage circuitry is configured to produce the reference voltage so that it is proportional to the input voltage.

10. The circuitry of claim 1, wherein the first and second switches, the first and second LC filters, and the first and second terminals are included in an H bridge.

11. A method of determining whether there is an open in a test circuit, the method comprising: a) closing a first switch to couple an input voltage to a first LC filter in which a first capacitor is coupled to a ground, wherein the first LC filter is coupled to a first terminal of the test circuit; b) closing a second switch to couple the input voltage to a second LC filter in which a second capacitor is coupled to the ground, wherein the second LC filter is coupled to a second terminal coupled to the test circuit; c) waiting for the first and second LC filters to charge to the input voltage; d) keeping the first switch closed, opening the second switch, and discharging the second capacitor across a discharge resistor for a discharge time; e) comparing a voltage across the discharge resistor to a reference voltage; f) when the voltage across the discharge resistor falls below the reference voltage, outputting an indication that there is an open load fault in the test circuit.

12. The method of claim 11, wherein the step a) is performed simultaneously with the step b).

13. The method of claim 11, wherein the voltage across the discharge resistor V.sub.DIS is voltage-divided with a ratio A, and the reference voltage V.sub.REF is voltage-divided with a ratio B, so that the step f) compares a voltage $\frac{V_{\mathrm{DIS}}}{A}$ to a voltage $\frac{V_{\mathrm{REF}}}{B}.$

14. The method of claim 13, wherein a first test voltage-divider resistor has a resistance R.sub.test_1, a second test voltage-divider resistor has a resistance R.sub.test_2, a first vref voltage divider-resistor has a resistance R.sub.vref_1, a second voltage-divider resistor has a resistance R.sub.vref_2, the discharge resistor has a resistance R.sub.DIS, and the ratios A and B are defined as follows: $A=\frac{R_{\mathrm{test}\_1}}{R_{\mathrm{test}\_1}+R_{\mathrm{test}\_2}}$ $B=\frac{R_{\mathrm{test}\_1}}{R_{\mathrm{test}\_1}+R_{\mathrm{test}\_2}}.$

15. The method of claim 13, wherein the test circuit includes, in series between the first and second terminals, a constant resistance R.sub.SPK and a resistance R.sub.OPEN corresponding to open load faults in the test circuit; and wherein the discharge resistor has a resistance of R.sub.DIS, and $\frac{V_{\mathrm{REF}}}{B}$ corresponds to a value of R.sub.OPEN of R.sub.TH, R.sub.TH being defined as: $R_{\mathrm{TH}}=\left(\frac{B}{A}-1\right)\times R_{\mathrm{DIS}}.$

16. The method of claim 11, wherein the first LC filter and the second LC filter charge at the same rate.

17. The method of claim 11, wherein the reference voltage is proportional to the input voltage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 schematically shows an example of a prior art circuit for detecting an open load fault.

(2) FIG. 2 schematically shows an example of a circuit for detecting an open load fault.

(3) FIG. 3 schematically shows a portion of the example circuit of FIG. 2.

(4) FIG. 4A shows an example of a process for using the circuit of FIG. 2 to determine whether an open load fault is present.

(5) FIG. 4B shows an example of a timing diagram 414 for the circuit 200 of FIG. 2, corresponding to the example process of FIG. 4A.

(6) FIG. 5 schematically shows an example circuit which includes the circuit of FIG. 2 and the resistances R.sub.SPK and R.sub.OPEN described with respect to FIG. 3, along with structure for generating the reference voltage.

(7) FIG. 6 shows an example table of values for R.sub.OPEN in ohms (Ω) with corresponding values of discharge time t in milliseconds (ms).

DETAILED DESCRIPTION

(8) FIG. 2 schematically shows an example of a circuit 200 for detecting an open load fault. The circuit 200 of FIG. 2 shares various aspects with the circuit 100 of FIG. 1, so like reference numbers from FIG. 1 are carried forth into FIG. 2 for such items. The circuit 200 of FIG. 2 does not include various aspects of the circuit 100, including the input current 130 and input switch 120, the comparator 132 and comparator switch 122, and the output switch 152 and the connection between OUTN 152 and ground 112 via the output switch 152. As shown in FIG. 2, the OUTN node 146 is connected to a first terminal of a discharge resistor 202 with resistance R.sub.DIS and a first terminal of a first OUTN voltage-divider resistor 204. A second terminal of the discharge resistor 202 is connected to a first terminal of a discharge switch 206, which has its second terminal connected to the ground 112. The second terminal of the first OUTN voltage-divider resistor 204 is connected to a test voltage node 208. The test voltage node 208 is also connected to a first terminal of a second OUTN voltage-divider resistor 210 and to a first (for example, inverting) input to a comparator 212. A second terminal of the second OUTN voltage-divider resistor 210 is connected to a first terminal of a comparator switch 214, which has its second terminal connected to the ground 112. A reference voltage vref 216 is connected to a second (for example, non-inverting) input to the comparator 212, so that the voltage at the OUTN node 146, once divided, is compared to the reference voltage 216 when the comparator switch 214 is closed. As further detailed later, depending on the comparison based on the voltage at the OUTN node 114 and the reference voltage 216, the comparator 212 outputs an open load flag 218 which indicates whether an open load fault is detected. The circuit 200 of FIG. 2 can be implemented using, for example, a class D amplifier.

(9) FIG. 3 schematically shows a portion 300 of the example circuit 200 of FIG. 2. As shown in FIG. 3, the speaker 104 can be thought of as roughly equivalent to a pair of resistors connected in series between the OUTP terminal 102 and the OUTN terminal 138: a speaker resistance R.sub.SPKR 302 corresponds to a resistance between the terminals 102, 138 when the speaker 104 is functioning properly; and an open load resistance R.sub.OPEN 304 corresponds to an additional resistance between the terminals 102, 138 which is zero (0) when there is no unintended open circuit between the terminals 102, 138, and which is larger than a threshold resistance R.sub.TH (not shown) when there is an open load fault. Preferably, R.sub.DIS of the resistor 202 is much larger than R.sub.TH, and R.sub.TH is much larger than R.sub.SPK 302 (as further described below). Accordingly, R.sub.DIS>>R.sub.TH>>R.sub.SPK. The threshold resistance R.sub.TH is further described with respect to FIG. 5.

(10) FIG. 4A shows an example of a process 400 for using the circuit 200 of FIG. 2 to determine whether an open load fault is present. To determine whether there is an open load fault using the circuit 200 of FIG. 2, the circuit 200 injects voltage and measures voltage. This avoids using a dedicated current generator configured to produce a precise current which will result in particular expected outputs when there is no open load fault condition between the speaker terminals 102, 138. This also avoids using switches directly connected to the OUTP node 114 or the OUTN node 146, other than those forming the H bridge (OUTP high-side and low-side transistors 116, 118); because the OUTP node 114 and OUTN node 146 operate at high voltage, switches directly connecting to the OUTP node 114 or the OUTN node 146 will generally be isolated switches, which take more device surface area than non-isolated switches. Accordingly, as shown in FIG. 1, switches 120, 122 and 154 (the input switch 120, OUTP comparator switch 122 and OUTN comparator switch 154) are isolated switches. As shown in FIG. 2, switches 206 and 214 (the discharge switch 206 and comparator switch 214) connect to ground 112, meaning that switches 206 and 214 can be, and preferably are, non-isolated switches. Further, in embodiments in which the OUTP node 114 and OUTN node 146 connect to respective chip pins, switches 206 and 214 are connected to the OUTN node 146 via series resistances 202, 204 and 210 (the discharge resistor 202, first OUTN voltage-divider resistor 204 and second OUTN voltage-divider resistor 210). This means that switches 206 and 214 are protected against electrostatic discharge during handling of a chip containing the circuit 200.

(11) FIG. 4B shows an example of a timing diagram 414 for the circuit 200 of FIG. 2, corresponding to the example process of FIG. 4A. As shown in FIGS. 4A and 4B, initially, the OUTP high-side driver 126 and the OUTN high-side driver 156 enable the OUTP high-side transistor 116 and the OUTN high-side transistor 148, respectively, to couple the OUTP and OUTN LC filters 110, 144 to PVDD 124 in step 402. This results in the voltages at the OUTP node 114 and the OUTN node 146 being equal to PVDD 124, and to each other. In embodiments as shown in FIG. 4B, step 402 is implemented using a pulse width modulation (PWM)-like pattern of enabling the OUTP high-side transistor 116 and the OUTN high-side transistor 148 (using the OUTP high-side driver 126 and the OUTN high-side driver 156, respectively), to more gradually charge the LC filters 110, 144 and more gradually ramp the voltages at the OUTP terminal 102 and the OUTN terminal 138 of the speaker 104. This can be used to further lower the differential voltage across the speaker terminals 102, 138. In step 404, there is a wait for the LC filters 110, 144 to fully charge and stabilize. The capacitances of the OUTP capacitor 106 and the OUTN capacitor 140 are preferably equal (both C.sub.F, as shown in FIG. 3) and the inductances of the OUTP inductor 108 and the OUTN inductor 142 are preferably equal (both L.sub.F, as shown in FIG. 3), so that the LC filters 110, 144 charge at equal rates. As a result, there is little or no differential voltage across the speaker 104 (particularly using the PWM-like control pattern shown in FIG. 4B). This reduces the likelihood of voltage spikes across the speaker 104 and reduces the total deflection distance of the speaker membrane during the test process. Accordingly, the likelihood of damage to the speaker 104 during the test process is reduced. After the wait in step 404 for the LC filters 110, 144 to charge and stabilize, the voltages at the terminals 102, 138 are equal.

(12) In step 406, the OUTP high-side transistor 116 remains enabled (closed), the OUTN high-side transistor 148 is disabled (opened), and the discharge switch 206 is closed to provide a discharge path through the OUTN inductor 142 of the OUTN LC filter 144 to ground 112, via the discharge resistor 202. According to the superposition principle, the circuit portion 300 can be viewed as having the pseudo-dc voltage on the OUTP capacitor 106 shorted out (accordingly, the OUTP capacitor 106 shorted), so that only the OUTN capacitor 140 affects transient voltage at the OUTN node 146.

(13) This can also be viewed as the resistance of the speaker 104 R.sub.SPK and the open load resistance ROPEN, and the resistance of the discharge resistor 202 R.sub.DIS, forming a voltage divider. Steps 402 and 404 set up an initial state for the discharge phase, which corresponds to steps 406 and 408. The ratio of the total speaker 104 load (R.sub.SPK+R.sub.OPEN) to the discharge resistor 202 load R.sub.DIS determines the final voltage state at the OUTN node 146 following the discharge phase. If there is no open load fault condition, then the final voltage state at the OUTN node 146 will be close to PVDD 124 (the normal load R.sub.SPK is much smaller than the discharge resistor resistance R.sub.DIS, and therefore will generally see a small proportion of the total voltage drop across the various resistances; the low voltage drop also corresponds to low noise produced on the speaker). If there is an open load fault condition, the total speaker 104 load will be larger, making the final voltage state at the OUTN node 146 significantly less than PVDD 124.

(14) Accordingly, the OUTN capacitor 140 can be viewed as discharging across the OUTN inductor 142 and the discharge resistor 202, and across the speaker 104, as shown by the dotted lines 306 in FIG. 3. The OUTN capacitor 140 thus discharges across a total discharge resistance of (R.sub.SPK+R.sub.OPEN)∥R.sub.DIS (the symbol ∥ indicates parallel resistors). This makes the RC time constant τ for the OUTN capacitor 140:

(15) $\begin{array}{cc}\tau =C_F\times \frac{R_{\mathrm{DIS}}\times \left(R_{\mathrm{OPEN}}+R_{\mathrm{SPK}}\right)}{R_{\mathrm{DIS}}+\left(R_{\mathrm{OPEN}}+R_{\mathrm{SPK}}\right)}& \mathrm{Equation}1\end{array}$

(16) (If there is an open load fault, then R.sub.OPEN is much larger than R.sub.SPK, and the resistance across which the OUTN capacitor 140 discharges can be approximated as R.sub.OPEN∥R.sub.DIS; also, the inductances of the inductors 108, 142 are preferably chosen so that their effects on the discharge time will be low.) If normal load is present (no open load fault), the voltage at the OUTN node 146 will remain (almost) PVDD 124, (nearly) equal to the voltage at the OUTP node 114. However, if there is an open load fault, then the voltage at the OUTN node 146 will decrease. (Recall that OUTN high-side transistor 148 was opened, disconnecting OUTN node 146 from the input voltage 124, in step 406.) This is apparent in light of Ohm's Law (V=I×R) because the resistance R.sub.OPEN increases in an open load fault condition while the current is constant. A stabilized value of the voltage at the OUTN node 146 is related to PVDD 124 and the total discharge resistance (R.sub.SPK+R.sub.OPEN)∥R.sub.DIS. Accordingly, the voltage drop across the speaker 104, plus the voltage drop across the discharge resistor 202, will equal the total supplied voltage PVDD 124 (the voltage to which the OUTN capacitor 140 was charged). The voltage across the discharge resistor 202 equals the voltage at the OUTN node 146 V.sub.OUTN:

(17) $\begin{array}{cc}{V}_{\mathrm{OUTN}}=\mathrm{PVDD}\times \frac{R_{\mathrm{DIS}}}{R_{\mathrm{DIS}}+\left(R_{\mathrm{OPEN}}+R_{\mathrm{SPK}}\right)}& \mathrm{Equation}2\end{array}$

(18) Because V.sub.OUTN is proportional to PVDD, a reference voltage proportional to PVDD can be used to establish a fixed threshold R.sub.TH for determining an open load fault. The threshold resistance R.sub.TH is further described with respect to FIG. 5.

(19) In step 408, there is a wait of a specific discharge time (described below with respect to FIG. 5 and Equation 8) for the OUTN capacitor 140 to discharge. In step 410, after waiting for the OUTN capacitor 140 to discharge, the discharge switch remains closed, the comparator switch 214 is closed and the voltage at the test voltage node 208, which depends on V.sub.OUTN, is compared by the comparator 212 with a reference voltage 216 which is proportional to PVDD 124. In step 412, if the voltage at the test voltage node 208 is determined to be less than the reference voltage 216, then the comparator 212 will set the open load flag 218 to indicate an open load fault.

(20) FIG. 5 schematically shows an example circuit 500 which includes the circuit 200 of FIG. 2 and the resistances R.sub.SPK 302 and R.sub.OPEN 304 described with respect to FIG. 3, along with structure for generating the reference voltage 216. The input voltage PVDD 124 is connected to a first terminal of a first vref voltage-divider resistor 502, which has its second terminal connected to a vref node 504. The vref node 504 is also connected to an input (for example, inverting) of the comparator 212 to supply the reference voltage 216 to the comparator 212. The vref node 504 is also connected to a reference voltage switch 506, which is shown by way of example as a transistor having its drain connected to the vref node 504 and its source connected through a second vref voltage-divider resistor 510 to ground. Reference voltage switch 506 preferably is enabled (closed) by a same EN_COMP signal 508 as the comparator switch 214. Enabling the reference voltage switch 506 causes the input voltage PVDD 124 to divide across resistors 502 and 510 and connects the divided voltage, as the reference voltage 216 across resistor 510, to the comparator 212. There is also a control circuitry 512 for controlling the OUTP high-side driver 126, the OUTP low-side driver 128, the OUTN high-side driver 156, the OUTN low-side driver 158, the discharge switch 206, the reference voltage switch 506, and the comparator switch 214 (the latter two by providing the EN_COMP signal 508). The control circuitry 512 is also connected to the ground 112.

(21) In the example shown in FIG. 5, for a base voltage-divider resistance R (which cancels out in relevant calculations, as described below) the first OUTN voltage-divider resistor 204 equals 7R and the second OUTN voltage-divider resistor 210 equals R. Accordingly, the voltage at the test voltage node 208 is

(22) $V_{\mathrm{OUTN}}\times \frac{1}{8}.$
The first OUTN voltage-divider resistor 502 equals 7.2R and the second OUTN voltage-divider resistor 510 equals R. Accordingly, the voltage at the vref node 504 is

(23) $\mathrm{PVDD}\times \frac{1}{8.2}.$
Using equation 2, the comparison made by the comparator 212 can be described as follows (wherein, in Equation 3, CMPR is a function meaning compare the two input parameters shown between parentheses and separated by a comma):

(24) $\begin{array}{cc}\mathrm{CMPR}\left(\mathrm{PVDD}\times \frac{R_{\mathrm{DIS}}}{R_{\mathrm{DIS}}+\left(R_{\mathrm{OPEN}}+R_{\mathrm{SPK}}\right)}\times \frac{1}{8},\mathrm{PVDD}\times \frac{1}{8.2}\right),& \mathrm{Equation}3\end{array}$

(25) The resistance threshold R.sub.TH (a minimum open load resistance R.sub.OPEN which will cause a voltage at OUTN node 146 indicating an open load fault) can be determined by substituting R.sub.TH for R.sub.OPEN in Equation 3 and setting the reference voltage 216 equal to the voltage at the test voltage node 208:

(26) $\begin{array}{cc}\mathrm{PVDD}\times \frac{R_{\mathrm{DIS}}}{R_{\mathrm{DIS}}+\left(R_{\mathrm{TH}}+R_{\mathrm{SPK}}\right)}\times \frac{1}{8}=\mathrm{PVDD}\times \frac{1}{8.2}& \mathrm{Equation}4\\ \frac{R_{\mathrm{DIS}}}{R_{\mathrm{DIS}}+\left(R_{\mathrm{TH}}+R_{\mathrm{SPK}}\right)}=\frac{8}{8.2}& \mathrm{Equation}5\end{array}$

(27) A scale factor

(28) $k=\frac{8}{8.2}$
is a ration between a voltage-divider ratio of the voltage-divider resistors 204, 210 used to generate the voltage at the test voltage node 208 from V.sub.OUTN, and a voltage-divider ratio of the voltage-divider resistors 502, 510 used to generate the reference voltage 216. In the example shown in and described with respect to FIG. 5, the former ratio is

(29) $\frac{1}{8},$
and the latter ratio is

(30) $\frac{1}{8.2}.$
As can be seen from Equation 6, k<1. The scale factor k is further used below in determining the discharge time of step 408 (as described with respect to FIG. 4A).

(31) As shown in Equation 5, the resistance threshold R.sub.TH is independent of the input voltage PVDD 124 and the base voltage-divider resistance R. Because R.sub.TH and R.sub.DIS are much larger than R.sub.SPK (R.sub.TH+R.sub.SPK≈R.sub.TH), Equation 5 can be rearranged and approximated as shown in Equation 6. For example, if R.sub.DIS equals 4200Ω, then R.sub.TH≈102Ω.

(32) 0$\begin{array}{cc}{R}_{\mathrm{DIS}}\times \left(\frac{1}{k}-1\right)=R_{\mathrm{DIS}}\times \left(\frac{8.2}{8}-1\right)=R_{\mathrm{DIS}}\times \frac{\mathrm{.2}}{8}=R_{\mathrm{TH}}& \mathrm{Equation}6\end{array}$

(33) The discharge time of step 408 is based on the discharge time for the voltage at the OUTN node 146 to drop below a threshold voltage corresponding to R.sub.TH when there is an open load fault. Accordingly, the threshold voltage at the OUTN node 146 is a voltage which will result in the comparator 212 indicating an open load fault. This discharge time t for the voltage at the OUTN node 146 is determined as follows:

(34) $\begin{array}{cc}\mathrm{PVDD}-\mathrm{PVDD}\times \frac{R_{\mathrm{OPEN}}}{R_{\mathrm{OPEN}}+R_{\mathrm{DIS}}}\times \left(1-e^{-\frac{t}{\tau }}\right)=\mathrm{PVDD}\times \frac{1}{k}& \mathrm{Equation}7\\ t=-\tau \times \ln \left[k+\left(k-1\right)\times \frac{R_{\mathrm{DIS}}}{R_{\mathrm{OPEN}}}\right],& \mathrm{Equation}8\\ \mathrm{where}\tau \approx \frac{R_{\mathrm{OPEN}}\times R_{\mathrm{DIS}}}{R_{\mathrm{OPEN}}+R_{\mathrm{DIS}}}\times C_F& \end{array}$

(35) When R.sub.OPEN is less than R.sub.TH (R.sub.OPEN<R.sub.TH), there is no solution to Equation 8. When R.sub.OPEN equals R.sub.TH (R.sub.OPEN=R.sub.TH), t=∞. When R.sub.OPEN is greater than R.sub.TH, then the larger R.sub.OPEN is, the shorter the required discharge time t is for the voltage at the test voltage node 208 to fall below the voltage at the reference voltage node 504 (indicating the open load fault). Conversely, the closer R.sub.OPEN is to R.sub.TH, the longer the required discharge time t will be. For example, the discharge time for LC filters to charge and stabilize (step 404 in FIG. 4A) can be 2 ms, and the discharge time for the OUTN capacitor to discharge (step 408 in FIG. 4A), as discussed with respect to FIG. 5 and Equation 8, can be 6 ms.

(36) Accordingly, if R.sub.OPEN is large compared to R.sub.TH, settle time (total RC discharge time) will be long, but open load fault detection time (relating, in part, to initial discharge rate) will be short. Also, if R.sub.OPEN is near R.sub.TH, settle time will be short, but open load fault detection time will be long.

(37) FIG. 6 shows an example table of values for R.sub.OPEN in ohms (Ω) with corresponding values of discharge time t in milliseconds (ms). The values in the table shown in FIG. 6 are dependent on the following assumed values: R.sub.TH=120Ω;

(38) $k=\frac{8}{8.2};$
R.sub.DIS=4800; and C.sub.F=3 μF (C.sub.F is the capacitance of the OUTP capacitor 106 and the OUTN capacitor 140). Note that if the speaker 104 is completely disconnected, such as if one of the terminals 102, 138 is disconnected, then R.sub.OPEN will be effectively infinite. However, as shown by the values in FIG. 6, a “hard open” fault (complete disconnection, corresponding to infinite resistance R.sub.OPEN) can be asserted quickly; and generally, relatively high resistance open load faults can be asserted quickly, before V.sub.OUTN settles. This is because, though V.sub.OUTN has not yet settled, the voltage at the test voltage node 208 has already fallen below the reference voltage 216. Preferably, a wait time longer than a typical or expected minimum required discharge time is used to avoid false negative results (false indications that there is no open load fault).

(39) Modifications are possible in the described embodiments, and other embodiments are possible, within the scope of the claims.

(40) In some embodiments, other voltage-divider values are used than those described above.

(41) In some embodiments, other open load detection threshold resistances R.sub.TH are used than those described above.

(42) In some embodiments, low-side transistors and low-side drivers are not used.

(43) In some embodiments, the no-fault resistance of the speaker (R.sub.SPK) is included in calculations of threshold resistance R.sub.TH and minimum discharge time