Method for managing the startup of a phase-locked loop and corresponding integrated circuit

Abstract

The operation of the phase-locked loop includes a startup phase where a reference signal having a duty cycle of 50% is applied to a phase comparator of the loop. A first divider of an output signal of the voltage-controlled oscillator of the loop is reset at each first type signal edge of the reference signal. The phase comparator receives the reference signal and a feedback signal from the first divider and generates a control pulse at each second type signal edge of the reference signal that causes a control voltage of the oscillator to increase.

Claims

1. A method for operating a phase-locked loop (PLL) circuit, comprising: delivering a reference signal for a phase comparator of the PLL circuit; resetting a first divider of an output signal of a voltage-controlled oscillator of the PLL circuit at each first type signal edge of the reference signal; outputting by the phase comparator, in response to the reference signal and a feedback signal derived from an output of said first divider, a control pulse at each second type signal edge of the reference signal; and during startup, increasing a control voltage of the voltage-controlled oscillator in response to each control pulse by applying, in response to the control pulse, a pre-charging current to a resistive capacitive filter connected at an input of the voltage-controlled oscillator; after startup is complete, ceasing to apply the pre-charging current to the resistive capacitive filter in response to each control pulse.

2. The method according to claim 1, wherein delivering said reference signal comprises dividing an initial reference signal by two, and wherein said feedback signal is the output of the first divider divided by two.

3. A method for operating a phase-locked loop (PLL) circuit, comprising: delivering a reference signal for a phase comparator of the PLL circuit; resetting a first divider of an output signal of a voltage-controlled oscillator of the PLL circuit at each first type signal edge of the reference signal; outputting by the phase comparator, in response to the reference signal and a feedback signal derived from an output of said first divider, a control pulse at each second type signal edge of the reference signal; and increasing a control voltage of the voltage-controlled oscillator in response to each control pulse; wherein increasing the control voltage of the voltage-controlled oscillator comprises applying, in response to the control pulse, a pre-charging current to a resistive capacitive filter connected at an input of the voltage-controlled oscillator; wherein the resistive capacitive filter comprises: a first branch connected between said input of the voltage-controlled oscillator and ground and containing a resistive network connected in series with a first capacitor having a first capacitance, said resistive network containing a first resistor connected between said input of the voltage-controlled oscillator and an intermediate node and having a first resistance, and a second resistor connected between the intermediate node and the first capacitor and having a second resistance; and a second branch connected between said input of the voltage-controlled oscillator and ground and containing a second capacitor having a second capacitance; the first capacitance being equal to a value that is A times the second capacitance, and the first resistance being equal to a value that is A times the second resistance; and wherein said pre-charging current is applied to said intermediate node.

4. The method according to claim 1, further comprising terminating startup when a duration of the control pulse is less than a few percent of a product of a period of the output signal of the voltage-controlled oscillator and a division ratio of the first divider.

5. The method according to claim 4, further comprising, in response to terminating startup, connecting the output of the phase comparator to a charge pump circuit configured to generate the control voltage of the voltage-controlled oscillator.

6. The method according to claim 5, further comprising performing a last reset of the first divider on the first type signal edge of the reference signal following terminating startup.

7. The method according to claim 4, wherein delivering said reference signal comprises dividing an initial reference signal by two, and wherein said feedback signal is the output of the first divider divided by two, and further comprising, in response to terminating startup, delivering the initial reference signal to the phase comparator, and delivering the output signal of the first divider as the feedback signal to the phase comparator.

8. The method according to claim 7, further comprising performing a last reset of the first divider on the first type signal edge of the reference signal following terminating startup.

9. A phase-locked loop (PLL) circuit, comprising: a phase comparator; a voltage-controlled oscillator; a first divider connected between an output of the voltage-controlled oscillator and a first input of the phase comparator; a delivery circuit configured to deliver, in a startup phase of the PLL circuit, a reference signal to a second input of the phase comparator; a reset circuit configured, in said startup phase, to reset the first divider at each first type signal edge of the reference signal; wherein the phase comparator is configured, in said startup phase, to deliver a control pulse at each second type signal edge of the reference signal; and a control circuit configured to: during the startup phase, increase a control voltage of the voltage-controlled oscillator during said control pulse by applying, in response to the control pulse, a pre-charging current to a resistive capacitive filter connected at an input of the voltage-controlled oscillator, but after the startup phase is complete, ceasing to apply the pre-charging current to the resistive capacitive filter in response to each pulse.

10. A phase-locked loop (PLL) circuit, comprising: a phase comparator; a voltage-controlled oscillator; a first divider connected between an output of the voltage-controlled oscillator and a first input of the phase comparator; a delivery circuit configured to deliver, in a startup phase of the PLL circuit, a reference signal to a second input of the phase comparator; a reset circuit configured, in said startup phase, to reset the first divider at each first type signal edge of the reference signal; wherein the phase comparator is configured, in said startup phase, to deliver a control pulse at each second type signal edge of the reference signal; and a control circuit configured to increase a control voltage of the voltage-controlled oscillator during said control pulse; wherein the delivery circuit comprises: an input configured to receiving an initial reference signal; a divide-by-two divider connected to said input; and an output configured to deliver the initial reference signal divided by two as reference signal during said startup phase, and another divide-by-two divider active during said startup phase and connected between the output of the first divider and the first input of the phase comparator.

11. A phase-locked loop (PLL) circuit, comprising: a phase comparator; a voltage-controlled oscillator; a first divider connected between an output of the voltage-controlled oscillator and a first input of the phase comparator; a delivery circuit configured to deliver, in a startup phase of the PLL circuit, a reference signal to a second input of the phase comparator; a reset circuit configured, in said startup phase, to reset the first divider at each first type signal edge of the reference signal; wherein the phase comparator is configured, in said startup phase, to deliver a control pulse at each second type signal edge of the reference signal; and a control circuit configured to increase a control voltage of the voltage-controlled oscillator during said control pulse; wherein the control circuit comprises: a current source configured to generate a pre-charging current that is selectively applied, in response to said control pulse, to a resistive capacitive filter connected at the input of the voltage-controlled oscillator; wherein the resistive capacitive filter comprises: a first branch connected between said input of the voltage-controlled oscillator and ground and containing a resistive network connected in series with a first capacitor having a first capacitance, said resistive network containing a first resistor connected between said input of the oscillator and an intermediate node and having a first resistance, and a second resistor connected between the intermediate node and the first capacitor and having a second resistance; and a second branch connected between said input of the voltage-controlled oscillator and ground and containing a second capacitor having a second capacitance; wherein the first capacitance is equal to a value A times the second capacitance, and wherein the first resistance is equal to a value A times the second resistance; and wherein the current source is connected to said intermediate node.

12. A phase-locked loop (PLL) circuit, comprising: a phase comparator; a voltage-controlled oscillator; a first divider connected between an output of the voltage-controlled oscillator and a first input of the phase comparator; a delivery circuit configured to deliver, in a startup phase of the PLL circuit, a reference signal to a second input of the phase comparator; a reset circuit configured, in said startup phase, to reset the first divider at each first type signal edge of the reference signal; wherein the phase comparator is configured, in said startup phase, to deliver a control pulse at each second type signal edge of the reference signal; a control circuit configured to increase a control voltage of the voltage-controlled oscillator during said control pulse; and a detection circuit configured to detect an end of the startup phase.

13. The circuit according to claim 12, wherein the detection circuit senses one of a duration of the control pulse and a type of pulse signal delivered by the phase comparator in order to detect end of the startup phase.

14. The circuit according to claim 13, wherein the detection circuit is further configured generate a signal indicating the end of the startup phase when the duration of the control pulse is less than a few percent of a product of a period of the output signal of the voltage-controlled oscillator and a division ratio of the first divider.

15. The circuit according to claim 12, further comprising a switching circuit configured, when the startup phase has ended, to connect the output of the phase comparator to a charge pump circuit which generates the control voltage of the voltage-controlled oscillator.

16. The circuit according to claim 15, wherein the reset circuit is configured, when the startup phase has ended, to perform a last reset of the first divider on the first type signal edge of the reference signal following the end of the startup phase.

17. The circuit according to claim 12, wherein the delivery circuit comprises: an input configured to receiving an initial reference signal; a divide-by-two divider connected to said input; and an output configured to deliver the initial reference signal divided by two as reference signal during said startup phase, and further comprising another divide-by-two divider active during said startup phase and connected between the output of the first divider and the first input of the phase comparator; wherein the delivery circuit is configured, when the startup phase has ended, to deliver the initial reference signal to the phase comparator; a control circuit configured to deactivate said other divide-by-two divider, such that a feedback signal delivered to the phase comparator is the output signal of the first divider.

18. The circuit according to claim 17, wherein the reset circuit is configured, when the startup phase has ended, to perform a last reset of the first divider on the first type signal edge of the reference signal following the end of the startup phase.

19. The method according to claim 3, further comprising terminating startup when a duration of the control pulse is less than a few percent of a product of a period of the output signal of the voltage-controlled oscillator and a division ratio of the first divider.

20. The method according to claim 19, further comprising, in response to terminating startup, connecting the output of the phase comparator to a charge pump circuit configured to generate the control voltage of the voltage-controlled oscillator.

21. The method according to claim 20, further comprising performing a last reset of the first divider on the first type signal edge of the reference signal following terminating startup.

22. The method according to claim 19, wherein delivering said reference signal comprises dividing an initial reference signal by two, and wherein said feedback signal is the output of the first divider divided by two, and further comprising, in response to terminating startup, delivering the initial reference signal to the phase comparator, and delivering the output signal of the first divider as the feedback signal to the phase comparator.

23. The method according to claim 22, further comprising performing a last reset of the first divider on the first type signal edge of the reference signal following terminating startup.

24. The circuit according to claim 11, further comprising a detection circuit configured to detect an end of the startup phase.

25. The circuit according to claim 24, wherein the detection circuit senses one of a duration of the control pulse and a type of pulse signal delivered by the phase comparator in order to detect end of the startup phase.

26. The circuit according to claim 25, wherein the detection circuit is further configured generate a signal indicating the end of the startup phase when the duration of the control pulse is less than a few percent of a product of a period of the output signal of the voltage-controlled oscillator and a division ratio of the first divider.

27. The circuit according to claim 24, further comprising a switching circuit configured, when the startup phase has ended, to connect the output of the phase comparator to a charge pump circuit which generates the control voltage of the voltage-controlled oscillator.

28. The circuit according to claim 27, wherein the reset circuit is configured, when the startup phase has ended, to perform a last reset of the first divider on the first type signal edge of the reference signal following the end of the startup phase.

29. The circuit according to claim 24, wherein the delivery circuit comprises: an input configured to receiving an initial reference signal; a divide-by-two divider connected to said input; and an output configured to deliver the initial reference signal divided by two as reference signal during said startup phase, and further comprising another divide-by-two divider active during said startup phase and connected between the output of the first divider and the first input of the phase comparator; wherein the delivery circuit is configured, when the startup phase has ended, to deliver the initial reference signal to the phase comparator; a control circuit configured to deactivate said other divide-by-two divider, such that a feedback signal delivered to the phase comparator is the output signal of the first divider.

30. The circuit according to claim 29, wherein the reset circuit is configured, when the startup phase has ended, to perform a last reset of the first divider on the first type signal edge of the reference signal following the end of the startup phase.

31. The circuit according to claim 9, wherein the delivery circuit comprises: an input configured to receiving an initial reference signal; a divide-by-two divider connected to said input; and an output configured to deliver the initial reference signal divided by two as reference signal during said startup phase, and further comprising another divide-by-two divider active during said startup phase and connected between the output of the first divider and the first input of the phase comparator.

32. The circuit according to claim 9, wherein the resistive capacitive filter comprises: a first branch connected between said input of the voltage-controlled oscillator and ground and containing a resistive network connected in series with a first capacitor having a first capacitance, said resistive network containing a first resistor connected between said input of the oscillator and an intermediate node and having a first resistance, and a second resistor connected between the intermediate node and the first capacitor and having a second resistance; and a second branch connected between said input of the voltage-controlled oscillator and ground and containing a second capacitor having a second capacitance; wherein the first capacitance is equal to a value A times the second capacitance, and wherein the first resistance is equal to a value A times the second resistance; and wherein a current source is connected to said intermediate node to deliver the pre-charge current.

33. The circuit according to claim 9, further comprising a detection circuit configured to detect an end of the startup phase.

34. The circuit according to claim 33, wherein the detection circuit senses one of a duration of the control pulse and a type of pulse signal delivered by the phase comparator in order to detect end of the startup phase.

35. The circuit according to claim 34, wherein the detection circuit is further configured generate a signal indicating the end of the startup phase when the duration of the control pulse is less than a few percent of a product of a period of the output signal of the voltage-controlled oscillator and a division ratio of the first divider.

36. The circuit according to claim 33, further comprising a switching circuit configured, when the startup phase has ended, to connect the output of the phase comparator to a charge pump circuit which generates the control voltage of the voltage-controlled oscillator.

37. The circuit according to claim 36, wherein the reset circuit is configured, when the startup phase has ended, to perform a last reset of the first divider on the first type signal edge of the reference signal following the end of the startup phase.

38. The circuit according to claim 33, wherein the delivery circuit comprises: an input configured to receiving an initial reference signal; a divide-by-two divider connected to said input; and an output configured to deliver the initial reference signal divided by two as reference signal during said startup phase, and further comprising another divide-by-two divider active during said startup phase and connected between the output of the first divider and the first input of the phase comparator; wherein the delivery circuit is configured, when the startup phase has ended, to deliver the initial reference signal to the phase comparator; a control circuit configured to deactivate said other divide-by-two divider, such that a feedback signal delivered to the phase comparator is the output signal of the first divider.

39. The circuit according to claim 38, wherein the reset circuit is configured, when the startup phase has ended, to perform a last reset of the first divider on the first type signal edge of the reference signal following the end of the startup phase.

40. The circuit according to claim 10, wherein the control circuit comprises: a current source configured to generate a pre-charging current that is selectively applied, in response to said control pulse, to a resistive capacitive filter connected at the input of the voltage-controlled oscillator.

41. The circuit according to claim 40, wherein the resistive capacitive filter comprises: a first branch connected between said input of the voltage-controlled oscillator and ground and containing a resistive network connected in series with a first capacitor having a first capacitance, said resistive network containing a first resistor connected between said input of the oscillator and an intermediate node and having a first resistance, and a second resistor connected between the intermediate node and the first capacitor and having a second resistance; and a second branch connected between said input of the voltage-controlled oscillator and ground and containing a second capacitor having a second capacitance; wherein the first capacitance is equal to a value A times the second capacitance, and wherein the first resistance is equal to a value A times the second resistance; and wherein the current source is connected to said intermediate node.

42. The circuit according to claim 10, further comprising a detection circuit configured to detect an end of the startup phase.

43. The circuit according to claim 42, wherein the detection circuit senses one of a duration of the control pulse and a type of pulse signal delivered by the phase comparator in order to detect end of the startup phase.

44. The circuit according to claim 43, wherein the detection circuit is further configured generate a signal indicating the end of the startup phase when the duration of the control pulse is less than a few percent of a product of a period of the output signal of the voltage-controlled oscillator and a division ratio of the first divider.

45. The circuit according to claim 42, further comprising a switching circuit configured, when the startup phase has ended, to connect the output of the phase comparator to a charge pump circuit which generates the control voltage of the voltage-controlled oscillator.

46. The circuit according to claim 45, wherein the reset circuit is configured, when the startup phase has ended, to perform a last reset of the first divider on the first type signal edge of the reference signal following the end of the startup phase.

47. The circuit according to claim 42, wherein the delivery circuit comprises: an input configured to receiving an initial reference signal; a divide-by-two divider connected to said input; and an output configured to deliver the initial reference signal divided by two as reference signal during said startup phase, and further comprising another divide-by-two divider active during said startup phase and connected between the output of the first divider and the first input of the phase comparator; wherein the delivery circuit is configured, when the startup phase has ended, to deliver the initial reference signal to the phase comparator; a control circuit configured to deactivate said other divide-by-two divider, such that a feedback signal delivered to the phase comparator is the output signal of the first divider.

48. The circuit according to claim 47, wherein the reset circuit is configured, when the startup phase has ended, to perform a last reset of the first divider on the first type signal edge of the reference signal following the end of the startup phase.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Other advantages and features of the invention will become apparent upon examining the detailed description of the completely non-limiting embodiments and modes of implementation of the invention and the appended drawings, in which:

(2) FIG. 1 shows a diagram of a phase-locked loop circuit;

(3) FIG. 2 is a diagram for a filter circuit; and

(4) FIG. 3 is a timing diagram illustrating a mode of implementation of the method for managing the operation of the loop PLL.

DETAILED DESCRIPTION

(5) In FIG. 1, the reference PLL denotes a phase-locked loop circuit including an input terminal BE for receiving an initial reference signal CKin and an output terminal BS for delivering the output signal CK.sub.VCO generated by a voltage-controlled oscillator VCO.

(6) By way of example, the frequency of the initial reference signal CKin may be equal to 16 MHz, whereas the frequency of the output signal CK.sub.VCO may be equal to 832 MHz.

(7) Moreover, the output terminal BS of the phase-locked loop PLL is connected to the input of a first divider DV1, for example a fractional divider, configured to divide the signal CK.sub.VCO delivered by the local oscillator VCO by N.

(8) The division ratio N is equal to the ratio between the frequency of the signal CK.sub.VCO and the frequency of the initial reference signal CKin.

(9) By way of example, in this case, this division ratio is equal to 800/16, that is to say 52. This divide-by-N divider has a conventional structure that is known per se, and is typically formed by a counter that is able to be reset by virtue of receiving a reset signal or pulse IMPRST on its reset input RST.

(10) The output signal of the first divider is referenced CKfb.

(11) The phase-locked loop PLL involves a startup phase or step at the end of which the reference signal delivered at the input of the phase comparator PFD (having a conventional and known structure) of the loop and the signal CKfb are virtually synchronized. Of course, when the reference signal and the signal CKfb are virtually synchronized, the reference signal and the output signal CK.sub.VCO are also virtually synchronized.

(12) The end of this startup phase occurs here, in this example, when a logic signal ENST has for example the logic value “1”.

(13) It is now assumed in this example that the initial reference signal CKin has any duty cycle, in particular other than 50%.

(14) For this purpose, the loop PLL comprises a delivery circuit MDV configured to deliver the reference signal CKin/2, which is a division by two of the initial reference signal CKin, on the second input E2 of the phase comparator PFD.

(15) For this purpose, the delivery circuit in this case contains, for example, a divide-by-two divider, DV2A, which is in fact a counter, connected to the input terminal BE and delivering the reference signal CKin/2.

(16) The delivery circuit MDV moreover contains a first multiplexer Mux1, controlled by the signal ENST and receiving, on the one hand, the reference signal CKin/2 and the initial reference signal CKin.

(17) During the startup phase, that is to say when the logic signal ENST has the logic value “0”, the multiplexer Mux1 delivers, on the input E2, the initial reference signal divided by two, which thus forms the reference signal received on the second input E2 of the phase comparator PFD.

(18) The feedback signal delivered on the first input E1 of the phase comparator PFD comes from a second multiplexer Mux2 that is also controlled by the signal ENST.

(19) The output signal of the first divider CKfb is delivered to a first input of the second multiplexer Mux2.

(20) The second input of the second multiplexer Mux2 receives the signal CKfb/2 delivered by another divide-by-two divider DV2B and that therefore results from the division by two of the signal CKfb.

(21) Thus, in this example, during the startup phase of the loop PLL, since the input E2 of the phase comparator receives the reference signal CKin/2, the feedback signal delivered on the first input E1 of the phase comparator is the signal CKfb/2.

(22) The phase comparator PFD, as is conventional, depending on the signals present at its two inputs, delivers either a control pulse UP configured to increase the control or command voltage at the input of the oscillator VCO or a control pulse DOWN configured to reduce this control voltage.

(23) The loop PLL moreover contains a resistive capacitive filter FLT having a node ND1 connected to the command or control input of the voltage-controlled oscillator VCO.

(24) The phase-locked loop PLL moreover contains a charge pump circuit CHP, having a structure that is conventional and known per se, configured to receive the two control pulses UP and DOWN, and delivering a current to the resistive capacitive filter FLT, thereby producing the control voltage Vcontrol able to be applied to the input of the oscillator.

(25) That being said, in this embodiment, the phase comparator PFD is connected to the input of the charge pump circuit CHP by a set of first switches SW1 able to be commanded by the logic signal ENST.

(26) In another embodiment, the set of first switches SW1 may be replaced by logic gates one input of which is connected to the logic signal ENST that makes it possible to open the switches internal to the charge pump circuit CHP.

(27) Thus, in this embodiment, when the phase-locked loop is in its startup phase (ENST=0, for example), the switches SW1 are opened, disconnecting the charge pump circuit CHP from the outputs of the phase comparator PFD.

(28) As illustrated in FIG. 2, the filter FLT in this case contains a first branch BR1 connected between the node ND1 and ground GND and a second branch BR2 also connected between the node ND1 and ground GND.

(29) The first branch comprises a resistive network R connected in series with a first capacitor C1.

(30) The resistive network R contains a first resistor R1 connected between the node ND1 and an intermediate node ND2 and a second resistor R2 connected between the intermediate node ND2 and the first capacitor C1.

(31) For the sake of simplification, C1, C2, R1 and R2 will also respectively denote the capacitance of the first capacitor C1, the capacitance of the second capacitor C2, the resistance of the first resistor R1 and the resistance of the second resistor R2.

(32) In this example, the capacitance C1 of the first capacitor C1 is equal to a value of a constant A times the capacitance C2 of the second capacitor C2. By way of indication, the value of A is of the order of 10.

(33) The resistance R1 of the first resistor R1 is for its part equal to a value of A times the resistance R2 of the second resistor R2.

(34) The product R2C1 is hence equal to the product R1C2, that is to say to A times the product R2C2.

(35) Plus, during the startup phase, a pre-charging current Ip will be applied to the intermediate node ND2.

(36) Plus, since C1 is equal to aC2, it will take the same time to pre-charge C1 and C2, this time being equal to the constant of the filter divided by A.

(37) As illustrated in FIG. 1, this pre-charging current Ip comes from a current source SC able to be activated by way of a second switch SW2 commanded by the output of a logic AND gate, referenced PL.

(38) This gate PL receives the control pulse IMP of the signal UP on a first input, and the signal ENST inverted by an inverter INV on a second input.

(39) During the startup phase, the signal ENST is at “0”, and it is at “1” after the startup phase.

(40) During the startup phase, the second switch SW2 is thus commanded by the pulses of the signal UP, whereas, after the startup phase, the second switch SW2 is always open.

(41) More precisely, during the startup phase, if the signal UP is at the high level (representative of a pulse IMP), the switch SW2 is closed and the current source delivers the pre-charging current Ip on the intermediate node ND2.

(42) And this lasts for as long as the signal UP is at 1, that is to say for as long as the control pulse IMP is present.

(43) By contrast, as soon as the pulse IMP disappears (signal UP at zero), the switch SW2 is opened and no pre-charging current is delivered to the node ND2.

(44) The capacitive filter FLT therefore charges during the pulses IMP, and these charging operations make it possible to increase the control voltage at the input of the oscillator VCO, thereby consequently making it possible to increase the frequency of the output signal of this oscillator.

(45) The current source SC and the filter FLT therefore form part of control circuit configured so as to increase the control voltage of the oscillator during said control pulse IMP.

(46) The first divider DV1 is reset, as indicated above, by applying a reset pulse IMPRST to the reset input RST of the divider.

(47) This reset pulse IMPRST is obtained, in the startup phase, by reset circuit MRST in response to each rising signal edge FM of the reference signal, which is in this case the signal CKin/2.

(48) Of course, it would have been possible to perform this resetting on each falling signal edge of the signal CKin/2.

(49) Moreover, as will be seen in more detail below, once the startup phase has ended, the reset circuit MRST will deliver a last reset pulse on the first rising signal edge of the reference signal, which will this time be the signal CKin, that follows the end of the startup phase.

(50) The reset circuit MRST may easily be produced by way of logic circuits.

(51) Moreover, the integrated circuit IC incorporating the phase-locked loop PLL also contains detection circuit MDT configured so as to detect the end of the startup phase and therefore deliver the logic value 1 to the signal ENST.

(52) The end of the startup phase is considered to be reached when the duration T of the control pulse IMP corresponding to the high state of the “up” signal is less than a few percent of the product of the nominal period T.sub.CKVCO of the output signal of the oscillator VCO and the division ratio N.

(53) By way of example, this threshold may be taken to be equal to 2%.

(54) Therefore, according to a first possibility, in order to detect this startup phase end condition, the detection circuit MDT may be configured so as to count the number of signal edges of the signal CK.sub.VCO during the duration of the pulse IMP.

(55) According to another possible embodiment, the detection circuit MDT may contain a low-pass filter receiving the signal UP and the time constant of which is linked to said threshold of a few percent.

(56) Depending on whether or not the output of this filter delivers a high signal, the detection circuit MDT will deliver either the logic value “0” or the logic value “1” of the signal ENST.

(57) As a variant, the end of the startup phase may also be considered to be reached when the first control pulse corresponding to the high state of the signal “DOWN” is detected. Reference is now made more particularly to FIG. 3 in order to illustrate one mode of implementation of the method for managing the operation of the loop PLL illustrated in the previous figures.

(58) This FIG. 3 has the form of a timing diagram.

(59) The first line of FIG. 3 shows the initial reference signal CKin which, as is seen, has a duty cycle other than 50%.

(60) The second line shows the reference signal CKin/2, resulting from the division by two of the initial reference signal, and which this time has a duty cycle that is equal to 50%.

(61) This signal CKin/2, as has been explained above, is the reference signal delivered on the second input E2 of the phase comparator PFD.

(62) Moreover, it is seen that a reset pulse IMPRST that resets the first divider DV1, that is to say that resets the counter forming this first divider to 0, is emitted by the reset circuit MRST at each rising signal edge of the reference signal CKin/2.

(63) Moreover, on each falling signal edge of the reference signal CKin/2, the phase comparator PFD compares the phase of the reference signal CKin/2 with the phase of the feedback signal CKFB/2, and consequently delivers the control pulse IMP of the signal UP.

(64) This pulse IMP, when it is present, makes it possible to apply the pre-charging current Ip to the intermediate node ND2 of the filter FLT.

(65) As this startup phase proceeds, it is noted that the duration of the pulse IMP of the signal UP decreases, since the output frequency of the signal CK.sub.VCO increases.

(66) In addition, as indicated above, when the duration T of the pulse IMP is less than or equal to 2% of the product of the division ratio N and the period TCK.sub.VCO of the oscillator signal, the control signal ENST changes to 1, marking the end of the startup phase.

(67) At this time, the first multiplexer Mux1 delivers the initial reference signal CKin, which becomes the reference signal, on the second input E2 of the phase comparator.

(68) Moreover, the feedback signal delivered on the first input E1 of the phase comparator PFD becomes the signal CKfb coming directly from the divider (that is to say without having been divided by two beforehand).

(69) At the same time, the switches SW1 are closed, connecting the two outputs (respectively delivering the two signals UP and DOWN) of the phase comparator PFD to the inputs of the charge pump circuit, so as to resume the conventional operation of a phase-locked loop.

(70) The switch SW2 is opened, interrupting the application of the pre-charging current Ip.

(71) The current for regulating the control voltage Vcontrol of the local oscillator VCO is this time the current Icp delivered by the charge pump circuit.

(72) That being said, in order to speed up the synchronization of the signal CK.sub.VCO and of the reference signal CKin, the reset circuit MRST, as indicated above, performs a last reset of the first divider DV1 upon the first rising signal edge of the reference signal CKin that follows the end of the startup phase.

(73) The phase-locked loop will then be ready to deliver its output signal after a few cycles.

(74) This output signal may serve, for example, as a clock signal for a microprocessor.