METHOD FOR GENERATING FULLY DIGITAL HIGH-RESOLUTION FEEDBACK PWM SIGNAL

Abstract

A method for generating digital, high resolution pulse width modulation (PWM) signals and a digital feedback correction method suited to the method of generation of the digital, high resolution PWM signals intended for using in feed forward systems, feedback systems and combined feed forward system and feedback system are provided.

Claims

1. A method for generating digital, high resolution pulse width modulation signals, used in feed forward systems, feedback systems and combined feed forward and feedback systems, and a digital feedback correction method suited to the method, comprising the steps of: a) reading current signal values, wherein the current signal values are fed into a system by a user; b) calculating voltage values of the current signal values at a feed forward block (FFB); c) calculating pulse widths at a pulse width calculation block (PWCB) by comparing the voltage values with a high frequency triangular wave; d) calculating counter and tap values of a digital integrated circuit corresponding to the pulse widths by using sample numbers and values; e) sampling a disturbed output signal y(t) by an analog digital converter (ADC); f) transmitting the disturbed output signal y(t) to a proportional-integral-derivative (PID) controller to calculate a correction value at the PID controller; g) correcting the counter and tap values calculated in step d) by using the correction value; h) transmitting the counter and tap values to output to generate a pulse width modulation (PWM) signal; i) applying a delay to increasing and decreasing edges of the PWM signal at an output by IO delay elements to increase a signal resolution with centre-aligned or edge-aligned signals.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0027] FIG. 1 shows a block diagram view of the combined feed forward and feedback system used in the PWM modulation according to the invention.

[0028] FIG. 2 shows a block diagram view of the feedback system used in the PWM modulation.

[0029] FIG. 3 shows a block diagram view of the feed forward system used in the PWM modulation.

[0030] FIG. 4A shows a view of the PWM signal generated by centre—aligned counter and tap values.

[0031] FIG. 4B shows a view of the PWM signal generated by edge—aligned counter and tap values.

[0032] FIG. 5 shows a view of the feed forward and feedback system in centre—aligned PWM signal generation.

[0033] FIG. 6 shows a view of the feed forward and feedback system in edge—aligned PWM signal generation.

[0034] FIG. 7 shows a view of the feed forward and feedback system for full bridge in centre—aligned PWM signal generation.

LIST OF REFERENCE SYMBOLS

[0035] u(t): Desired Signal [0036] y(t): Disturbed Output Signal [0037] FFB: Feed Forward Block [0038] FB: Feedback Block [0039] PWCB: Pulse Width Calculation Block [0040] M: Pulse Width Modulator [0041] STCB: Signal and Tap Calculation Block [0042] FBS: Full Bridge Switching [0043] ADC: Analog Digital Converter [0044] PID: Proportional—Integral—Derivative Controller [0045] S: Current/Voltage Sensor [0046] F.sub.counter FPGA Counter Clock Frequency [0047] F.sub.PWM: PWM Frequency [0048] IO: IO Delay Element

DETAILED DESCRIPTION OF THE EMBODIMENTS

[0049] This detailed description discloses a method for generating fully digital, high resolution feedback pulse width modulation (PWM) signal by the way of the IO Delay element (IO) presented according to the invention and preferred embodiments of the invention in order to facilitate a better understanding of the present invention.

[0050] The invention typically relates to a method for generating digital, high resolution pulse width modulation (PWM) signals and a digital feedback correction method suited to the method of generation intended for use in feed forward systems, feedback systems and combined feed forward and feedback systems, respectively shown in FIG. 1, FIG. 2 and FIG. 3. The said method can be used in full bridge D class power amplifiers, AC—DC, DC—DC, DC—AC convertors and all systems driven by PWM signals.

[0051] In standard PWM, PWM pulses are generated by use of analog mixers, while in digital generation output widths are created by comparing FPGAs (Field Programmable Gate Arrays) with a variable calculated according to the clock used on digital integrated circuits. Therefore, if the resolution of pulse widths provided in the standard method are calculated at the single edge of the clock signal, it can have a single period or two half—periods as increase and decrease at both edges.

[0052] In the method according to the invention, the lowest resolution is increased depending on the control bit number of input—output delay (IOD) elements by means of IOD elements. F.sub.tap value is calculated at the signal and tap calculation block (STCB) as IOD tap frequency by using the below formula:

F.sub.tap=F.sub.IOdelayclock×(2.sup.nbit+2)  (1)

[0053] Delays in the method according to the invention can be center—aligned as shown in FIG. 4A or edge—aligned as shown in FIG. 4B. FIG. 4A shows a1 logic at 0 as the total of a1 counter and a1_tap values with a1_counter as the counter value used by FPGA and a1_tap as the last bit value counted at the counter. a1_counter is counted with the counter used by the digital integrated circuit—FPGA—and the last counted bit is delayed by tap counter at the rate of a1_tap. FIG. 4A shows b1 logic at 1 as the total of b1 counter and b1 tap values. b1 counter is counted with the counter used by FPGA and the last counted bit is delayed by tap counter at the rate of b1 tap.

[0054] Current/voltage output values are read by way of the current/voltage sensor (S). Then, voltage value of the current value read at the forward feed block (FFB) is calculated.

[0055] The voltage value required to generate the current value desired by the user at forward feed block (FFB) is calculated by using the driven load values. After comparing the calculated voltage value with triangular wave, pulse widths are calculated at the pulse width calculation block (PWCB). Counter and tap values that correspond to the calculated pulse widths are determined based on the edge—aligned or centre—aligned PWM signal. The current value applied to the load is read by the current/voltage sensor (S). The read current value is sampled by Analog Digital Converter (ADC), converted to digital, and the error value between the digital value and the current value desired to be fed by the user (disturbed output signal y(t)) is calculated. The disturbed output signal y(t) is transmitted to proportional—integral—derivative (PID) controller and the correction value is calculated at the proportional—integral—derivative (PID) controller. The pulse amplitude corresponding to the correction value and the counter and tap values corresponding to the pulse amplitude are calculated and used to correct the values calculated at the feed forward line.

[0056] To generate the centre—aligned signal shown in FIG. 4A, duty cycle (duty.sub.n) value is subtracted from F.sub.tap/F.sub.WPM value and divided by two to calculate the sample number (O.sub.n) of the initial 0 section.

[0057] Duty cycle value is calculated by comparing the desired signal with triangular wave used to generate PWM signal. Duty cycle value is the rate of the period where the desired signal (u(t)) value is higher than triangular wave to pulse period. This rate is calculated for each period of the triangular wave. a1, a1_tap, b1, b1_tap values are calculated using the duty.sub.n and O.sub.n values and below formulas for centre—aligned PWM generation:

a1=fixed(O.sub.n/F.sub.tap/F.sub.counter)  (2)

a1.sub.tap=O.sub.n−(fixed(O.sub.n/(F.sub.tap/F.sub.counter))×(F.sub.tap/F.sub.counter)  (3)

b1=fixed(duty.sub.n/(F.sub.tap/F.sub.counter)  (4)

b1.sub.tap.sub.i=duty.sub.n−(fixed(duty.sub.n/(F.sub.tap/F.sub.counter)×(F.sub.tap−F.sub.counter)  (5)

[0058] Following the calculations, the disturbed output signal y(t) is sampled by means of analog digital converter (ADC). Disturbed output signal y(t) is transmitted from the desired signal u(t) to proportional—integral—derivative (PID) controller and the correction value is calculated at the proportional—integral—derivative (PID) unit.

[0059] PWM signal is generated at FPGA by counting a1 and b1 counter values at F.sub.counter frequency. After counting 0 at the rate of a1 and 1 at the rate of b1, the sample number of total period is counted as 0 to obtain F.sub.counter/F.sub.WPM and to pass on to the next period of signal. Delays are applied to increasing and decreasing edges at the output by means of IO delay elements.

[0060] Delay at the rate of a1_tap value is applied to the increasing edge of the signal shown in FIG. 4A. Since the delay is only applied to the edge, the pulse's section 1 is shortened at the rate of a1_tap. In order correct the shortening, tap value to be applied to the decreasing edge is calculated using the below formula:

b1_tap=b1_tap_i+a1_tap  (6)

[0061] When input—out delay (IOD) elements are controlled by n bit, tap values need to be within the range of 0−(2n−1). This is why F.sub.tap/F.sub.sayaç ratio is adjusted to be maximum 2n. If b1 tap value calculated using formula (6) is bigger than F.sub.tap/F.sub.sayaç b1 counter value is added 1, then (F.sub.tap/F.sub.sayaç)−1 is subtracted from b1 tap value F.sub.tap/F.sub.sayaç to update b1 and b1 tap values.

[0062] b1, b1_tap values calculated using the duty.sub.n value are sufficient to generate the edge—aligned PWM signal shown in FIG. 4B.

b1=fixed(duty.sub.n/(F.sub.tap/F.sub.counter)  (7)

b1.sub.tap=duty.sub.n(fixed(duty.sub.n/(F.sub.tap/F.sub.sayaç)))×(F.sub.tap/F.sub.counter)  (8)

[0063] PWM signal is generated at FPGA by counting b1 counter values at F.sub.counter frequency. After counting 1 at the rate of b1 at the beginning of period, the sample number of total period is counted as 0 to obtain F.sub.counter/F.sub.WPM and to pass on to the next period of signal. Delays are applied to decreasing edges at the output by means of IO delay elements. As shown in FIG. 4B, the calculated b1_tap value is applied to the decreasing edge to generate the desired WPM signal.

[0064] When full—bridge switching (FBS) is used as switching mode power amplifier, the following formulas are used to calculate the duty sample numbers for left and right bridge (direction of current configured from left to right) by using the duty.sub.n value for centre—aligned WPM signal.

[00001]$\begin{array}{cc}\mathrm{lef}{t}_{-}dut{y}_n=\left(\frac{\frac{F_{tap}}{F_{DGM}}}{2}\right)+{\mathrm{duty}}_n/2& \left(9\right)\\ \mathrm{rig}{h}_{-}dut{y}_n=\left(\frac{\frac{F_{tap}}{F_{DGM}}}{2}\right)-\mathrm{du}t{y}_n/2& \left(10\right)\end{array}$

[0065] After calculating the duty sample numbers for left and right bridges, counter and tap values for left and right bridges are calculated using the centre—aligned method shown in FIG. 4A to generate two separate PWM signals.

[0066] Counter and tap values obtained at the feed forward block (FFB) output shown in FIG. 1, FIG. 2 and FIG. 3 are updated using the data coming from feedback block (FB) and transmitted to pulse width modulator (M).

[0067] FIG. 5 shows the system to update feed forward system parameters for feed forward system of centre—aligned and half—bridge switching power amplifier. As shown in FIG. 3, disturbed output signal y(t) is sampled by analog digital converter (ADC) and transmitted to FPGA. In FIG. 5, disturbed output signal y(t) is removed from the desired signal u(t) to enter the proportional—integral—derivative (PID) controller. Proportional—integral—derivative (PID) controller parameters need to be calculated according to the system in use. Correction value (duty.sub.n_PID) corresponding to the value of how much the duty value will be increased or decreased is calculated based on F.sub.tap frequency at the output of proportional—integral—derivative (PID) controller block. This value is divided by F.sub.tap/F.sub.counter to calculate counter PID and tap_PID values corresponding to b1_PID and b1_tap_PID. These values are divided by 2 to calculate the a1_PID, a1_tap_PID values shown in FIG. 5.

[0068] Updated counter and tap values to generate PWM signal are calculated using the formulas below:

a1_updated=a1−a1_PID  (11)

b1_updated=b1+b1_PID  (12)

a1_tap_updated=a1_tap−a1_tap_PID  (13)

b1_tap_updated=b1_tap+b1_tap_PID−a1_tap_PID  (14)

a1_tap_PID value needs to be taken into account while calculating b1_tap_updated in order not to shorten the 1 period. If tap value is smaller than 0 as a result of the addition and subtraction operations made while calculating the updated counter tap values, 1 is subtracted from the relevant counter is F.sub.tap/F.sub.counter added to update the tap value.

[0069] FIG. 6 shows the system to update feed forward system parameters for feed forward system of edge—aligned and half—bridge switching power amplifier by means of the feed forward block (FFB). b1_PID, b1_tap_PID values are calculated in FIG. 6 are calculated after calculating the counter PID and tap_PID values shown in FIG. 5. The below formulas are used to calculate the updated counter and tap values to be used to generate PWM signal:

b1_updated=b1+b1_PID  (15)

b1_tap_updated=b1_tap+b1_tap_PID  (16)

[0070] FIG. 7 shows the feedback and feed forward system for full—bridge centre—aligned PWM signal generation. Since the direction of current on load is from left to right and the voltage is calculated as the difference between left and right, the difference between both sides in full bridge gives the desired duty value. Therefore, correction amount obtained at the proportional—integral—derivative (PID) controller output needs to be applied to the difference. counter—PID is divided by 2, where left_b1_PID is the division and right_a1_PID is the remainder. The same operations are performed for pat_PID to calculate left_b1_tap_PID, right_b1_tap_PID, left a1_tap_PID and right_a1_tap_PID values. Formulas (11), (12), (13), and (14) are applied to calculated values to obtained updated counter and tap values and updated PWM signals are generated.

[0071] After generating the PWM signal, control signals of sub and top switches in each bridge is configured in reverse. Configuring control signals in reverse is known as the bridge drive method. According to this method, one of the switches is coupled to voltage source, while the other is coupled to earth. Voltage is fed to the load as long as desired while one of the switches is on and the other off.

[0072] According to another preferred embodiment of the invention, idle time adjustment circuits can be used between the circuits. While using the idle time adjustment circuit, voltage supply is protected by preventing both switches (used to couple load to voltage supply or earth) from being on at the same time. Control signal of each switch can be applied as digital WPM signal and the reverse signal. Moreover, idle time period between switches can be added to counter, tap or counter+tap periods of reverse signals. Calculations made in systems where each switch is separately controlled can be repeated based on the scenario of use.