Method for fabricating shallow trench isolation

Abstract

A method for fabricating semiconductor device includes the steps of: forming a trench in a substrate; forming a pad layer adjacent to two sides of trench; forming a dielectric layer to fill the trench; and performing a dry etching process to remove the pad layer and part of the dielectric layer to form a shallow trench isolation (STI). Preferably, the dry etching process comprises a non-plasma etching process.

Claims

1. A method for fabricating semiconductor device, comprising: forming a pad layer on a substrate, wherein the pad layer comprises: a first pad layer on the substrate; and a second pad layer on the first pad layer; removing part of the pad layer and the substrate to form a trench; forming a liner in the trench after removing part of the pad layer; performing a nitridation process to divide the liner into a first portion and a second portion, wherein the second portion comprises a lateral extending portion covering an end portion of the first portion and flush with a top surface of the substrate; after the nitridation process, forming a dielectric layer to fill the trench; performing a planarizing process to remove the dielectric layer so that the top surfaces of the dielectric layer and the pad layer are coplanar; removing the second pad layer; after removing the second pad layer, performing a dry etching process to remove the first pad layer, part of the liner, and part of the dielectric layer at the same time to form a shallow trench isolation (STI), wherein the dry etching process comprises a non-plasma etching process, and after the dry etching process, a top surface of the liner comprises a curve, and a top surface of the dielectric layer comprises a planar surface that is flush with the top surface of the substrate; and performing an anneal process to remove residues on a top surface of the substrate after removing the first pad layer and part of the dielectric layer.

2. The method of claim 1, wherein the first pad layer comprises silicon oxide and the second pad layer comprises silicon nitride.

3. The method of claim 1, wherein the dielectric layer directly contacts the second portion of the liner and a sidewall of the first pad layer.

4. The method of claim 1, wherein the second portion comprises nitrogen ions.

5. The method of claim 1, further comprising performing an in-situ steam generation (ISSG) process to form the liner.

6. The method of claim 1, wherein the dry etching process comprises hydrogen fluoride (HF) and ammonia gas (NH.sub.3).

7. The method of claim 1, wherein the dielectric layer comprises silicon oxide.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIGS. 1-5 illustrate a method for fabricating semiconductor device according to an embodiment of the present invention.

DETAILED DESCRIPTION

(2) Referring to FIGS. 1-5, FIGS. 1-5 illustrate a method for fabricating semiconductor device according to an embodiment of the present invention. As shown in FIG. 1, a substrate 12, such as a silicon substrate or silicon-on-insulator (SOI) substrate is provided, and a transistor region such as a PMOS region or a NMOS region is defined on the substrate. Next, a pad layer 14 is formed on the surface of the substrate 12, in which the pad layer 14 preferably includes a composite structure which could further include a pad layer 16 disposed on the surface of the substrate 12 and another pad layer 18 disposed on the pad layer 16. In this embodiment, the pad layers 16, 18 are preferably made of different insulating materials, in which the pad layer 16 preferably includes silicon oxide and the pad layer 18 preferably includes silicon nitride.

(3) Next, as shown in FIG. 2, a pattern transfer process is conducted by first forming a patterned mask (not shown) such as a patterned resist on the surface of the pad layer 18, and then conducting an etching process by using the patterned mask as mask to remove part of the pad layer 18, part of the pad layer 16, and part of the substrate 12 to form a trench 20 in the substrate 12. Next, an in-situ steam generation (ISSG) process is conducted to form a liner 22 on all of the sidewalls exposed in the trench 20. In this embodiment, the liner 22 is preferably made of an insulating layer including but not limited to for example a silicon oxide layer containing no dopants.

(4) Next, as shown in FIG. 3, a nitridation process 24 is conducted to divide the liner 22 into a first portion 26 and a second portion 28. Specifically, a decoupled plasma nitridation (DPN) process is conducted at this stage by using the patterned pad layer 14 as mask to implant nitrogen ions into part of the liner 22 while separating part of the liner 22 closer to the substrate 12 into a first portion 26 and part of the liner 22 away from the substrate 12 into a second portion 28. Preferably, the first portion 26 on the lower part of the liner 22 is not implanted with any dopants during the DPN process whereas the second portion 28 on the upper part of the liner 22 is implanted with nitrogen ions during the DPN process. In this embodiment, the single-layered liner 22 is preferably divided into a dual-layered structure during the DPN process, in which the thickness of each of the divided portions could be adjusted depending on the energy of the DPN process. For instance, the thickness of the first portion 26 could be equal to, less than, or greater than the thickness of the second portion 28, which are all within the scope of the present invention.

(5) Next, as shown in FIG. 4, a dielectric layer 30 is formed to fill the trench 20, and a planarizing process such as a chemical mechanical polishing (CMP) process could be conducted selectively to remove part of the dielectric layer 30 so that the top surface of the remaining dielectric layer 30 is even with the top surface of the pad layer 18. Next, another etching process is conducted to remove the pad layer 18 adjacent to two sides of the dielectric layer 30 and expose the pad layer 16 underneath.

(6) Next, as shown in FIG. 5, a dry etching process is conducted to remove part of the dielectric layer 30 and all of the pad layer 16 adjacent to two sides of the dielectric layer 30 to forma shallow trench isolation (STI). Specifically, the dry etching process conducted at this stage preferably includes a non-plasma dry etching process, in which the non-plasma dry etching process is accomplished by using hydrofluoric acid (HF) and/or ammonia gas (NH.sub.3) as main etching gas to remove part of the dielectric layer as well as all of the pad layer 16 adjacent to two sides of the dielectric layer 30 to form the STI 32. Next, a thermal treatment or anneal process could be conducted after removing part of the dielectric layer 30 and all of the pad layer 16 to remove or vaporize the residues remained on the surface of the substrate 12 formed during the dry etching process.

(7) It should be noted that in addition to dry etching process, a wet etching process is typically employed during the formation of the STI 32 to remove the pad layer 16 adjacent to two sides of the dielectric layer 30. The wet etching process however often causes divots on the top surface of the STI 32 as well as the adjacent liner 22 and affects the performance of the device. To resolve this issue, the present invention preferably conducts a dry etching process and without any wet etching process before forming gate dielectric layer of a MOS transistor to remove part of the dielectric layer 30 and pad layer 16 to form a STI 32. By following this approach, no divots would be formed on the top surface of the STI 32 and adjacent liner 22 and smoothness of the STI 32 could also be improved substantially. In this embodiment, the temperature of the dry etching process is preferably between 10° C. to 80° C. and the temperature of the thermal treatment or anneal process is preferably between 100° C. to 250° C. After the STI 32 is formed, follow-up fabrication process could be conducted by forming semiconductor device such as MOS transistors or memory devices adjacent to the STI 32 while using the STI 32 to isolate the adjacent devices. Since the fabrication of MOS transistors and memory devices are well known to those skilled in the art, the details of which are not explained herein for the sake of brevity.

(8) Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.