Double synchronous unified virtual oscillator control for grid-forming and grid-following power electronic converters

Abstract

A power electronic converter can utilize exemplary double synchronous unified virtual oscillator control (DSUVOC) logic or circuitry to convert direct current to alternating current that is input into a power grid. An exemplary DSUVOC controller of the present disclosure includes a double synchronous space vector oscillator component, a sequence extraction component, a fault detection component, a pre-synchronization component, a virtual impedance component, a terminal voltage compensation component, and/or an active damping component, wherein the double synchronous unified virtual oscillator controller is capable of controlling a grid following or a grid forming power electronic converter enabling synchronization and fault ride-through under both balanced and unbalanced conditions.

Claims

1. A double synchronous unified virtual oscillator controller of a power electronic converter in a power grid, comprising: a double synchronous space vector oscillator configured to generate a voltage vector output using feedback of an output current of the power electronic converter, the double synchronous space vector oscillator comprising a double sequence current reference generation component, a double sequence vector limiter component, a positive sequence space vector oscillator component, and a negative sequence space vector oscillator component; a sequence extraction component that is configured to extract positive and negative sequence symmetrical components of the output current of the power electronic converter; a fault detection component that is configured to detect and latch a fault condition based on the feedback of the output current of the power electronic converter or a grid voltage at a point-of-coupling of the power electronic converter with the power grid; a virtual impedance component that is configured to achieve harmonic current suppression in the output current of the power electronic converter; an observer based active damping component that is configured to achieve resonance damping in a high frequency range originating from a higher-order filter of the power electronic converter, wherein the higher-order filter is at least a second order filter; a terminal voltage compensation component that is configured to compensate a voltage deviation due to the higher-order filter or other non-ideal effects of the power electronic converter; and a pre-synchronization component that is configured to synchronize the double synchronous space vector oscillator with a terminal voltage of the power electronic converter at the point-of-coupling before being connected to the power grid, wherein the double synchronous unified virtual oscillator controller is configured to control the power electronic converter for both grid forming and grid following operations.

2. The double synchronous unified virtual oscillator controller of claim 1, wherein the higher-order filter comprises an LCL filter.

3. The double synchronous unified virtual oscillator controller of claim 1, wherein the power electronic converter connects to the power grid via a static transfer switch.

4. The double synchronous unified virtual oscillator controller of claim 1, wherein the double synchronous unified virtual oscillator controller is configured to provide grid synchronization in a grid-following mode of operation with bidirectional power flow control capability without using a phase-locked-loop.

5. The double synchronous unified virtual oscillator controller of claim 1, wherein the double synchronous unified virtual oscillator controller is configured to provide DC bus voltage regulation in a grid-following mode of operation without a phase-locked-loop.

6. The double synchronous unified virtual oscillator controller of claim 1, wherein the double synchronous unified virtual oscillator controller is configured to implement a grid forming mode of operation that implements a droop response for both grid connected and islanded operations.

7. The double synchronous unified virtual oscillator controller of claim 6, wherein the double synchronous unified virtual oscillator controller is implemented using an error in voltage vector magnitude in a voltage magnitude correction term.

8. The double synchronous unified virtual oscillator controller of claim 6, wherein the double synchronous unified virtual oscillator controller is implemented using an error in square of voltage vector magnitude in a voltage magnitude correction term.

9. The double synchronous unified virtual oscillator controller of claim 6, wherein the double synchronous unified virtual oscillator controller is configured to generate a switching duty ratio based on a DC bus voltage measurement.

10. The double synchronous unified virtual oscillator controller of claim 6, wherein the double synchronous unified virtual oscillator controller is configured to provide voltage regulation support without communication through a communication network.

11. The double synchronous unified virtual oscillator controller of claim 1, wherein the double synchronous unified virtual oscillator controller is configured to enable grid synchronization of a grid following power electronic converter or a grid forming power electronic converter under balanced and unbalanced grid voltage conditions without operation of a phase-locked-loop.

12. The double synchronous unified virtual oscillator controller of claim 1, wherein the double synchronous unified virtual oscillator controller is configured to enable a ride-through of balanced and unbalanced grid faults by limiting the output current of the power electronic converter without switching to a phase-locked-loop based back-up controller.

13. The double synchronous unified virtual oscillator controller of claim 1, wherein the double synchronous unified virtual oscillator controller is configured to enable grid synchronization of the power electronic converter under variable grid impedance conditions without tuning of control parameters.

14. The double synchronous unified virtual oscillator controller of claim 1, wherein the virtual impedance component is configured to suppress harmonic distortion in the output current of a grid-following power electronic converter or a grid-forming power electronic converter.

15. The double synchronous unified virtual oscillator controller of claim 1, wherein the terminal voltage compensation component is configured to eliminate a voltage deviation caused by the higher-order filter of the power electronic converter.

16. The double synchronous unified virtual oscillator controller of claim 1, wherein the double sequence vector limiter component is configured to limit a reference of the output current of the power electronic converter within limits allowable by power electronic converter hardware.

17. The double synchronous unified virtual oscillator controller of claim 1, wherein the positive sequence space vector oscillator component and the negative sequence space vector oscillator component are configured to enable simultaneous synchronization with positive and negative sequence symmetrical components of the grid voltage without operation of a phase-locked-loop.

18. The double synchronous unified virtual oscillator controller of claim 1, wherein active resistances in the positive and negative sequence space vector oscillator components are configured to enable over-current limiting protection under fault conditions.

19. The double synchronous unified virtual oscillator controller of claim 1, wherein the pre-synchronization component is configured to achieve start-up in a grid-following power electronic converter or seamless islanded to grid connected transition in a grid forming power electronic converter without operation of a phase-locked-loop.

20. The double synchronous unified virtual oscillator controller of claim 1, wherein the double sequence current reference generation component is configured to achieve different control objectives in the power electronic converter, wherein the different control objectives include at least one of constant real power flow, constant reactive power flow, or balanced output current.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Many aspects of the present disclosure can be better understood with reference to the following drawings. The components in the drawings are not necessarily to scale, emphasis instead being placed upon clearly illustrating the principles of the present disclosure. Moreover, in the drawings, like reference numerals designate corresponding parts throughout the several views.

(2) FIG. 1 shows a three-phase power electronic converter based on an exemplary double synchronous unified virtual oscillator controller (DSUVOC) using either the converter side current i.sub.a of the grid/network-side current i.sub.g feedback in accordance with embodiments of the present disclosure.

(3) FIG. 2 shows a double synchronous space vector oscillator which enables simultaneous synchronization to both positive and negative sequence components of a grid voltage in accordance with embodiments of the present disclosure.

(4) FIG. 3 shows an exemplary positive sequence space vector oscillator using error in square of voltage vector magnitude for magnitude correction in accordance with embodiments of the present disclosure.

(5) FIG. 4 shows an exemplary negative sequence space vector oscillator using error in square of voltage vector magnitude for magnitude correction in accordance with embodiments of the present disclosure.

(6) FIG. 5 shows generation of mode transition signal from a fault signal by an exemplary fault detection component in accordance with embodiments of the present disclosure.

(7) FIG. 6 shows an exemplary closed-loop compensator for DC bus voltage regulation in a grid following application using an exemplary DSUVOC in accordance with embodiments of the present disclosure.

(8) FIGS. 7A and 7B show a DC bus voltage regulation using a grid following (GFL) form of DSUVOC at (A) start-up transient and (B) steady-state voltage and current shapes in accordance with embodiments of the present disclosure.

(9) FIGS. 8A and 8B shows a response to step change in reactive power reference at (A) Q.sub.0=500 VAR to Q.sub.0=−500 VAR and (B) Q.sub.0=−500 VAR to Q.sub.0=500 VAR.

(10) FIGS. 9A and 9B show a steady-state wave-shapes for (A) Q.sub.0=500 VAR and (B) Q.sub.0=−500 VAR.

(11) FIG. 10 shows a response to step change in a DC load in a GFL power electronic converter using an exemplary DSUVOC in accordance with embodiments of the present disclosure.

(12) FIG. 11 shows a hybrid AC-DC microgrid setup in accordance with embodiments of the present disclosure.

(13) FIGS. 12A-12B show a pre-synchronization of an interlinking converter (ILC1) when a first static-transfer-switch (STS.sub.1) is open and a second static-transfer-switch (STS.sub.g) is closed (A) before synchronization and (B) at a synchronized condition in accordance with embodiments of the present disclosure.

(14) FIG. 13 shows an interlinking converter (ILC1) being connected to the grid by closing STS.sub.1 after synchronization is achieved in accordance with embodiments of the present disclosure.

(15) FIGS. 14A-14B show a harmonic compensation in converter output current (A) without harmonic suppression filters and (B) with harmonic compensation in accordance with embodiments of the present disclosure.

(16) FIG. 15 shows an AC load that does not experience any disturbance (uninterrupted load current when the system is islanded unintentionally by opening STS.sub.g in accordance with embodiments of the present disclosure.

(17) FIG. 16 shows interlinking converters (ILC1 and ILC2) serving the AC load in islanded condition (STS.sub.g open; STS.sub.1 and STS.sub.2 are closed) in accordance with embodiments of the present disclosure.

(18) FIG. 17 shows a ride-through response of a GFM converter using an exemplary DSUVOC when subjected to an AC fault through an impedance of 53% p.u. under islanded condition in accordance with embodiments of the present disclosure.

(19) FIG. 18 shows a ride-through response of a grid forming (GFM) power electronic converter using an exemplary DSUVOC when subjected to a dead-short at the converter terminal in, accordance with embodiments of the present disclosure.

(20) FIG. 19A-19C show ride-through response of a GFM converter under grid-tied operation when a converter current limit is not reached for (A) an overall response of fault occurring and clearing, (B) a zoomed-in response of the instant when fault occurs, and (C) a zoomed-in response of the instant when a fault is cleared, in accordance with embodiments of the present disclosure.

(21) FIG. 20A-20C show a ride-through response of a GFM converter under grid-tied operation when a converter current limit is reached for (A) an overall response of fault occurring and clearing, (B) a zoomed-in response of the instant when fault occurs, and (C) a zoomed-in response of the instant when a fault is cleared, in accordance with embodiments of the present disclosure.

(22) FIG. 21 shows a ride-through response of a GFM converter under grid-tied operation when subjected to a single line to ground fault and an exemplary DSUVOC is programmed to achieve constant real power flow under a fault condition, in accordance with embodiments of the present disclosure.

(23) FIG. 22A-22D show a robust response of an exemplary DSUVOC based power electronic converter under a strong grid (short-circuit ratio of 10) and an ultra-weak grid (short-circuit ratio of 1) using identical set of control parameters for (A) a no-load to full-load step response under strong grid, (B) a full-load to no-load step response under strong grid, (C) a no-load to full-load step response under ultra-weak grid, and (D) a full-load to no-load step response under an ultra-weak grid, in accordance with embodiments of the present disclosure.

DETAILED DESCRIPTION

(24) The present disclosure describes various embodiments of systems, apparatuses, and methods for a double synchronous unified virtual oscillator controller (DSUVOC) of a power electronic converter. In accordance with embodiments of the present disclosure, a double synchronous unified virtual oscillator controller (DSUVOC) enables phase-locked-loop (PLL)-less grid synchronization and ride-through in grid following and grid forming power electronic converters under nominal conditions as well as under both symmetric (balanced) and asymmetric (unbalanced) AC fault conditions.

(25) In a grid following power electronic converter, an exemplary DSUVOC achieves grid connected operation with bidirectional power flow control and DC bus voltage regulation. Grid forming (GFM) operation is achieved in both grid connected and islanded modes with seamless transition between the two. For both GFL and GFM modes of operation, an exemplary DSUVOC enables fast over-current limiting and simultaneous synchronization to the positive and negative sequence symmetrical components of the AC network/grid voltage without any phase-locked-loop (PLL) circuitry. This enables ride-through of balanced/symmetrical and unbalanced/asymmetrical faults without the need for switching to a separate set of back-up controller under fault conditions. The PLL-ness nature of the DSUVOC enables robust synchronization of power electronic converters under widely varying grid strengths ranging from strong to ultra-weak grids using identical control parameters. The GFL and GFM operation, fault ride-through response, and robust operation under variable grid conditions of an exemplary DSUVOC are validated through hardware experiments in a hybrid AC-DC microgrid.

(26) Space vector notations are used in subsequent analysis and descriptions of an exemplary DSUVOC controller. The space vector representation of a set of three-phase quantities, such as [u.sub.u u.sub.v u.sub.w].sup.T, in the stationary αβ reference frame is obtained using magnitude-invariant Clarke transformation. The corresponding space vector is denoted as u=[u.sub.α u.sub.β].sup.T .Math.u=u.sub.α+ju.sub.β, where j=√{square root over (−1)} denotes the imaginary unit. The column vector u and the complex representation u of space vectors are used interchangeably in the rest of the present disclosure. A subscript of ‘0’, such as in u.sub.0 or u.sub.0, denote the reference/set-point or nominal value of the respective state/variable. Positive and negative sequence components correspond to the symmetrical components of a three-phase quantity. A ‘+’ or ‘−’ in the subscript represents the +ve or −ve sequence component of the corresponding variable; the +ve and −ve sequence components of u are denoted as u.sub.+=[u.sub.α+ u.sub.β+]T.Math.u.sub.+=u.sub.α++ju.sub.β+ and u.sub.−=[u.sub.α− u.sub.β−].sup.T.Math.u.sub.−=u.sub.α−+ju.sub.β−. Similarly, the +ve and −ve sequence components of u.sub.0 are denoted as u.sub.0+=[u.sub.α0+ u.sub.β0+].sup.T.Math.u.sub.0+=u.sub.α0++ju.sub.β0+ and u.sub.0−=[u.sub.α0− u.sub.β0−].sup.T.Math.u.sub.0−=u.sub.α0−+ju.sub.β0−. The magnitude of a vector is denoted as , e.g., û=∥u∥=(u.sub.α.sup.2+u.sub.β.sup.2).sup.0.5.

(27) A three-phase power electronic converter using DSUVOC is shown in FIG. 1. The DSUVOC controller is implemented based on space vectors in stationary αβ-reference frame. DSUVOC generates a voltage vector output v.sub.c using feedback of the terminal voltage v.sub.g at the point-of-coupling (PoC) (of the power electronic converter with the power grid) and the converter output current; either of the converter-side current i.sub.a or the network/grid-side current i.sub.g feedback can be used. The switching duty ratio m is generated for pulse-width modulation (PWM) using appropriate scaling based on the DC bus voltage measurement. The DSUVOC structure includes a double synchronous space vector oscillator component, a sequence extraction (SE) component, a fault detection (FD) component, a pre-synchronization (PS) component, a virtual impedance (VI) component, a terminal voltage compensation (TVC) component, and an active damping (AD) component. All components are not essential and selective components can be used in various applications for specific control objectives. The DSUVOC controller can be identically used in single phase and three-phase applications.

(28) The double synchronous space vector oscillator component, shown in FIG. 2, includes four components: a double sequence current reference generation (DSCRG) component, a double sequence vector limiter (DSVL) component, a +ve sequence space vector oscillator (SVO), and a −ve sequence SVO. The DSCRG uses the +ve sequence real and reactive power set-points (P.sub.0+, Q.sub.0+), the −ve sequence real and reactive power set-points (P.sub.0−, Q.sub.0−), and the +ve and −ve sequence SVO outputs v.sub.+ and v.sub.−, respectively, to generate the +ve sequence current reference i.sub.0+.Math.[i.sub.α0+ i.sub.β0+].sup.T and the −ve sequence current reference i.sub.0−.Math.[i.sub.α0− i.sub.β0−].sup.T. Instead of separate +ve and −ve sequence power set-points, aggregate set-points P.sub.0=P.sub.0++P.sub.0− and Q.sub.0=Q.sub.0++Q.sub.0− may also be used. The double sequence current reference can be generated for different control objectives. For instance, under asymmetric grid faults, unbalanced/asymmetric reactive power injection may be desired to boost the positive sequence component and to reduce the negative sequence component of the grid voltage. Alternatively, constant real power flow may be desired under unbalanced fault condition to reduce the stress on the DC bus capacitor. For constant real power flow under unbalanced grid condition, the double sequence current references can be determined as:

(29) $\begin{array}{cc}{i}_{\alpha 0+}=\frac{2P_0{v}_{\alpha +}}{N\left({.Math.v_{+}.Math.}^2-{.Math.v_{-}.Math.}^2\right)}+\frac{2Q_0{v}_{\beta +}}{N\left({.Math.v_{+}.Math.}^2+{.Math.v_{-}.Math.}^2\right)}& 1\left(a\right)\\ i_{\beta 0+}=\frac{2P_0{v}_{\beta +}}{N\left({.Math.v_{+}.Math.}^2-{.Math.v_{-}.Math.}^2\right)}-\frac{2Q_0{v}_{\alpha +}}{N\left({.Math.v_{+}.Math.}^2+{.Math.v_{-}.Math.}^2\right)}& 1\left(b\right)\\ i_{\alpha 0-}=\frac{2P_0{v}_{\alpha -}}{N\left({.Math.v_{+}.Math.}^2-{.Math.v_{-}.Math.}^2\right)}+\frac{2Q_0{v}_{\beta -}}{N\left({.Math.v_{+}.Math.}^2+{.Math.v_{-}.Math.}^2\right)}& 1\left(c\right)\\ i_{\beta 0-}=\frac{2P_0{v}_{\beta -}}{N\left({.Math.v_{+}.Math.}^2-{.Math.v_{-}.Math.}^2\right)}-\frac{2Q_0{v}_{\alpha -}}{N\left({.Math.v_{+}.Math.}^2+{.Math.v_{-}.Math.}^2\right)}& 1\left(d\right)\end{array}$

(30) Here, N=1 or N=3 is used for single-phase or three-phase applications, respectively. The choice of how the double sequence current reference is generated is not unique and different selection rules may be used to achieve various control objectives such as constant real power flow, constant reactive power flow, balanced three-phase current injection, etc. Note that under symmetric/balanced grid condition v.sub.−=0 and hence a balanced three-phase current reference, i.e., i.sub.0−=0, is obtained.

(31) The double sequence vector limiter (DSVL) is used to limit the current reference below the maximum current value allowable for the power electronic converter hardware. For i.sub.0+≠0, i.sub.0−≠0, the two sequence vectors rotate in an opposite direction and lead to a resultant rotating vector in the stationary frame with a time-varying magnitude. Therefore, to ensure safe converter operation, the current references of all three phases must be checked and limited within safe values. In the DSVL, the three-phase current references [i.sub.u0, i.sub.v0, i.sub.w0] are determined as:
i.sub.u0=[i.sub.α0+.sup.2+i.sub.β0+.sup.2+i.sub.α0−.sup.2+2(i.sub.α0+−i.sub.β0+i.sub.β0−)].sup.1/2  (2a)
i.sub.v0=[i.sub.α0+.sup.2+i.sub.β0+.sup.2+i.sub.α0−.sup.2+i.sub.β0−.sup.2−(i.sub.α0+i.sub.α0−−i.sub.β0+i.sub.β0−)−√{square root over (3)}(i.sub.β0+i.sub.α0−+i.sub.+0+i.sub.β0−)].sup.1/2  (2b)
i.sub.w0=[i.sub.α0+.sup.2+i.sub.β0+.sup.2+i.sub.α0−.sup.2+i.sub.β0−.sup.2−(i.sub.α0+i.sub.α0−−i.sub.β0+i.sub.β0−)].sup.1/2.  (2c)

(32) Next, the instantaneous maximum phase current reference is determined as i.sub.0max=max{i.sub.u0, i.sub.v0, i.sub.w0}. The saturated current reference vectors are then obtained as
i.sub.0+=k.sub.sati.sub.0+; i.sub.0−=k.sub.sati.sub.0−  (3)

(33) Here, k.sub.sat=i.sub.m/i.sub.0max where i.sub.m denotes the maximum current allowable by the converter hardware.

(34) The positive and negative sequence space vector oscillators (SVO) serve as the synchronizing units for positive and negative sequence components, respectively. The implementation structure of the +ve and −ve sequence SVOs are shown in FIG. 3 and FIG. 4, respectively. The dynamics of the +ve and −ve sequence SVOs are given as
{dot over (v)}.sub.+=jω.sub.0+x.sub.rμ.sub.+({circumflex over (v)}.sub.0+.sup.2−∥v.sub.+∥.sup.2)+η.sub.+e.sup.jϕ(i.sub.0+−i.sub.+)  (4a)
{dot over (v)}.sub.−=−jω.sub.0+x.sub.rμ.sub.−({circumflex over (v)}.sub.0−.sup.2−∥v.sub.−∥.sup.2)−η.sub.−e.sup.jϕ(i.sub.0−−i.sub.−)  (4b)

(35) Here, ω.sub.0 denotes the nominal frequency; {circumflex over (v)}.sub.0+ and {circumflex over (v)}.sub.0− denote the peak values of the +ve sequence and −ve sequence voltage references v.sub.0+ and v.sub.0−, respectively; η.sub.+>0 and η.sub.−>0 are the synchronization gains; μ.sub.+>0 and μ.sub.−>0 are the voltage magnitude correction gains; and ϕ∈[0,π/2] is chosen for desired droop relation. For instance, ϕ=π/2 gives a real power versus frequency and reactive power versus voltage droop response, whereas ϕ=0 leads to the opposite droop relation. To facilitate a smooth and seamless transition between normal operations and a fault ride-through operation, the SVO dynamics are adjusted through a mode transition signal x.sub.r generated by the fault detection (FD) block (see FIG. 1). The complementary signal x.sub.r=1−x.sub.r is used in Equation (4a) and Equation (4b). The +ve and −ve sequence components, i.sub.+ and i.sub.−, respectively, of the converter output current are generated by the sequence extraction (SE) block in FIG. 1. Under normal operation, the negative sequence SVO may be disabled; however, both +ve and −ve sequence SVOs are required under unbalanced grid conditions. An active resistance R.sub.0 is used (see FIG. 3 and FIG. 4) to achieve fast over-current limiting under fault conditions. The insertion and exclusion of the active resistance under different modes of operation are achieved through the mode transition signal x.sub.r. To reduce current tracking error under fault conditions, the synchronization gains η.sub.+ and η.sub.− are raised to higher values as:

(36) $\begin{array}{cc}{\eta }_{+}={\eta }_{0+}\left(1+\frac{x_r}{{\tau }_f}\right)& \left(5a\right)\\ {\eta }_{-}={\eta }_{0-}\left(1+\frac{x_r}{{\tau }_f}\right)& \left(5b\right)\end{array}$
where η.sub.0+ and η.sub.0− are the nominal synchronization gains and τ.sub.f denotes the settling time.

(37) Another alternative implementation of the space vector oscillators can be represented as:
{dot over (v)}.sub.+=jω.sub.0+x.sub.rμ.sub.+({circumflex over (v)}.sub.0+−∥v.sub.+∥)+η.sub.+e.sup.jϕ(i.sub.0+−i.sub.+)  (6a)
{dot over (v)}.sub.−=−jω.sub.0+x.sub.rμ.sub.−({circumflex over (v)}.sub.0−−∥v.sub.−∥)−η.sub.−e.sup.jϕ(i.sub.0−−i.sub.−)  (6b)

(38) In Equation (4a) and (4b), the error in the squares of the voltage vector magnitudes ({circumflex over (v)}.sub.0+.sup.2−∥v.sub.+∥.sup.2) and ({circumflex over (v)}.sub.0−.sup.2−∥v.sub.−∥.sup.2) are used in the magnitude correction terms, respectively, whereas in Equation (6a) and (6b), errors in the voltage vector magnitudes ({circumflex over (v)}.sub.0+−∥v.sub.+∥) and ({circumflex over (v)}.sub.0−−∥v.sub.−∥) are used, respectively. For brevity, in the following texts the analysis and design are shown using Equation (4a) and (4b). Similar analysis, design, and controller implementation can be achieved using Equation 6(a) and 6(b) as well.

(39) From the converter output current i.Math.[i.sub.α i.sub.β].sup.T, the sequence extraction (SE) block calculates the +ve and −ve sequence components i.sub.+.Math.[i.sub.α+ i.sub.β+].sup.T and i.sub.−.Math.[i.sub.α− i.sub.β−].sup.T as:
i.sub.α+=0.5(i.sub.α−i.sub.β⊥)  (7a)
i.sub.β+=0.5(i.sub.β+i.sub.α⊥)  (7b)
i.sub.α−=0.5(i.sub.α+i.sub.β⊥)  (7c)
i.sub.β−=0.5(i.sub.β−i.sub.α⊥)  (7d)
where i.sub.α⊥ and i.sub.β⊥ denote the T.sub.0/4 delayed versions of i.sub.α and i.sub.β, respectively, and T.sub.0=2π/ω.

(40) The fault detection (FD) subsystem may detect and latch a fault state due to overcurrent, i.e., max{i.sub.u, i.sub.v, i.sub.w}>I.sub.m, or due to unbalance in the grid voltage, i.e.,

(41) $\frac{.Math.v_{g-}.Math.}{.Math.v_{g+}.Math.}>k_{\mathrm{uft}},$
where k.sub.uft denotes the maximum allowable unbalance factor. The unbalance factor is defined as the ratio of the −ve sequence component v.sub.g− to the +ve sequence component v.sub.g+ of the grid voltage v.sub.g. The fault signal x.sub.f is shown in FIG. 5. Based on the fault signal x.sub.f, the mode transition signal x.sub.r is generated. At the instant when a fault is detected and latched, i.e., x.sub.f=1, x.sub.r follows x.sub.f immediately. However, when the fault is cleared, the transition signal is ramped down over a period of time t.sub.f to enable a smooth transition from a fault mode to a normal mode of operation.

(42) Under the normal mode of operation, x.sub.r=0 and the negative sequence SVO can be disabled. For ease of explanation of the synchronizing mechanism of the SVO, the normal operation is considered. Substituting Equation (1) into Equation (4a), the instantaneous voltage and frequency of the SVO output voltage are derived as:

(43) $\begin{array}{cc}\stackrel{.}{V}=2\mu \left(V_0^2-V^2\right)+\frac{\eta }{\mathrm{NV}}\left[\left(P_0-P\right)\cos \varphi +\left(Q_0-Q\right)\sin \varphi \right]& \left(8a\right)\\ \omega ={\omega }_0+\frac{\eta }{{\mathrm{NV}}^2}\left[\left(P_0-P\right)\sin \varphi -\left(Q_0-Q\right)\cos \varphi \right]& \left(8b\right)\end{array}$
where

(44) $V=\frac{.Math.v.Math.}{\sqrt{2}},V_0=\frac{.Math.v_0.Math.}{\sqrt{2}},P_0=P_{0+},Q_0=Q_{0-},\eta ={\eta }_{0+},\mathrm{and}\mu ={\mu }_{+}.\mathrm{For}\varphi =\frac{\pi }{2},$
Equation (8) reduces to:

(45) $\begin{array}{cc}\stackrel{.}{V}=2\mu \left(V_0^2-V^2\right)+\frac{\eta }{\mathrm{NV}}\left(Q_0-Q\right)& \left(9a\right)\\ \omega ={\omega }_0+\frac{\eta }{{\mathrm{NV}}^2}\left(P_0-P\right)& \left(9b\right)\end{array}$

(46) For μ=0, Q=Q.sub.0 is achieved. For GFL operation, μ=0 is used. Therefore, accurate tracking of the reactive power reference is achieved. However, a real power droop response is observed for any deviation of the grid frequency from the nominal value, i.e., ω≠ω.sub.0. Integral compensation can be used to achieve accurate tracking of a real power reference. For ϕ=0 and μ=0, accurate tracking of the real power reference is achieved by the SVO dynamics, but integral compensation is required to obtain accurate tracking of the reactive power reference. For DC bus voltage regulation in a GFL application, ϕ=π/2 and μ=0 can be used where the real power set-point P.sub.0 is dynamically generated by applying a closed-loop compensator, such as a proportional-integral (PI) compensator, on the DC bus voltage error, which is shown in FIG. 6, where v.sub.dc* denotes the DC bus voltage reference.

(47) For GFM operation μ≠0 is used. For μ≠0 and ϕ=π/2, the voltage magnitude and frequency can be derived from Equation (9) as:

(48) $\begin{array}{cc}{V}^2=V_0^2+\frac{\eta }{2\mu {\mathrm{NV}}^2}\left(Q_0-Q\right)& \left(10a\right)\\ \omega ={\omega }_0+\frac{\eta }{{\mathrm{NV}}^2}\left(P_0-P\right)& \left(10b\right)\end{array}$

(49) Accordingly, a real power versus frequency and reactive power versus voltage droop responses are obtained. For ϕ=0, opposite droop relations are obtained as:

(50) $\begin{array}{cc}{V}^2=V_0^2+\frac{\eta }{2\mu {\mathrm{NV}}^2}\left(P_0-P\right)& \left(11a\right)\\ \omega ={\omega }_0+\frac{\eta }{{\mathrm{NV}}^2}\left(Q_0-Q\right)& \left(11b\right)\end{array}$

(51) In Equation (10a) and (11a), the droop response is obtained in terms of the square of the voltage vector magnitude due to SVO implementation following Equation (4a) and (4b). The droop response in terms of voltage vector magnitude, instead of its square, can be obtained with an SVO implementation following Equation (6a) and (6b).

(52) There are two key purposes of virtual impedance, namely, harmonic compensation and the stabilization of SVOs. Non-ideal effects, such as dead-time, introduce harmonic distortion in v.sub.a. Moreover, harmonic distortion in the network/grid voltage v.sub.g or nonlinear loads lead to undesired harmonic distortion in the output current. Contrarily, in certain applications, specifically in an islanded microgrid, harmonic current injection by the GFM converters may be desired to compensate for harmonic distortion in the network voltage. The converter output impedance or admittance can be selectively increased to very high values at the harmonic frequencies to achieve the desired harmonic compensation in converter output current or network voltage, respectively. In a power electronic converter, harmonic current suppression is achieved by virtual impedance as:
v.sub.zv(s)=v.sub.x−Z.sub.v(s)×i.sub.x(s); ∀x∈{α,β}  (12a)

(53) $\begin{array}{cc}{Z}_v\left(s\right)=\frac{R_{\mathrm{vir}}+s{L}_{\mathrm{vir}}}{\frac{s}{{\omega }_c}+1}+\underset{h}{.Math.}-\frac{K_h{\omega }_{B,h}{\omega }_h}{s^2+{\omega }_{B,h}s+{\omega }_h^2};\mathrm{or}& \left(12b\right)\\ Z_v\left(s\right)=\frac{R_{\mathrm{vir}}+s{L}_{\mathrm{vir}}}{\frac{s}{{\omega }_c}+1}+\underset{h}{.Math.}\frac{K_h{\omega }_{B,h}s}{s^2+{\omega }_{B,h}s+{\omega }_h^2}& \left(12c\right)\end{array}$

(54) Here, K.sub.h and ω.sub.B,h denote the desired impedance magnitude and the bandwidth of the resonant filter at harmonic frequency ω.sub.h, respectively. On the other hand, virtual resistance R.sub.vir emulation is necessary to ensure dynamic stability of the SVOs. A virtual inductance L.sub.vir may also be used in different applications where very fast over-current limiting is required under fault operation with a strong grid condition. A limited bandwidth of ω.sub.c in Equation (7) is used for the virtual resistance and inductance emulation. Further detail and design guidelines for Z.sub.v(s) can be found in a paper by Awal, et al. (M. A. Awal, H. Yu, I. Husain, W. Yu, and S. Lukic, “Selective Harmonic Current Rejection for Virtual Oscillator Controlled Grid-Forming Voltage Source Converters,” in IEEE Transactions on Power Electronics) [21].

(55) In existing literature, the high frequency dynamics of the higher order input filters, such as LCL filters, of oscillator based VSCs have been completely ignored which may lead to undesired resonances in the high frequency range (hundreds of Hz to few kHz). The digital controller implementation delay and variation in network/grid impedance further aggravates the severity of such resonances and may even destabilize the system in extreme cases. In various embodiments, an exemplary DSUVOC includes an observer band active damping (OBAD) component that utilizes an observer to estimate the states of the LCL filter, and using the observer estimated states, active damping of the of high frequency resonances is achieved [22].

(56) For the analysis and design of the observer based active damping, the slower dynamics of the SVOs and the selectively tuned dynamics of virtual impedance emulation can be ignored. The LCL filter is modelled as:

(57) 0$\begin{array}{cc}\frac{d}{\mathrm{dt}}\left(x\right)=\mathrm{Ax}+\mathrm{Bu};x={\left[i_a{i}_g{v}_f\right]}^T;u={\left[v_a{v}_g\right]}^T& \left(13\right)\end{array}$

(58) The system matrices A and B can be determined using the LCL filter parameters. A discrete observer is designed using the LCL filter model, in which the discrete observer is implemented as:
{circumflex over (x)}[k+1]=A.sub.obs{circumflex over (x)}[k]+B.sub.obsu.sub.obs[k];{circumflex over (x)}=[{circumflex over (.Math.)}.sub.a{circumflex over (.Math.)}.sub.g{circumflex over (v)}.sub.f].sup.T; u.sub.obs=[v.sub.av.sub.gi.sub.m].sup.T  (14)
where i.sub.m=i.sub.a or i.sub.m=i.sub.g can be used based on availability of feedback signal. The output of the OBAD block is calculated as v.sub.ad=R.sub.ad({circumflex over (.Math.)}.sub.a−{circumflex over (.Math.)}.sub.g), where R.sub.ad denotes the active damping gain.

(59) The power electronic converter can connect/disconnect to/from the network using a static-transfer-switch (STS). This process of synchronizing the converter output voltage with the grid voltage is termed as pre-synchronization. The pre-synchronization can be achieved by a first-order low-pass filter in the form of a virtual RL branch. A virtual current i.sub.ps can be generated by the pre-synchronization block to estimate the current that would flow if the STS were closed. The virtual current is generated as:

(60) $\begin{array}{cc}{i}_{ps}=\frac{v-v_g}{{\mathrm{sL}}_{ps}+R_{ps}}& \left(15\right)\end{array}$

(61) The parameters can be chosen as L.sub.ps≈(L.sub.a+L.sub.g) and R.sub.ps≈R.sub.vir. It is worth noting that exact knowledge of the LCL filter parameters are not required for the parameter selection. To illustrate the functionality, two distinct use-cases can be defined for the pre-synchronization component.

(62) For GFM converters while serving local loads, the voltages across the STS need to be synchronized prior to closing the STS. In such scenarios, the virtual current i.sub.ps is added to the actual converter output current and the resultant total current is used as feedback to the SVOs. The virtual current i.sub.ps gives an estimate of the current that would flow between the power electronic converter and the network at the PoC if the STS were closed. Due to the virtual current i.sub.ps feedback, SVOs adjust the oscillator voltage to minimize the virtual real and reactive power flow. When the amplitude of the virtual current |i.sub.ps| stabilizes, the STS can be closed safely.

(63) For GFL operation, the STS can be closed before the switching of the power devices are initiated. For instance, during start-up of an active-front-end rectifier, the DC bus may be charged by using the switch network as an uncontrolled diode bridge. Meanwhile, the SVOs can be synchronized with the measured voltage v.sub.g using the pre-synchronization filter. Once |i.sub.ps| stabilizes, the DC bus voltage control loop and the switching of the power devices can be initialized without large transients. Alternatively, PLL based pre-synchronization may also be used where PLLs are run to detect the phase and voltage magnitude mismatches between the converter output voltage and the grid voltage. Two sets of PI compensators can be used on the differences, and dynamic adjustments ΔV.sub.0 and Δω.sub.0 are generated which are added to the nominal voltage and frequency set-points. Note that these PLLs are not required for grid synchronization when the power electronic converter is connected to the electrical network/grid; rather, the double synchronous space vector oscillator serves as the synchronizing units.

(64) The droop responses given by Equations (8), (9), (10), and (11) appear at the converter's switch terminals and not at the PoC. The LCL filter causes voltage deviation from the ideal droop response depending on the power flow between the converter and the grid. The terminal voltage compensation (TVC) (see FIG. 1) is used to compensate such voltage deviations. The TVC is implemented as:
v.sub.tvc=jω.sub.0(L.sub.a+L.sub.g)i  (16)

(65) In various embodiments, DSUVOC is a vector controller running on both α and β axis. In a single-phase implementation, a full vector controller is used. The feedback signal i.sub.β can be generated by delaying the actual converter output current i.sub.α=i.sub.g or i.sub.a by T.sub.0/4=2π/(4ω.sub.0), where ω.sub.0 denotes the nominal frequency of the power electronic converter and the modulating signal for PWM is obtained from v.sub.cα. All analysis and design guidelines presented in the present disclosure are generalized to apply identically for single phase and three phase applications using a parameter N denoting the number of phases, i.e., N=1 and N=3 for single and three phase systems, respectively.

(66) The GFL and GFM modes of operation of the DSUVOC are validated through hardware experiments using laboratory prototypes. For digital implementation, the SVO dynamic equations are discretized using Huen's method, which is a second order Runge-Kutta technique [23].

(67) In various embodiments, a single-phase active rectifier is used to validate the GFL operation, which has real and reactive powers ratings of P.sub.rated=3 kW and Q.sub.rated=1.5 kVAR, respectively. Accordingly, experiments are done for single phase systems, and hence, the negative sequence SVO is disabled. The subscript ‘+’ is dropped from all parameters for simplicity, and the nominal DC bus voltage is set as v.sub.dc*=200 V. FIG. 7A shows the start-up transient, in which the DC voltage regulation is achieved using the DSUVOC without any power source on the DC bus side. Prior to start-up, the DC bus needs to be charged. By closing the STS, the DC bus is charged by operating the switch network as an uncontrolled diode-rectifier. Using the pre-synchronization block, SVO is synchronized with the voltage measured at the PoC. Note that i.sub.g measurement is excluded from the feedback to SVO during this time. Once ∥i.sub.ps∥ stabilizes, the DC bus voltage regulator and the converter switching is initiated at t.sub.1. The DC bus voltage is quickly stabilized at the reference value.

(68) Next, FIG. 7B shows the steady-state voltage and current shapes when serving 1.5 kW load and the reactive power reference is set as Q.sub.0=0. Next, reactive power dispatch is introduced, such that when a step change in the reactive power reference (Q.sub.0=500 VAR to Q.sub.0=−500 VAR) is introduced, the rectifier serves 1.2 kW DC load. The corresponding waveshapes are shown in FIG. 8A, where the reactive power reference Q.sub.0 and the output reactive power Q measured by the digital controller are shown on the scope. The opposite step response for Q.sub.0=500 VAR to Q.sub.0=−500 VAR is shown in FIG. 8B. In both cases, accurate tracking of the reactive power reference is obtained with a minimal transient. The steady-state voltage and current shapes for Q.sub.0=500 VAR and Q.sub.0=−500 VAR are shown in FIG. 9A and FIG. 9B, respectively.

(69) A step change in the DC load is introduced from 0.5 kW to 1.2 kW at t=t.sub.2 while the reactive power reference is kept at Q.sub.0=0 and the corresponding response is shown in FIG. 10. The DC bus voltage recovers quickly and the reactive power output settles back to the reference value after a small transient.

(70) DSUVOC GFM operation is validated in a hybrid AC-DC microgrid, and the microgrid structure is shown in FIG. 11. Two battery storage units are connected to 380V DC buses through non-isolated DC/DC converters, and two interlinking converters (ILCs) are used to connect the DC systems to the AC side. Each ILC can connect/disconnect to/from the AC microgrid using static transfer switches (STS.sub.1 and STS.sub.2) and the AC microgrid can be islanded using another STS.sub.g. The front-ends of the ILCs are rated at P.sub.rated=3 kW, and Q.sub.rated=1.5 kVAR. The DSUVOC parameters η and μ are selected using the guidelines listed in Table I (below) for ϕ=0 and a virtual resistance of R.sub.vir=0.2Ω is used.

(71) TABLE-US-00001 TABLE I Parameter For ϕ = π/2 For ϕ = 0 η $\frac{N{\mathrm{\Delta \omega }}_{\mathrm{ma}x}{V}_{m\mathrm{ax}}^2}{P_{\mathrm{rated}}}$ $\frac{N{\mathrm{\Delta \omega }}_{m\mathrm{ax}}{V}_{m\mathrm{ax}}^2}{Q_{\mathrm{rated}}}$ μ $\frac{2\eta Q_{\mathrm{rated}}}{N\left[{\left(2V_{m\mathrm{ax}}^2-V_0^2\right)}^2-V_0^4\right]}$ $\frac{2\eta P_{\mathrm{rated}}}{N\left[{\left(2V_{m\mathrm{ax}}^2-V_0^2\right)}^2-V_0^4\right]}$

(72) FIGS. 12A-12B show the pre-synchronization process for ILC1, when STS.sub.g is closed and STS.sub.1 is open. Before synchronization, a large phase mismatch is observed between υ.sub.f1 and υ.sub.g1 (FIG. 12A). Using an exemplary pre-synchronization method, synchronization is achieved, as shown in FIG. 12B. At this condition, ILC1 can be connected to the grid by closing STS.sub.1. The corresponding transient is shown in FIG. 13.

(73) The converter output current without using the harmonic compensation method is illustrated in FIG. 14A, in which higher order harmonics are present in the output current. Using resonant filters given in Equation (12b) at h=3, 5, 7, 9, 11, and 13, the distortion is compensated and the corresponding current shape is shown in FIG. 14B.

(74) Next, unintentional islanding is demonstrated in FIG. 15. Prior to disconnecting from the grid by opening STS.sub.g, the ILC1 draws real power from the grid (i.sub.dc1<0). At the opening of STS.sub.g, marked by the transition in grid current i.sub.gT the power-flow through the ILC1 reverses immediately and the load current i.sub.L does not experience any noticeable disturbance. Islanded operation (STS.sub.g open) of the hybrid AC-DC microgrid system is illustrated in FIG. 16, where the two interlinking converters ILC1 and ILC2 serve the AC load.

(75) An additional set of experiments is performed to validate the fault ride-through capability of the power electronic converter with DSUVOC control. FIG. 17 shows the converter response when an AC fault occurs through an impedance of 53% p.u. during islanded operation. Prior to the fault, the converter supplies a local load of 100% p.u. and the fault is introduced by shorting the load terminals. The converter output current is immediately limited to the maximum value I.sub.m=120% p.u. allowable by the converter hardware. The converter returns to normal operation as soon as the fault is cleared. FIG. 18 shows the converter response when a dead short is introduced at the converter terminal. The output current is clamped to I.sub.m and normal operation is retained as soon as the fault is cleared.

(76) Next, the fault ride-through capability of the DSUVOC controller is tested under grid-tied operation. While connected to a grid (emulated by a programmable AC source v.sub.TH and an impedance Z.sub.TH), a sudden voltage sag is introduced to emulate a grid fault. FIG. 19A shows the converter response when the converter output current does not reach the current limit I.sub.m under fault conditions, in which the converter output current is denoted as i.sub.2. The converter injects reactive power to provide voltage support at the PoC and normal operation is retained once the fault is cleared. The instants when a fault occurs and when the fault is cleared are shown in FIG. 19B and FIG. 19C, respectively. Correspondingly, FIG. 20A shows the converter responses under a more sever grid fault when the converter output current hits the maximum allowable value I.sub.m. The instants when fault occurs and when fault is cleared are shown in FIG. 20B and FIG. 20C, respectively.

(77) Next, FIG. 21 shows the simulated ride-through response under an asymmetric/unbalanced grid fault. For this set of tests, both positive and negative sequence space vector oscillators are used and the double sequence current reference generation is performed following Equation (1) to achieve constant real power flow at the converter output during an asymmetric/unbalanced fault. The equivalent three phase AC voltage source v.sub.TH is used to emulate a single line to ground fault, i.e., one of the three phase voltages is suddenly lowered from 1 p.u. to 0.3 p.u. As soon as the fault is detected in the output current, i.e., i.sub.g>I.sub.m, the DSUVOC controller clamps the output current at I.sub.m. From the real power waveform, it is evident that despite the initial transient at the instant when fault occurs, the desired constant real power flow is achieved under the fault condition.

(78) Due to its enhanced synchronization capability, an exemplary DSUVOC can enable stable converter operation under widely varying grid impedance conditions without the need for any change/tuning of control parameters. FIG. 22A-22B show converter operation under a strong grid with grid impedance of 10% p.u. FIG. 22A and FIG. 22B show no-load to full-load and full-load to no-load step responses, respectively; and FIG. 22C-22D show the converter response using identical control parameters under an ultra-weak grid with a grid impedance of 100%. No-load to full-load and full-load to no-load step responses are shown in FIG. 22C and FIG. 22D, respectively.

(79) In accordance with embodiments of the present disclosure, an exemplary DSUVOC provides a comprehensive solution for grid following and grid forming converters. Through experiments, an exemplary GFL controller is shown to retain synchronization with the grid without a dedicated PLL. DC bus voltage regulation is also demonstrated using an exemplary GFL controller. The GFM controller achieves seamless transition from islanded to grid-connected mode using the PLL-less pre-synchronization method as well as serving local loads without interruption in an event of unintentional islanding. Both symmetrical and asymmetrical fault ride-through operations under islanded and grid-tied operations have been demonstrated. Robust converter operation under widely varying grid impedances ranging from 10% p.u. to 100% p.u. using identical control parameters has been achieved.

(80) An exemplary double synchronous unified virtual oscillator controller has several advantages over existing grid-forming and grid following power electronic converter technologies. While grid-forming converters are the fundamental building blocks in self-sustaining microgrid applications, an exemplary double synchronous unified virtual oscillator controller reduces the number of voltage and current sensors in half compared to existing grid forming control methods, thereby leading to lower cost. Further, an exemplary DSUVOC controller is easily scalable enabling plug-and-play type application, thereby simplifying commissioning in the field. For grid following operations, an exemplary DSUVOC controller enables grid synchronization without phase-locked-loops which can be very useful in weak grid and ultra-weak grid conditions. For example, in an HVDC-VSC (High Voltage Direct Current-Voltage Source Converter) application, an exemplary DSUVOC controller is expected to give significant performance improvement in terms of stability.

(81) An exemplary double synchronous unified virtual oscillator controller enables fast over-current limiting and ride-through of both balanced/symmetric and unbalanced/asymmetric AC faults without the need for switching to a back-up-controller. Additionally, a PLL is not required for such fault ride-through or any mode of operation in both grid following and grid forming power electronic converters. Due to its PLL nature, robust synchronization under a variable grid condition is achieved, while a stable converter operation is achieved using identical control parameters irrespective of grid impedance variations ranging from 10% p.u. to 100 p.u.

(82) Potential applications of an exemplary grid-forming controller include, but are not limited to, battery energy storage systems, parallel UPS (uninterruptible power supply) systems, interfacing converters for distributed and renewable (such as solar, wind and wave) energy resources, and solid-state-transformers. Potential applications of an exemplary grid-following controller include, but are not limited to, a PV (photovoltaic) inverter, wind power converter, an active-front-end motor drive, HVDC-VSC, and UPS. A grid following controller may also be used in STATCOM (static synchronous compensator) and active power filter applications. The robust synchronizing capability irrespective of grid impedance variations can substantially reduce the cost of commissioning/deployment and maintenance of power electronic converter under changing grid conditions.

(83) In brief, a power electronic converter can utilize exemplar DSUVOC control logic or circuitry to convert direct current to alternating current that is input into a power grid. An exemplary DSUVOC controller includes a double synchronous space vector oscillator component, a sequence extraction (SE) component, a fault detection (FD) component, a pre-synchronization (PS) component, a virtual impedance (VI) component, a terminal voltage compensation (TVC) component, and/or an active damping (AD) component, wherein the double synchronous unified virtual oscillator controller is configured to control the power electronic converter for both grid forming and grid following modes of operation. In various embodiments, a processor of a power electronics converter can be configured to implement the DSUVOC control operations described herein. Accordingly, such operations can be programmed on a digital controller, in various embodiments.

(84) It should be emphasized that the above-described embodiments are merely possible examples of implementations, merely set forth for a clear understanding of the principles of the present disclosure. Many variations and modifications may be made to the above-described embodiment(s) without departing substantially from the principles of the present disclosure. All such modifications and variations are intended to be included herein within the scope of this disclosure.

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