Integrated circuit with mixed circuitry structure of static combinational circuit and dynamic combinational circuit and designing method thereof

Abstract

An integrated circuit includes a first stage and a second stage. The first stage receives a previous stage output data and a clock signal and generates a first output data. The second stage receives the first output data and the clock signal. The first stage includes a first flip-flop circuit, a first static combinational circuit, a dynamic combinational circuit and a multi-phase generator. The first flip-flop circuit receives the previous output data and the clock signal and generates an input data. The first static combinational circuit receives the input data and generates an intermediate data. The multi-phase generator receives the clock signal and generates a delayed clock signal. The dynamic combinational circuit receives the intermediate data and the delayed clock signal and generates the first output data.

Claims

1. An integrated circuit with a mixed circuitry structure of a static combinational circuit and a dynamic combinational circuit, the integrated circuit comprising: a first stage receiving a previous stage output data and a clock signal, and generating a first output data; and a second stage receiving the first output data and the clock signal, and generating a second output data, wherein the first stage comprises a first flip-flop circuit, a first static combinational circuit, a dynamic combinational circuit and a multi-phase generator, wherein a data input terminal of the first flip-flop circuit receives the previous output data, a clock input terminal of the first flip-flop circuit receives the clock signal, a data output terminal of the first flip-flop circuit generates an input data, the first static combinational circuit receives the input data and generates an intermediate data, the multi-phase generator receives the clock signal and generates a delayed clock signal, a data input terminal of the dynamic combinational circuit receives the intermediate data, a clock input terminal of the dynamic combinational circuit receives the delayed clock signal, and a data output terminal of the dynamic combinational circuit generates the first output data.

2. The integrated circuit as claimed in claim 1, wherein the second stage comprises a second flip-flop circuit and a second static combinational circuit, wherein a data input terminal of the second flip-flop circuit receives the first output data, a clock input terminal of the second flip-flop circuit receives the clock signal, a data output terminal of the second flip-flop circuit is connected with a data input terminal of the second static combinational circuit, and a data output terminal of the second static combinational circuit generates the second output data.

3. The integrated circuit as claimed in claim 1, wherein in a first cycle of the clock signal, the first stage processes the previous output data and generates the first output data, wherein in a second cycle of the clock signal, the second stage processes the first output data and generates the second output data.

4. The integrated circuit as claimed in claim 1, wherein the multi-phase generator comprises plural serially-connected delay elements and a multiplexer, wherein a first delay element of the plural delay elements receives the clock signal, output terminals of the plural delay elements are connected with plural input terminals of the multiplexer, and an output terminal of the multiplexer is selectively connected with one of the plural input terminals to generate the delayed clock signal.

5. A designing method of the integrated circuit according to claim 1, the designing method comprising steps of: setting the first flip-flop circuit, the first static combinational circuit, the dynamic combinational circuit and the multi-phase generator of the first stage as a macro block; performing a placement and routing operation on the integrated circuit; performing a clock tree balancing operation on the integrated circuit; and restoring the macro block to the flip-flop circuit, the static combinational circuit, the dynamic combinational circuit and the multi-phase generator.

6. The designing method as claimed in claim 5, wherein while the placement and routing operation is performed, the macro block and plural electronic elements of the second stage are arranged through an automatic placement and routing tool.

7. The designing method as claimed in claim 5, wherein plural signal input terminals of the macro block receive the previous stage output data, a clock input terminal of the macro block receives the clock signal, and plural signal output terminals of the macro block generate the first output data.

8. The designing method as claimed in claim 7, wherein while the clock tree balancing operation is performed, an automatic placement and routing tool performs a clock tree synthesis operation, so that the clock signal received by the clock input terminal of the macro block and the clock signal received by a clock input terminal of the second stage are synchronous with each other.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) The above objects and advantages of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, in which:

(2) FIG. 1 (prior art) is a schematic circuit block diagram illustrating a conventional integrated circuit;

(3) FIG. 2 (prior art) is a schematic circuit diagram illustrating a dynamic NAND gate;

(4) FIG. 3 is a schematic circuit diagram illustrating an integrated circuit with a mixed circuitry structure of a static combinational circuit and a dynamic combinational circuit;

(5) FIG. 4 is a schematic circuit diagram illustrating an integrated circuit with a mixed circuitry structure of a static combinational circuit and a dynamic combinational circuit according to an embodiment of the present invention;

(6) FIG. 5 is a schematic circuit diagram illustrating the multi-phase generator of the integrated circuit as shown in FIG. 4; and

(7) FIG. 6 is a flowchart of a designing method of the integrated circuit according to the embodiment of the present invention.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

(8) The present invention provides an integrated circuit with a mixed circuitry structure of a static combinational circuit and a dynamic combinational circuit. In particular, at least one stage of the integrated circuit comprises a dynamic combinational circuit. FIG. 3 is a schematic circuit diagram illustrating an integrated circuit with a mixed circuitry structure of a static combinational circuit and a dynamic combinational circuit.

(9) The circuit diagram of the integrated circuit comprises plural stages. For succinctness, only an n-th stage 310 and an (n+1)-th stage 320 are shown. These stages are operated according to a clock signal CLK. The n-th stage 310 comprises a flip-flop circuit 312, a static combinational circuit 314 and a dynamic combinational circuit 316. The (n+1)-th stage 320 comprises a flip-flop circuit 322 and a static combinational circuit 324. The clock input terminals CKin of the flip-flop circuits 312 and 322 receive the clock signal CLK. Moreover, each of the flip-flop circuits 312 and 322 comprises plural latches.

(10) In the n-th stage 310, the flip-flop circuit 312 latches the output data Dout.sub.n−1 of the previous stage as the input data Din.sub.n. After the static combinational circuit 314 receives and processes the input data Din.sub.n, an intermediate data Dx is generated. The clock input terminal CKin of the dynamic combinational circuit 316 receives the clock signal CLK. According to the clock signal CLK, the dynamic combinational circuit 316 receives and processes the intermediate data Dx. Consequently, the output data Dout.sub.n of the n-th stage 310 is generated.

(11) Similarly, in the (n+1)-th stage 320, the flip-flop circuit 322 latches the output data Dout.sub.n of the n-th stage 310 as the input data Din.sub.n+1. After the static combinational circuit 324 receives and processes the input data Din.sub.n+1, the output data Dout.sub.n+1 of the (n+1)-th stage 320 is generated.

(12) The operation of the integrated circuit as shown in FIG. 3 will be described as follows. In the previous cycle of the clock signal CLK, the n-th stage 310 has to process the output data Dout.sub.n−1 of the previous stage and generate the output data Dout.sub.n of the n-th stage 310. In the next cycle of the clock signal CLK, the (n+1)-th stage 320 has to process the output data Dout.sub.n of the n-th stage 310 and generate the output data Dout.sub.n+1 of the (n+1)-th stage 320.

(13) After the circuit diagram of FIG. 3 is designed, it is necessary to use an automatic placement and routing tool to perform a layout action. The automatic placement and routing too is also referred as an APR tool. The integrated circuit as shown in FIG. 3 has the mixed circuitry structure of a static combinational circuit and a dynamic combinational circuit. After the APR tool performs the clock tree balancing operation on the clock signal CLK, the clock signals CLK received by the clock input terminals CKin of all stages are synchronous with each other. In addition, the integrated circuit cannot be operated normally. The reasons will be described.

(14) Generally, it takes a specified processing time from the time point of receiving the input data Dine to the time point of generating the intermediate data Dx. As mentioned above, the clock signal CLK received by the clock input terminal CKin of the flip-flop circuit 312 in the n-th stage 310 and the clock signal CLK received by the clock input terminal CKin of the dynamic combinational circuit 316 are synchronous with each other. When the dynamic combinational circuit 316 is enabled according to the clock signal CLK, the flip-flop circuit 312 is starting to latch the output data Dout.sub.n−1. Consequently, it is determined that the intermediate data Dx of the static combinational circuit 314 is not ready. Since the dynamic combinational circuit 316 is unable to correctly receive the intermediate data Dx, the output data Dout.sub.n is generated incorrectly.

(15) In order to solve the above problems and allow the integrated circuit to operate normally, the integrated circuit of the present invention is further equipped with a multi-phase generator. The multi-phase generator is used for dynamically adjusting the delay time of the clock signal. Consequently, the integrated circuit can be operated correctly.

(16) FIG. 4 is a schematic circuit diagram illustrating an integrated circuit with a mixed circuitry structure of a static combinational circuit and a dynamic combinational circuit according to an embodiment of the present invention. The circuit diagram of the integrated circuit comprises plural stages. For succinctness, only an n-th stage 410 and an (n+1)-th stage 320 are shown. These stages are operated according to a clock signal CLK. The n-th stage 410 comprises a flip-flop circuit 412, a static combinational circuit 414, a multi-phase generator 418 and a dynamic combinational circuit 416. The structure of the (n+1)-th stage 320 is identical to that of FIG. 3, and not redundantly described herein. The clock input terminals CKin of the flip-flop circuits 412 and 322 receive the clock signal CLK. Moreover, each of the flip-flop circuits 412 and 322 comprises plural latches.

(17) In the n-th stage 410, the data input terminal of the flip-flop circuit 412 receives the output data Dout.sub.n−1 of the previous stage, and the output data Dout.sub.n−1 is latched as the input data Dine. Moreover, the data output terminal of the flip-flop circuit 412 generates the input data Dine. After the static combinational circuit 414 receives and processes the input data Dine, an intermediate data Dx is generated. The multi-phase generator 418 receives the clock signal CLK and generated a delayed clock signal CLK_d. The clock input terminal CKin of the dynamic combinational circuit 416 receives the delayed clock signal CLK_d. The data input terminal of the dynamic combinational circuit 416 receives the intermediate data Dx. The data output terminal of the dynamic combinational circuit 416 generates the output data Dout.sub.n. That is, according to the delayed clock signal CLK_d, the dynamic combinational circuit 416 receives and processes the intermediate data Dx. Consequently, the output data Dout.sub.n of the n-th stage 410 is generated.

(18) Similarly, in the (n+1)-th stage 320, the data input terminal of the flip-flop circuit 322 receives the output data Dout.sub.n of the n-th stage 310, and the output data Dout.sub.n is latched as the input data Din.sub.n+1. Moreover, the data output terminal of the flip-flop circuit 322 generates the input data Din.sub.n+1. After the static combinational circuit 324 receives and processes the input data Din.sub.n+1, the output data Dout.sub.n+1 of the (n+1)-th stage 320 is generated.

(19) Generally, it takes a specified processing time from the time point of receiving the input data Dine to the time point of generating the intermediate data Dx. The phase of the delayed clock signal CLK_d from the multi-phase generator 418 lags the clock signal CLK for at least the processing time. When the dynamic combinational circuit 416 is enabled according to the delayed clock signal CLK_d, it is determined that the intermediate data Dx of the static combinational circuit 414 is ready. Since the dynamic combinational circuit 416 is able to correctly receive the intermediate data Dx, the output data Dout.sub.n is generated correctly.

(20) From the above descriptions, the associated signals are generated during the normal operation of the integrated circuit. In the previous cycle of the clock signal CLK, the n-th stage 410 processes the output data Dout.sub.n−1 of the previous stage and generates the output data Dout.sub.n of the n-th stage 410. In the next cycle of the clock signal CLK, the (n+1)-th stage 320 processes the output data Dout.sub.n of the n-th stage 310 and generates the output data Dout.sub.n+1 of the (n+1)-th stage 320.

(21) FIG. 5 is a schematic circuit diagram illustrating the multi-phase generator of the integrated circuit as shown in FIG. 4. The multi-phase generator 418 comprises plural serially-connected delay elements 501˜50y and a multiplexer 520. Each of the delay elements 501˜50y can delay the received clock signal for a unit delay time. The first delay element 501 receives the clock signal CLK and generates a clock signal CLK1. The second delay element 502 receives the clock signal CLK1 and generates a clock signal CLK2. The rest may be deduced by analogy. The y-th delay element 50y receives the clock signal CLKy-1 and generates a clock signal CLKy. The multiplexer 520 receives the clock signals CLK1˜CLKy from the delay elements 501˜50y. The output terminal of the multiplexer 520 is connected with one of plural input terminals of the multiplexer 520, and thus one of the clock signals CLK1˜CLKy is selectively outputted. Consequently, the delayed clock signal CLK_d is outputted from the output terminal of the multiplexer 520. In other words, during the operation of the integrated circuit, a control circuit (not shown) of the integrated circuit selects the suitable delayed clock signal CLK_d to the dynamic combinational circuit 416 through the multiplexer 520 according to the processing time of the static combinational circuit 414.

(22) The present invention further comprises a designing method of the integrated circuit. FIG. 6 is a flowchart of a designing method of the integrated circuit according to the embodiment of the present invention.

(23) After the circuit diagram of the integrated circuit is designed, the flip-flop circuit, the static combinational circuit, the multi-phase generator and the dynamic combinational circuit in the stage of the integrated circuit with the mixed circuitry structure of the static combinational circuit and the dynamic combinational circuit are set as a macro block (Step S602). In an embodiment, the macro block is considered as an electronic element. For example, as shown in FIG. 4, the flip-flop circuit 412, the static combinational circuit 414, the dynamic combinational circuit 416 and the multi-phase generator 418 are set as a macro block. The signal input terminals of the macro block receive the output data Dout.sub.n−1 of the previous stage, the clock input terminal CLKin of the macro block receives the clock signal CLK, and the signal output terminals of the macro block generate the output data Dout.sub.n.

(24) Then, the integrated circuit undergoes a placement and routing operation (Step S604). That is, the ARP tool is used to arrange the macro block and the other electronic elements of the (n+1)-th stage 320.

(25) Then, the integrated circuit undergoes a clock tree balancing operation (Step S606). That is, the ARP tool is used to perform the clock tree balancing operation on the clock signal. Consequently, the clock signal CLK received by the clock input terminal CKin of the macro block and the clock signal CLK received by the clock input terminal CKin of the (n+1)-th stage are synchronous with each other.

(26) Then, the macro block is restored to the flip-flop circuit 412, the static combinational circuit 414, the dynamic combinational circuit 416 and the multi-phase generator 418 (Step S608).

(27) As mentioned above, the ARP tool is used to perform the clock tree balancing operation. In particular, the clock tree synthesis (CTS) operation performed by the ARP tool is only aimed at the clock input terminal of the macro block and the clock input terminals of other stages. In other words, the clock input terminal of the dynamic combinational circuit of the macro block is not subjected to the clock tree balancing operation by the ARP tool.

(28) After the clock tree balancing operation is completed, the macro block is restored to the flip-flop circuit, the static combinational circuit, the dynamic combinational circuit and the multi-phase generator. Since the clock signal received by the clock input terminal of the dynamic combinational circuit and the clock signal received by the clock input terminal of the flip-flop circuit are not synchronous with each other, the integrated circuit can be operated normally.

(29) While the invention has been described in terms of what is presently considered to be the most practical and preferred embodiments, it is to be understood that the invention needs not be limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangements included within the spirit and scope of the appended claims which are to be accorded with the broadest interpretation so as to encompass all such modifications and similar structures.