Single-ended successive approximation register analog-to-digital converter

Abstract

A single-ended successive approximation register (SAR) analog-to-digital converter (ADC) includes a first digital-to-analog converter (DAC) having a first capacitor associated with a most significant bit (MSB) of the output code, and a second capacitor associated with other bit or bits of the output code; and a second DAC having a first capacitor associated with a MSB of the output code, and a second capacitor associated with other bit or bits of the output code. A bottom plate of the first capacitor of the second DAC is connected to a negative reference voltage in all phases.

Claims

1. A single-ended successive approximation register (SAR) analog-to-digital converter (ADC), comprising: a first digital-to-analog converter (DAC) coupled to receive an input voltage via a first sampling switch; a second DAC coupled to receive a ground voltage via a second sampling switch; a comparator having a positive input node coupled to receive a first output voltage of the first DAC, and a negative input node coupled to receive a second output voltage of the second DAC; and a SAR controller that controls switching of the first DAC and the second DAC according to a comparison output of the comparator, thereby generating an output code; wherein the first DAC includes a first capacitor associated with a most significant bit (MSB) of the output code, and a second capacitor associated with other bit or bits of the output code; and the second DAC includes a first capacitor associated with a MSB of the output code, and a second capacitor associated with other bit or bits of the output code; wherein a bottom plate of the first capacitor of the second DAC is connected to a negative reference voltage in all phases; wherein the first DAC further comprises a redundant capacitor having a top plate connected to an input node of the first DAC and a bottom plate switchably connected to the positive reference voltage and the negative reference voltage; and the second DAC further comprises a redundant capacitor having a top plate connected to an input node of the second DAC and a bottom plate switchably connected to the positive reference voltage and the negative reference voltage; wherein in sampling phase the redundant capacitor of the first DAC and the redundant capacitor of the second DAC are switchably coupled to receive the positive reference voltage.

2. The single-ended SAR ADC of claim 1, further comprising: a first boost switch coupled between the positive input node of the comparator and a common mode boost voltage; and a second boost switch coupled between the negative input node of the comparator and the common mode boost voltage.

3. The single-ended SAR ADC of claim 1, wherein the SAR controller enters a single-ended mode or a differential mode according to a mode signal, wherein in the differential mode, a differential input voltage is sampled by the first DAC and the second DAC via the first sampling switch and the second sampling switch, and the bottom plate of the first capacitor of the second DAC is connected to a positive reference voltage or the negative reference voltage according to control of the SAR controller.

4. The single-ended SAR ADC of claim 1, wherein top plates of the first capacitor and the second capacitor of the first DAC are connected together to the input node of the first DAC, top plates of the first capacitor and the second capacitor of the second DAC are connected together to the input node of the second DAC, bottom plates of the first capacitor and the second capacitor of the first DAC are switchably connected to a positive reference voltage and the negative reference voltage, and bottom plates of the first capacitor and the second capacitor of the second DAC are switchably connected to the positive reference voltage and the negative reference voltage.

5. The single-ended SAR ADC of claim 1, wherein the first DAC further comprises a boost capacitor coupled between the input node and an output node of the first DAC, and the second DAC further comprises a boost capacitor coupled between the input node and an output node of the second DAC.

6. The single-ended SAR ADC of claim 1, wherein the first DAC further comprises: a first parasitic capacitor having a top plate coupled to the input node of the first DAC, and a bottom plate coupled to receive a parasitic voltage; and a second parasitic capacitor having a top plate coupled to an output node of the first DAC, and a bottom plate coupled to receive the parasitic voltage.

7. A single-ended successive approximation register (SAR) analog-to-digital converter (ADC), comprising: a first digital-to-analog converter (DAC) coupled to receive an input voltage via a first sampling switch; a second DAC coupled to receive a ground voltage via a second sampling switch; a comparator having a positive input node coupled to receive a first output voltage of the first DAC, and a negative input node coupled to receive a second output voltage of the second DAC; and a SAR controller that controls switching of the first DAC and the second DAC according to a comparison output of the comparator, thereby generating an output code; wherein the first DAC includes a first capacitor associated with a most significant bit (MSB) of the output code, and a second capacitor associated with other bit or bits of the output code; and the second DAC includes a first capacitor associated with a MSB of the output code, and a second capacitor associated with other bit or bits of the output code; wherein a bottom plate of the first capacitor of the second DAC is connected to a negative reference voltage in all phases; wherein in sampling phase the first capacitor and the second capacitor of the first DAC are switchably coupled to receive a positive reference voltage, and the second capacitor of the second DAC is switchably coupled to receive the negative reference voltage; wherein the first sampling switch and the second sampling switch are turned on in the sampling phase to respectively sample the input voltage and the ground voltage.

8. The single-ended SAR ADC of claim 7, wherein the sampling phase is followed by top-plate level shifting phase, in which the second capacitor of the second DAC is switchably coupled to receive the positive reference voltage.

9. The single-ended SAR ADC of claim 8, wherein the first sampling switch and the second sampling switch are turned off in the top-plate level shifting phase.

10. The single-ended SAR ADC of claim 1, wherein the sampling phase is followed by top-plate level shifting phase, in which the second capacitor of the second DAC is switchably coupled to receive the positive reference voltage.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1A shows a block diagram illustrating a single-ended successive approximation register (SAR) analog-to-digital converter (ADC) according to one embodiment of the present invention;

(2) FIG. 1B shows a detailed circuit diagram of the single-ended SAR ADC of FIG. 1A;

(3) FIG. 2A to FIG. 2C show configurations of the single-ended SAR ADC before sampling, in sampling phase and in top-plate level shifting phase, respectively; and

(4) FIG. 3 shows exemplary waveforms at the input node and the output node of the (first/second) DAC.

DETAILED DESCRIPTION OF THE INVENTION

(5) FIG. 1A shows a block diagram illustrating a single-ended successive approximation register (SAR) analog-to-digital converter (ADC) 100 according to one embodiment of the present invention, and FIG. 1B shows a detailed circuit diagram of the single-ended SAR ADC 100 of FIG. 1A.

(6) In the embodiment, the single-ended SAR ADC 100 may include a first digital-to-analog converter (DAC) 11A coupled, at its input node, to receive an input voltage V.sub.i via a first sampling switch SW1. The input voltage V.sub.i may swing between a full-scale voltage (e.g., 1 volt) and a ground voltage (e.g., 0 volt). The single-ended SAR ADC 100 may include a second DAC 11B coupled, at its input node, to receive the ground voltage via a second sampling switch SW2.

(7) The single-ended SAR ADC 100 of the embodiment may include a comparator 12 having a positive input node coupled to receive a first output voltage V.sub.o1 (at an output node) of the first DAC 11A, and a negative input node coupled to receive a second output voltage V.sub.o2 (at an output node) of the second DAC 11B. The single-ended SAR ADC 100 of the embodiment may include a first boost switch SW.sub.b1 coupled between the positive input node of the comparator 12 and a common mode boost voltage V.sub.com_boost, and a second boost switch SWb.sub.2 coupled between the negative input node of the comparator 12 and the common mode boost voltage V.sub.com_boost. The first boost switch SW.sub.b1 and the second boost switch SW.sub.b2 can raise a common mode voltage for the comparator 12.

(8) The single-ended SAR ADC 100 of the embodiment may include a SAR controller 13 configured to control switching of the first DAC 11A and the second DAC 11B according to a comparison output of the comparator 12, thereby generating an output code from a most significant bit (MSB) to a least significant bit (LSB) in sequence. The SAR controller 13 may enter a single-ended mode or a differential mode according to a mode signal Sm. The single-ended mode is assumed in the following embodiment.

(9) Specifically, the first DAC 11A may include a first capacitor C.sub.T1, a second capacitor C.sub.T2 and an (optional) redundant capacitor C.sub.redun. The first capacitor C.sub.T1 is associated with the most significant bit (MSB) of the output code, and the second capacitor C.sub.T2 is associated with other bit(s) of the output code. In the embodiment, the second capacitor C.sub.T2 may represent a plurality of parallel-connected capacitors collectively. Top plates of the first capacitor C.sub.T1, the second capacitor C.sub.T2 and the redundant capacitor C.sub.redun may be connected together to the input node of the first DAC 11A. Bottom plates of the first capacitor C.sub.T1, the second capacitor C.sub.T2 and the redundant capacitor C.sub.redun may be switchably connected to a positive reference voltage V.sub.refp (e.g., 1 volt) and a negative reference voltage V.sub.refn (e.g., 0 volt). The first DAC 11A may include a boost capacitor C.sub.com_boost coupled between the input node and the output node of the first DAC 11A for raising the common mode voltage for the comparator 12.

(10) In one embodiment, the first DAC 11A may include a first parasitic capacitor C.sub.para1 having a top plate coupled to the input node of the first DAC 11A, and a bottom plate coupled to receive a parasitic voltage V.sub.para. The first DAC 11A may include a second parasitic capacitor C.sub.para2 having a top plate coupled to the output node of the first DAC 11A, and a bottom plate coupled to receive the parasitic voltage V.sub.para.

(11) Similarly, the second DAC 11B may include a first capacitor C.sub.T1, a second capacitor C.sub.T2 and an (optional) redundant capacitor C.sub.redun. The first capacitor C.sub.T1 is associated with the most significant bit (MSB) of the output code, and the second capacitor C.sub.T2 is associated with other bit(s) of the output code. In the embodiment, the second capacitor C.sub.T2 may represent a plurality of parallel-connected capacitors collectively. Top plates of the first capacitor C.sub.T1, the second capacitor C.sub.T2 and the redundant capacitor C.sub.redun are connected together to the input node of the second DAC 11B. Bottom plates of the first capacitor C.sub.T1, the second capacitor C.sub.T2 and the redundant capacitor C.sub.redun may be switchably connected to a positive reference voltage V.sub.refp (e.g., 1 volt) and a negative reference voltage V.sub.refn (e.g., 0 volt). The second DAC 11B may include a boost capacitor C.sub.com_boost coupled between the input node and the output node of the second DAC 11B.

(12) In one embodiment, the second DAC 11B may include a first parasitic capacitor C.sub.para1 having a top plate coupled to the input node of the second DAC 11B, and a bottom plate coupled to receive the parasitic voltage V.sub.para. The second DAC 11B may include a second parasitic capacitor C.sub.para2 having a top plate coupled to the output node of the second DAC 11B, and a bottom plate coupled to receive the parasitic voltage V.sub.para.

(13) FIG. 2A to FIG. 2C show configurations of the single-ended SAR ADC 100 before sampling (or at end of previous conversion phase), in sampling phase and in top-plate level shifting phase, respectively. FIG. 3 shows exemplary waveforms at the input node and the output node of the (first/second) DAC 11A/11B.

(14) Specifically, in sampling phase as shown in FIG. 2B, the first sampling switch SW1 and the second sampling switch SW2 are turned on (i.e., closed) to respectively sample the input voltage V.sub.i and the ground voltage, and the first boost switch SW.sub.b1 and the second boost switch SW.sub.b2 are turned off (i.e., open). According to one aspect of the embodiment, the bottom plate of the first capacitor C.sub.T1 of the second DAC 11B may be switchably connected to the negative reference voltage V.sub.refn (e.g., 0 volt) in all phases of each cycle.

(15) According to another aspect of the embodiment, in sampling phase, the first capacitor C.sub.T1, the second capacitor C.sub.T2 and the redundant capacitor C.sub.redun of the first DAC 11A and the redundant capacitor C.sub.redun of the second DAC 11B are swichably coupled to receive the positive reference voltage V.sub.refp, while the second capacitor C.sub.T2 of the second DAC 11B are switchably coupled to receive the negative reference voltage V.sub.refn. In one embodiment, the positive reference voltage V.sub.refp for an N-bit single-ended SAR ADC 100 may be expressed as
V.sub.refp=(2.sup.N−1+C.sub.para1+C.sub.redun±(C.sub.com_boost∥C.sub.para2))/2.sup.N−1

(16) In top-plate level shifting phase as shown in FIG. 2C, the first sampling switch SW1 and the second sampling switch SW2 are turned off (i.e., open), and the first boost switch SW.sub.b1 and the second boost switch SW.sub.b2 remain turned off (i.e., open). According to one aspect of the embodiment, in top-plate level shifting phase, the first capacitor C.sub.T1, the second capacitor C.sub.T2 and the redundant capacitor C.sub.redun of the first DAC 11A and the redundant capacitor C.sub.redun of the second DAC 11B remain coupled to receive the positive reference voltage V.sub.refp, the first capacitor C.sub.T1 of the second DAC 11B remains coupled to receive the negative reference voltage V.sub.refn, but the second capacitor C.sub.T2 of the second DAC 11B is switchably coupled to receive the positive reference voltage V.sub.refp. The top-plate level shifting phase is followed by conversion phase and pre-charging phase.

(17) According to the embodiment as disclosed above, a comparison benchmark at the input node of the second DAC 11B may be properly generated according to swing of the positive reference voltage V.sub.refp. Specifically, the comparison benchmark is generated according to voltage division among the first capacitor C.sub.T1, the second capacitor C.sub.T2 and the redundant capacitor C.sub.redun of the second DAC 11B.

(18) In the differential mode, a differential input voltage (not shown) is sampled by the first DAC 11A and the second DAC 11B via the first sampling switch SW1 and the second sampling switch SW2 respectively, and the bottom plate of the first capacitor C.sub.T1 of the second DAC 11B is connected to the positive reference voltage V.sub.refp or the negative reference voltage V.sub.refn according to the control of the SAR controller 13.

(19) Although specific embodiments have been illustrated and described, it will be appreciated by those skilled in the art that various modifications may be made without departing from the scope of the present invention, which is intended to be limited solely by the appended claims.