Superconducting qubit with tapered junction wiring

Abstract

Error correction can only work with superconducting qubits if qubit errors are lowered. Surface loss from thin oxides is currently a dominant error mechanism. Formulas for useful qubit geometries are presented to predict surface loss, which can be used to optimize the qubit layout. A significant fraction of surface loss comes from the small wire that connects the Josephson junction to the qubit capacitor. Tapering this wire is shown to significantly lower its loss, as well as etching the underlying silicon to create free-standing wires.

Claims

1. A superconducting qubit device comprising: a Josephson tunnel junction; a capacitor external to the Josephson junction; and an electrical connection between the Josephson junction and the capacitor, the electrical connection comprising a tapered wire that has a narrower width at the Josephson junction and a wider width at the capacitor.

2. The superconducting qubit device of claim 1, wherein the electrical connection has a smooth taper.

3. The superconducting qubit device of claim 1, wherein the electrical connection has a linear taper.

4. The superconducting qubit device of claim 3, wherein the taper of the electrical connection has slope of at least 0.2.

5. The superconducting qubit device of claim 3, wherein the taper of the electrical connection has slope of at least 0.1.

6. The superconducting qubit device of claim 1, wherein the length of the tapered electrical connection from the capacitor to the Josephson junction is approximately 50 μm.

7. The superconducting qubit device of claim 1, wherein the substrate is etched underneath the taper.

8. The superconducting qubit device of claim 7, wherein the substrate is etched underneath the taper at least approximately 5 μm.

9. The superconducting qubit device of claim 1, wherein the substrate is etched underneath the taper and unetched underneath the junction.

10. The superconducting qubit device of claim 9, wherein the substrate is etched underneath the taper at least approximately 5 μm.

11. The superconducting qubit device of claim 9, wherein the substrate is unetched within 5 μm of the junction.

12. A superconducting qubit device comprising: a Josephson tunnel junction; a capacitor external to the Josephson junction; and an electrical connection between the Josephson junction and the capacitor, wherein the surface loss of the device is modeled by: a parallel plate capacitor, having an effective loss tangent
tan(δ.sub.PP)=(1/ε.sub.MA)tan(δ.sub.mA)(t.sub.MA/L.sub.C)(A/s.sup.2), where tan(δ.sub.PP) is the effective loss tangent of the parallel plate capacitor, ε.sub.MA is dielectric constant of the metal-air interface, tan(δ.sub.MA) is the loss tangent of the metal-air interface, t.sub.MA is the thickness of the metal-air interface, L.sub.C=C/ε.sub.0 is the total capacitance C divided by the vacuum permittivity, A is the area of the parallel plate, and s is the separation of the parallel plates; a ribbon capacitor, having an effective loss tangent
tan(δ.sub.DR)=(ε.sub.S.sup.2/ε.sub.MS)tan(δ.sub.MS)(t.sub.MS/L.sub.C)(L.sub.r/d)(1+2.2(d/w).sup.0.8)(1/π.sup.2)(ln(4 d/t)+4.1), where tan(δ.sub.DR) is the effective loss tangent of the differential ribbon capacitor, ε.sub.S is dielectric constant of the substrate, ε.sub.MS is dielectric constant of the metal-substrate interface, tan(δ.sub.MS) is the loss tangent of the metal-substrate interface, t.sub.MS is the thickness of the metal-air interface oxide, L.sub.C=C/ε.sub.0 is the total capacitance C divided by the vacuum permittivity, L.sub.r is the length of the ribbon capacitor, 2 d is the distance between the two electrodes of the ribbon capacitor, w is the width of each electrode of the ribbon capacitor, t is the thickness of each electrode of the ribbon capacitor; a differential coplanar capacitor, having an effective loss tangent
tan(δ.sub.DC)=(ε.sub.S.sup.2/ε.sub.MS)tan(δ.sub.MS)(t.sub.MS/L.sub.C)[2L.sub.c/w+2L.sub.c/(w+2g)](0.33c.sub.c/π).sup.2(ln(2 w/t)+4.1), where tan(δ.sub.DC) is the effective loss tangent of the differential coplanar capacitor, ε.sub.S is dielectric constant of the substrate, ε.sub.MS is dielectric constant of the metal-substrate interface, tan(δ.sub.MS) is the loss tangent of the metal-substrate interface, t.sub.MS is the thickness of the metal-air interface oxide, L.sub.C=C/ε.sub.0 is the total capacitance C divided by the vacuum permittivity, L.sub.c is the length of the coplanar capacitor, w is the width of inner coplanar electrode, g is the gap between the inner electrodes and the ground plane, t is the thickness of each electrode of the coplanar capacitor, and c.sub.c=ln[2(1+sqrt[w/(w+2g)])/(1−sqrt[w/(w+2g)])]; an untapered junction wire, having an effective loss tangent
tan(δ.sub.UW)=(ε.sub.S.sup.2/ε.sub.MS)tan(δ.sub.MS)(t.sub.MS/L.sub.C)(d/w)(ln(2 w/t)+4.1)/ln.sup.2(2 d/w), where tan(δ.sub.UW) is the effective loss tangent of the untapered wire, ε.sub.S is dielectric constant of the substrate, ε.sub.MS is dielectric constant of the metal-substrate interface, tan(δ.sub.MS) is the loss tangent of the metal-substrate interface, t.sub.MS is the thickness of the metal-air interface oxide, L.sub.C=C/ε.sub.0 is the total capacitance C divided by the vacuum permittivity, d is the length of the wire from the junction to the capacitor electrode, w is the width of wire, and t is the thickness of wire; and a tapered junction wire, having an effective loss tangent:
tan(δ.sub.TW)=(ε.sub.S.sup.2/ε.sub.MS)tan(δ.sub.MS)(t.sub.MS/L.sub.C)(ln(2 d/w.sub.0)/S)0.44(ln(4 Sd/t)+4.1)/ln.sup.2(4/S), where tan(δ.sub.TW) is the effective loss tangent of the untapered wire, ε.sub.S is dielectric constant of the substrate, ε.sub.MS is dielectric constant of the metal-substrate interface, tan(δ.sub.MS) is the loss tangent of the metal-substrate interface, t.sub.MS is the thickness of the metal-air interface oxide, L.sub.C=C/ε.sub.0 is the total capacitance C divided by the vacuum permittivity, d is the length of the wire from the junction to the capacitor electrode, w.sub.0 is the initial width of the wire at the junction, S is the slope of the taper, and t is the thickness of wire.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 is a plan view of the differential thin-film transmon device, in accordance with an embodiment of the invention. The two long ribbons of width 106, length 105 and separation 107 are the qubit capacitor 101. They are connected to the junction 102 via junction wires drawn for the untapered 103 and tapered 104 designs.

(2) FIG. 2 is a plan view of an example differential transmon qubit, with junction 201 and taped junction wires 204, in accordance with an embodiment of the invention. The qubit capacitance is a composite of a ribbon 202 and coplanar 203, both surrounded by a ground plane 205.

(3) FIG. 3 is a plan view of a differential coplanar capacitor, with junction 301 and junction wires 302, here untapered, in accordance with an embodiment of the invention. The qubit capacitor 303 with width 306 and length 305 is separated from the ground plane 304 by a gap 307.

(4) FIG. 4 is a plot of the surface loss (arbitrary units) versus the junction wire length, for both a tapered and untapered design, in accordance with an embodiment of the invention.

(5) The figures depict various embodiments of the present invention for purposes of illustration only. One skilled in the art will readily recognize from the following discussion that alternative embodiments of the structures and methods illustrated herein may be employed without departing from the principles of the invention described herein.

DETAILED DESCRIPTION

(6) For thin films suitable for superconducting qubits, the electric fields have to be calculated numerically. Fortunately, realistic transmon designs are well approximated by simple geometries with fields that can be well described using simple fitting functions, so that they can be physically understood and optimized. Two-dimensional geometries are particularly amenable to efficient numerical solutions, even though the electric fields diverge at the film edges. The fitting functions for the electric field generally scale as 1/r.sub.c.sup.1/2, where r.sub.c is the distance from the edge of a long thin film. The effect of the thickness t of the film can be included by modifying the above scaling for distances r.sub.c<t/2 by matching the electric field magnitude at t/2 but having it continue to scale as 1/r.sub.c.sup.1/3. More accurate results may be obtained by modifying fit functions based on this scaling to numerical results.

(7) From these surface electric fields E.sub.s, the effective loss tangent tan(δ.sub.eff) from all of the surface loss can be calculated by a standard integration of the field energy over the surface
tan(δ.sub.eff)=SurfaceIntegral(E.sub.s.sup.2t.sub.s tan(δ)ε/2)/(CV.sup.2/2),
where t.sub.s is the thickness of the lossy surface (typically a few nm), tan(δ) is its surface dielectric loss (typically 0.002), c is the surface dielectric constant, and CV.sup.2/2 is the total capacitive energy of the device. As E.sub.s scales with V, this formula is independent of the size of the field and only depends on geometry and the dissipation physics.

(8) For the practical situation of the device fabricated on a silicon substrate with relative dielectric constant ε.sub.S=10, the loss is broken up into interface (surface) components of the metal-substrate (MS), metal-air (MA) and substrate-air (SA). Their relative dielectric constants are ε.sub.MA, ε.sub.MS, and ε.sub.SA, with typical values of 10, 3.8, and 3.8 respectively. To compute the surface loss for the three interfaces, the numerical results for tan(δ.sub.eff) are first computed with a relative dielectric constant of 1, is then scaled by the dielectric constants for the 3 interfaces:
tan(δ.sub.MA)=(1/ε.sub.MA)tan(δ.sub.eff),
tan(δ.sub.MS)=(ε.sub.S.sup.2/ε.sub.MS)tan(δ.sub.eff),
tan(δ.sub.SA)=(ε.sub.SA)tan(δ.sub.eff).
The dielectric constant terms in parenthesis for these formulas are typically 0.1, 26 and 3.8, so the MS interface typically dominates by a large factor. Only the dominant interface is discussed below.

(9) A differential parallel plate capacitor typically uses a vacuum (“air”) dielectric between the parallel plates. Thus the dominant dielectric loss tangent is from the MA term, giving
tan(δ.sub.PP)=(1/ε.sub.MA)tan(δ.sub.MA)(t.sub.MA/L.sub.C)(A/s.sup.2),
where tan(δ.sub.MA) is the loss tangent and t.sub.MA is the thickness of the surface oxide, L.sub.C=C/ε.sub.0 is the qubit total capacitance expressed in distance units, typically with L.sub.C=11.3 mm, and A is the area of the parallel plates and s are their separation distance.

(10) For a differential ribbon capacitor shown in FIG. 1, the dominant loss comes from the MS interface, with loss tangent
tan(δ.sub.DR)=(ε.sub.S.sup.2/ε.sub.MS)tan(δ.sub.MS)(t.sub.MS/L.sub.C)(L.sub.r/d)(1+2.2(d/w).sup.0.8)(1/π.sup.2)(ln(4 d/t)+4.1),
where tan(δMS) is the loss tangent and t.sub.MS is the thickness of the surface oxide, L.sub.r is the length of the ribbon (105), w is the width of ribbon (106), 2 d is the gap between the ribbons (107), and t is the metal thickness.

(11) For a differential coplanar capacitor shown in FIG. 3 embedded in a ground plane 304, the dominant loss comes from the MS interface, with loss tangent
tan(δ.sub.DC)=(ε.sub.S.sup.2/ε.sub.MS)tan(δ.sub.MS)(t.sub.MS/L.sub.C)[2L.sub.c/w+2L.sub.c/(w+2g)](0.33c.sub.c/π).sup.2(ln(2 w/t)+4.1),c.sub.c=ln[2(1+sqrt[w/(w+2g)])/(1−sqrt[w/(w+2g)])],
where L.sub.c is the length of the coplanar pad (305), w is the width of pad (306), and g is the gap between the ribbons (307). The logarithmic dependence for c.sub.c enables an approximation for the typical case w=g, giving c.sub.c=2.

(12) For the case of an untapered (straight) wire as shown in FIG. 1, the dominant loss comes from the MS interface, with loss tangent
tan(δ.sub.UW)=(ε.sub.S.sup.2/ε.sub.MS)tan(δ.sub.MS)(t.sub.MS/L.sub.C)(d/w)(ln(2 w/t)+4.1)/ln.sup.2(2 d/w),
where 2 d is the total length of the wire and w is the width of the wire. For the case of the tapered wire, the loss tangent is
tan(δ.sub.TW)=(ε.sub.S.sup.2/c.sub.MS)tan(δ.sub.MS)(t.sub.MS/L.sub.C)(ln(2 d/w.sub.0)/S)0.44(ln(4Sd/t)+4.1)/ln.sup.2(4/S)
where w.sub.0 is the width of the wire at the junction, and S is the slope of the taper for one edge. Here S=0 corresponds to an untapered wire, and the latter formula is only valid for S>0.05.

(13) In one embodiment, the wire has a linear taper, where the slope of the wire is constant. As used herein, slope is defined as the change in thickness of the wire along its length. In various embodiments the taper of the electrical connection has slope of at least 0.2, at least 0.1, or any other suitable slope range. In another embodiment, the wire has a smooth taper that may be nonlinear, where “smooth” means that the slope of the wire is free of discontinuities or sharp edges.

(14) A comparison of the untapered (straight) and tapered wire is shown in FIG. 4, which shows significantly lower loss for a distance d of the junction wire greater than about 10 μm. Here t=w/2=0.1 μm and S=0.4. This design would improve present transmon qubits.

(15) Another method to decrease the MS surface loss of the tapered wires is to decrease the electric field at this interface by etching the silicon substrate under the junction wires. Comparing the epsilon factors for the MA and MS, this could give a large decrease in loss. Since the relative dielectric constants between silicon and air is 10, a 5 μm or greater etch would approximately appear as a 50 μm increase in the distance between the wires. Since this is approximately the distance d between the junction and the end of the wire, this will decrease the electric field. Since the surface loss of the wires only begin to be important beyond a distance d of about 5-10 μm, it is possible to undercut only the junction wires from the end to within 3-10 μm of the junction. This is useful since not freely suspending the junction will increase their fabrication reliability and stability. Standard silicon etching techniques can be used, such as Xenon-difluoride vapor, which will not degrade the aluminum wires.

(16) While this specification contains many specific details of the implementation, these should not limit the scope of any inventions or what may be claimed, but rather as descriptions to features specific to particular embodiments. Certain features described in this specification in the context of specific embodiments can also be implemented in a single embodiment. Conversely, various features that are described in context of a single embodiment can also be implemented in multiple embodiments separately or in any combination. The foregoing description of the embodiments of the invention has been presented for the purpose of illustration; it is not intended to be exhaustive or to limit the invention to the precise forms disclosed. Persons skilled in the relevant art can appreciate that many modifications and variations are possible in light of the above disclosure. Finally, the language used in the specification has been principally selected for readability and instructional purposes, and it may not have been selected to delineate or circumscribe the inventive subject matter. It is therefore intended that the scope of the invention be limited not by this detailed description, but rather by any claims that issue on an application based hereon. Accordingly, the disclosure of the embodiments of the invention is intended to be illustrative, but not limiting, of the scope of the invention, which is set forth in the following claims.