Bias Compensation Circuit and Amplifying Module

Abstract

A bias compensation circuit, coupled to an amplifying circuit, is disclosed. The bias compensation circuit comprises a transistor, comprising a first terminal, a second terminal and a control terminal; a first feedback transistor, comprising a control terminal, coupled to the first terminal of the transistor; a first terminal, coupled to the control terminal of the transistor; and a second terminal; and a second feedback transistor, comprising a control terminal, coupled to the first terminal of the transistor; a first terminal, coupled to the amplifying circuit; and a second terminal; and a first resistor, comprising a first terminal, coupled to the first terminal of the transistor; and a second terminal, configured to receive a first voltage.

Claims

1. A bias compensation circuit, coupled to an amplifying circuit, the bias compensation circuit comprising: a transistor, comprising a first terminal, a second terminal and a control terminal; a first feedback transistor, comprising: a control terminal, coupled to the first terminal of the transistor; a first terminal, coupled to the control terminal of the transistor; and a second terminal; a second feedback transistor, comprising: a control terminal, coupled to the first terminal of the transistor; a first terminal, coupled to the amplifying circuit; and a second terminal; and a first resistor, comprising: a first terminal, coupled to the first terminal of the transistor; and a second terminal, configured to receive a first voltage.

2. The bias compensation circuit of claim 1, further comprising: a second resistor, comprising: a first terminal, coupled to the second terminal of the transistor; and a second terminal, coupled to a ground.

3. The bias compensation circuit of claim 1, further comprising: a third resistor, comprising: a first terminal, coupled to the first terminal of the first feedback transistor; and a second terminal, coupled to a ground.

4. The bias compensation circuit of claim 1, further comprising: a fourth resistor, comprising: a first terminal, coupled to the first terminal of the second feedback transistor; and a second terminal, coupled to a ground.

5. The bias compensation circuit of claim 1, wherein the second terminal of the first feedback transistor and the second terminal of the second feedback transistor receive a second voltage.

6. The bias compensation circuit of claim 1, wherein the amplifying circuit comprises an amplifying transistor comprising a control terminal, and the first terminal of the second feedback transistor is coupled to the control terminal of the amplifying transistor.

7. The bias compensation circuit of claim 6, wherein the first terminal of the second feedback transistor is coupled to the control terminal of the amplifying transistor via an inductor.

8. An amplifying module, comprising: an amplifying circuit; and a bias compensation circuit, coupled to the amplifying circuit, the bias compensation circuit comprising: a transistor, comprising a first terminal, a second terminal and a control terminal; a first feedback transistor, comprising: a control terminal, coupled to the first terminal of the transistor; a first terminal, coupled to the control terminal of the transistor; and a second terminal; a second feedback transistor, comprising: a control terminal, coupled to the first terminal of the transistor; a first terminal, coupled to the amplifying circuit; and a second terminal; and a first resistor, comprising: a first terminal, coupled to the first terminal of the transistor; and a second terminal, configured to receive a first voltage.

9. The amplifying module of claim 8, further comprising: a second resistor, comprising: a first terminal, coupled to the second terminal of the transistor; and a second terminal, coupled to a ground.

10. The amplifying module of claim 8, further comprising: a third resistor, comprising: a first terminal, coupled to the first terminal of the first feedback transistor; and a second terminal, coupled to a ground.

11. The amplifying module of claim 8, further comprising: a fourth resistor, comprising: a first terminal, coupled to the first terminal of the second feedback transistor; and a second terminal, coupled to a ground.

12. The amplifying module of claim 8, wherein the second terminal of the first feedback transistor and the second terminal of the second feedback transistor receive a second voltage.

13. The amplifying module of claim 8, wherein the amplifying circuit comprises an amplifying transistor comprising a control terminal, and the first terminal of the second feedback transistor is coupled to the control terminal of the amplifying transistor.

14. The amplifying module of claim 13, wherein the first terminal of the second feedback transistor is coupled to the control terminal of the amplifying transistor via an inductor.

15. The amplifying module of claim 8, wherein the amplifying module is formed within a die.

16. The amplifying module of claim 15, wherein the die is fabricated by a pHEMT (Pseudomorphic High Electron Mobility Transistor) process.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] FIG. 1 is a schematic diagram of an amplifying module according to an embodiment of the present application.

[0010] FIG. 2 is a schematic diagram of currents of the amplifying module of under various turn on voltages.

[0011] FIG. 3 is a schematic diagram of currents of the amplifying module of under various temperatures.

DETAILED DESCRIPTION

[0012] In the present application, a control terminal of a transistor is referred to a gate of the transistor, when the transistor is an FET (Field Effect Transistor) or a (p)HEMT ((Pseudomorphic) High Electron Mobility Transistor), or referred to a base of the transistor, when the transistor is a BJT (Bipolar Junction Transistor) or an HBT (Heterojunction Bipolar Transistor). A terminal, either a first terminal or a second terminal, of a transistor is referred to a source or a drain of the transistor, when the transistor is an FET or a (p)HEMT, or referred to an emitter or collector of the transistor, when the transistor is a BJT or an HBT. For illustrative purpose, the following description takes N-type (p)HEMT or FET as an example, which is not limited thereto.

[0013] FIG. 1 is a schematic diagram of an amplifying module 10 according to an embodiment of the present application. The amplifying module 10 comprises a bias compensation circuit 12 and an amplifying circuit 14. In the embodiment illustrated in FIG. 1, the amplifying circuit 14 comprises an amplifying transistor QA.

[0014] The amplifying module 10 may be formed within a die. In an embodiment, the die may be a GaAs (Gallium Arsenide) die, which is not limited thereto. The amplifying module 10 may be fabricated by a pHEMT process, which is not limited thereto. Note that, the turn on voltage Vto and the threshold voltage V.sub.th of the transistor(s) are used interchangeably in the present application.

[0015] The bias compensation circuit 12 comprises a transistor Q, feedback transistors QF1, QF2, and resistors R1-R4. In the embodiment illustrated in FIG. 1, gates of the feedback transistors QF1, QF2 are coupled to a drain of the transistor Q. Drains of the feedback transistors QF1, QF2 receive a voltage VB. Sources of the transistor Q and the feedback transistors QF1, QF2 are coupled to a ground via the resistors R2-R4, respectively. A drain of the transistor Q and the gates of the feedback transistors QF1, QF2 are coupled to a first terminal of the resistor R1. A second terminal of the resistor R1 receives a voltage Vref. A source of the feedback transistor QF2 is coupled to a gate of the amplifying transistor QA via an inductor L1. A drain of the amplifying transistor QA is coupled to an inductor L2 to receive a voltage VD.

[0016] The bias compensation circuit 12 exploits a negative feedback mechanism, which is illustrated in the below. A current flowing through the transistor can be expressed as eq. 1, which is known in the art. When the turn on voltage Vto or the threshold voltage V.sub.th decreases/increases (due to fabrication or temperature variation), a current ID1 flowing through the transistor Q (and also a current ID2 flowing through the amplifying transistor QA) would increase/decrease, a voltage VG1 at the gate of the feedback transistors QF1, QF2 would decrease/increase due to VG1=Vref−ID1*R1. A voltage VG at the source of the feedback transistor QF1 and a voltage VG2 at the source of the feedback transistor QF2 would decrease/increase, such that the current ID1 would decrease/increase. Therefore, the (biased) current ID2 may be maintained consistent. In another perspective, the bias compensation circuit 12 utilizes a negative feedback loop formed by the transistor Q and the feedback transistors QF1, QF2 to stabilize the biased current ID2.

[00001]$\begin{array}{cc}{I}_D=\frac{{\mu }_n{C}_{ox}}{2}\frac{W}{L}{\left(V_{GS}-V_h\right)}^2& \left(\mathrm{eq}.1\right)\end{array}$

[0017] FIG. 2 represents results of the current ID2 flowing through the amplifying transistor QA under various turn on voltages Vto. The variation of the turn on voltages Vto lies between ±0.1V (volt). Different curves in FIG. 2 represent ID2 corresponding to different turn on voltages Vto. The left/right portion of FIG. 2 represent results of the current ID2 flowing through the amplifying transistor QA without/with the bias compensation circuit 12. The horizontal axis represents input power, denoted as Pin, of the amplifying transistor QA, and the vertical axis represents the current ID2. As can be seen from FIG. 2, when the input power Pin is low (e.g., less than −10 dBm), a variation of the current ID2 corresponding to the case without compensation is about 25 mA (milliampere). On the other hand, a variation of the current ID2 corresponding to the case with compensation, i.e., with the bias compensation circuit 12, is reduced to 6 mA. Therefore, the bias compensation circuit 12 is able to effectively reduce the current variation due to turn on voltage variation and stabilize the biased current ID2.

[0018] FIG. 3 represents results of the current ID2 flowing through the amplifying transistor QA under various temperatures. The variation of the temperatures lies between −30° C.-80° C. Different curves in FIG. 3 represent ID2 corresponding to different temperatures. The left/right portion of FIG. 3 represent results of the current ID2 flowing through the amplifying transistor QA without/with the bias compensation circuit 12. The horizontal axis represents input power, denoted as Pin, of the amplifying transistor QA, and the vertical axis represents the current ID2. As can be seen from FIG. 3, when the input power Pin is low (e.g., less than −10 dBm), a variation of the current ID2 corresponding to the case without compensation is about 6 mA. On the other hand, a variation of the current ID2 corresponding to the case with compensation, i.e., with the bias compensation circuit 12, is reduced to 3 mA. Therefore, the bias compensation circuit 12 is able to reduce the current variation due to temperature variation and stabilize the biased current ID2.

[0019] In a short remark, the bias compensation circuit 12 is able to reduce the current variation due to the turn on voltage variation and the temperature variation. Therefore, the bias compensation circuit 12 and the amplifying module 10 are able to provide a stable biased current, e.g., ID2.

[0020] Note that, the turn on voltage variation in unavoidable after a fabrication process. That is, fabricating a wafer (comprising a plurality of dies) may result in various turn on voltages corresponding to the plurality of dies. The bias compensation circuit 12 is suitable for a scenario that the turn on voltages of the transistors within one die are the same and the turn on voltages corresponding to different dies might be different, but not limited therein.

[0021] In summary, the bias compensation circuit of the present application utilizes the negative feedback loop to stabilize the biased current, such that the bias compensation circuit and the amplifying module are able to provide the stable biased current.

[0022] Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.