INPUT CIRCUIT

Abstract

An input circuit including an input transistor including a drain input with an input voltage, an input current generation circuit configured to generate an input current to flow in the input transistor, a resistor connected between a source of the input transistor and a first power source, and an output transistor including a gate connected to a connection point between the source of the input transistor and the resistor.

Claims

1. An input circuit comprising: an input transistor including a drain input with an input voltage; an input current generation circuit configured to generate an input current to flow in the input transistor; a first resistor connected between a source of the input transistor and a first power source; and an output transistor including a gate connected to a connection point between the source of the input transistor and the first resistor.

2. The input circuit of claim 1, wherein: the input current generation circuit is configured by a current mirror circuit including a first transistor having a gate commonly connected to a gate of the input transistor, and a current source connected to a drain of the first transistor.

3. The input circuit of claim 1, further comprising a current mirror circuit configured by a second transistor having a drain commonly connected to a drain of the output transistor and a third transistor having a gate commonly connected to a gate of the second transistor, and a level shift circuit including a second resistor connected between a drain of the third transistor and a second power source having a lower voltage value than a voltage value of the first power source.

4. The input circuit of claim 2, further comprising a current mirror circuit configured by a second transistor having a drain commonly connected to a drain of the output transistor and a third transistor having a gate commonly connected to a gate of the second transistor, and a level shift circuit including a second resistor connected between a drain of the third transistor and a second power source having a lower voltage value than a voltage value of the first power source.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0018] FIG. 1 is a circuit diagram illustrating an example of a configuration of an input circuit according to an exemplary embodiment of the present disclosure;

[0019] FIG. 2 is a circuit diagram illustrating currents in respective sections of an input circuit according to an exemplary embodiment of the present disclosure; and

[0020] FIG. 3 is a circuit diagram illustrating a configuration of an input circuit according to related art.

DETAILED DESCRIPTION

[0021] Detailed explanation follows regarding an input circuit 10 according to an exemplary embodiment of the present disclosure, with reference to FIG. 1 and FIG. 2. FIG. 1 is a circuit diagram of the input circuit 10, and FIG. 2 illustrates currents in respective sections of the input circuit 10. The input circuit 10 is for example a circuit for determining a logic level (H, L) of input voltage to a semiconductor integrated circuit.

[0022] As illustrated in FIG. 1, the input circuit 10 according to the present exemplary embodiment is configured including N-type MOS transistors QN1, QN2, P-type MOS transistors QP1, QP2, QP3, a current source is, an inverter IN1, and resistors R1, R2. A high voltage power source VBB having a comparatively high voltage value is connected to a terminal 1, and a low voltage power source VCC having a comparatively low voltage value is connected to a terminal 2. An input voltage Vin is input to a terminal 3, and an output voltage V out is output from a terminal 4.

[0023] The input voltage Vin according to the present exemplary embodiment has a full swing between ground and the voltage value of the high voltage power source VBB, namely between L=0V and H=VBB. Note that VBB is the voltage value of the high voltage power source. The P-type MOS transistors QP2, QP3 and the resistor R1 are connected to the high voltage power source VBB, and the resistor R2 and the inverter IN1 are connected to the low voltage power source VCC. Logical switching of the input voltage Vin is schematically illustrated by a switch SW1. Note that the P-type MOS transistor QP1 is an example of an input transistor and the P-type MOS transistor QP3 is an example of an output transistor according to the present disclosure.

[0024] The input circuit 10 is configured such that the input voltage Vin is input to a drain of the P-type MOS transistor QP1. The P-type MOS transistors QP1 and QP2 configure a current mirror, and so when I1 is the current of the current source Is as illustrated in FIG. 2, the current I1 also flows in the P-type MOS transistor QP1 in response to the input voltage Vin. Namely, when the input voltage Vin is H, Vin=VBB, and so the current I1 does not flow. However, when the input voltage Vin is L, Vin=0V as the drain of the P-type MOS transistor QP1 is connected to ground, and so the current I1 flows.

[0025] Thus, when the input voltage Vin is L, a voltage expressed by I1.Math.R1 is applied between gate and source of the P-type MOS transistor QP3. Taking Vt as a threshold of a gate-source voltage of the P-type MOS transistor QP3, the present exemplary embodiment is set such that I1.Math.R1>Vt. Thus, when the input voltage Vin is L, a current I2 flows in the P-type MOS transistor QP3 as illustrated in FIG. 2. Note that although a mirror ratio of the current mirror circuit configured by the P-type MOS transistors QP1 and QP2 is 1:1 in the present exemplary embodiment, there is no limitation thereto, and the minor ratio may be changed according to the design conditions and so on of the input circuit 10. Note that the current mirror circuit configured by the P-type MOS transistors QP1, QP2 and the current source Is is an example of an input current generation circuit according to the present disclosure.

[0026] The N-type MOS transistors QN1 and QN2 also configure a current mirror. Thus, when the current I2 flows in the N-type MOS transistor QN1, a current corresponding to I2 (for example, I2 for a mirror ratio of 1:1) flows through the resistor R2, and the output voltage Vout is generated and output from the terminal 4 through the inverter IN1. Note that the current mirror circuit configured by the N-type MOS transistors QN1, QN2 and the resistor R2 configure an example of a level shift circuit according to the present disclosure.

[0027] Note that as previously described, for input circuits it is difficult to achieve both an easing of conventional withstand voltage-related constraints and an expansion of an input dynamic range. In order to address this issue, in the input circuit 10 according to the present exemplary embodiment, the input voltage Vin is input to the drain of the P-type MOS transistor QP1 configuring an input transistor. In such cases, the withstand voltage of the P-type MOS transistor QP1 is restricted by a drain-source withstand voltage <Vds> of the P-type MOS transistor QP1. However, this drain-source withstand voltage <Vds> is generally higher than a gate-source withstand voltage <Vgs>. For example, in contrast to a gate-source withstand voltage <Vgs> of approximately 5V, the drain-source withstand voltage <Vds> exhibits a value of approximately 40V. This accordingly enables both an easing of the withstand voltage-related constraints of the P-type MOS transistor QP3 configuring the input transistor, and an expansion in the input dynamic range by raising the voltage value of the high voltage power source VBB, to be accommodated.

[0028] Furthermore, the input circuit 10 according to the present exemplary embodiment is configured such that an electric potential of the gate of the P-type MOS transistor QP3 configuring an output transistor is fixed, irrespective of the voltage value of the high voltage power source VBB and irrespective of the input voltage Vin. Namely, as described above, the electric potential of the gate of the P-type MOS transistor QP3 in the input circuit 10 is fixed at (VBB−R1.Math.I1), and so the gate-source voltage Vgs of the P-type MOS transistor QP3 is a voltage determined by (R1.Math.I1). The present exemplary embodiment is configured such that the value of the current I1 is a constant value, and so setting such that I1.Math.R1>Vt enables Vin=L to always be ON without the gate-source withstand voltage <Vgs> of the P-type MOS transistor QP3 ever being exceeded.

[0029] As described in detail above, the input circuit according to the present exemplary embodiment provides an input circuit enabling both an easing of withstand voltage-related constraints and an expansion in the input dynamic range to be achieved.