QUAD SWITCHED MULTIBIT DIGITAL TO ANALOG CONVERTER AND CONTINUOUS TIME SIGMA-DELTA MODULATOR

Abstract

A quad signal generator circuit generates four 2.sup.N−1 bit control signals in response to a sampling clock and a 2.sup.N−1 bit thermometer coded signal. A digital-to-analog converter (DAC) circuit has 2.sup.N−1 unit resistor elements, with each unit resistor element including four switching circuits controlled by corresponding bits of the four 2.sup.N−1 bit control signals. Outputs of the 2.sup.N−1 unit resistor elements are summed to generate an analog output signal. The quad signal generator circuit controls generation of the four 2.sup.N−1 bit control signals such that all logic states of bits of the four 2.sup.N−1 bit control signals remain constant for at least a duration of one cycle of the sampling clock. The analog output signal may be a feedback signal in a sigma-delta analog-to-digital converter (ADC) circuit that includes a multi-bit quantization circuit operating to quantize a filtered loop signal to generate the 2.sup.N−1 bit thermometer coded signal.

Claims

1. A circuit, comprising: a digital-to-analog converter (DAC) circuit having 2.sup.N−1 unit resistive DAC elements, wherein each unit resistive DAC element includes four switching circuits controlled by corresponding bits of four 2.sup.N−1 bit control signals, wherein outputs of the 2.sup.N−1 unit resistive DAC elements are summed to generate an analog output signal; and a quad signal generator circuit configured to generate the four 2.sup.N−1 bit control signals in response to a sampling clock and a 2.sup.N−1 bit thermometer coded input signal, wherein the quad signal generator circuit controls generation of the four 2.sup.N−1 bit control signals such that all logic states of bits of the four 2.sup.N−1 bit control signals remain constant for at least a duration of one cycle of the sampling clock.

2. The circuit of claim 1, wherein the quad signal generator circuit controls generation of the four 2.sup.N−1 bit control signals such that all changes in logic state of bits of the four 2.sup.N−1 bit control signals occur in response to a same leading or trailing edge of the cycles of the sampling clock.

3. The circuit of claim 1, wherein the quad signal generator circuit includes a frequency divider circuit configured to divide the sampling clock and generate a divided sampling clock, and wherein the quad signal generator circuit controls generation of the four 2.sup.N−1 bit control signals such that all changes in logic states of bits of the four 2.sup.N−1 bit control signals occur in response to edges of the divided sampling clock.

4. The circuit of claim 1, wherein four switching circuits of each unit resistive DAC element comprise: a first switching circuit configured to switch a first common node between a first and second reference voltages in response to a first control signal of the four 2.sup.N−1 bit control signals and a logical inversion of a second control signal of the four 2.sup.N−1 bit control signals; a second switching circuit configured to switch the first common node between the first and second reference voltages in response to a third control signal of the four 2.sup.N−1 bit control signals and a logical inversion of a fourth control signal of the four 2.sup.N−1 bit control signals; a third switching circuit configured to switch a second common node between the first and second reference voltages in response to the second control signal of the four 2.sup.N−1 bit control signals and a logical inversion of the first control signal of the four 2.sup.N−1 bit control signals; and a fourth switching circuit configured to switch the second common node between the first and second reference voltages in response to the fourth control signal of the four 2.sup.N−1 bit control signals and a logical inversion of the third control signal of the four 2.sup.N−1 bit control signals.

5. The circuit of claim 4, further comprising: a first resistive circuit coupled between the first common node and a first summing output node for providing a first component of the analog output signal; and a second resistive circuit coupled between the second common node and a second summing output node for providing a second component of the analog output signal.

6. The circuit of claim 5, wherein the first and second components are differential currents of the analog output signal.

7. The circuit of claim 4, wherein the quad signal generator circuit comprises: a frequency divider circuit configured to divide the sampling clock and generate a divided sampling clock; a first logic circuit configured to logically combine each bit of the 2.sup.N−1 bit thermometer coded input signal with the divided sampling clock to generate a corresponding bit of the second control signal; a second logic circuit configured to logically combine each bit of the 2.sup.N−1 bit thermometer coded input signal with a logical inverse of the divided sampling clock to generate a corresponding bit of the fourth control signal; a third logic circuit configured to logically combine each bit of a logical inverse of the 2.sup.N−1 bit thermometer coded input signal with the divided sampling clock to generate a corresponding bit of the first control signal; and a fourth logic circuit configured to logically combine each bit of the logical inverse of the 2.sup.N−1 bit thermometer coded input signal with the logical inverse of the divided sampling clock to generate a corresponding bit of the third control signal.

8. The circuit of claim 7, wherein the quad signal generator circuit further comprises a latching circuit for each of the four 2.sup.N−1 bit control signals that is configured to latch the bits of the four 2.sup.N−1 bit control signals in response to a delayed sampling clock generated by applying a delay to the sampling clock.

9. The circuit of claim 1, wherein the 2.sup.N−1 bit thermometer coded input signal is generated with data weighted averaging (DWA).

10. The circuit of claim 9, further including a DWA circuit configured to apply data weighted averaging to a received 2.sup.N−1 bit thermometer coded signal in order to generate the 2.sup.N−1 bit thermometer coded input signal.

11. The circuit of claim 10, further including a multi-bit quantization circuit configured to generate the 2.sup.N−1 bit thermometer coded signal.

12. A sigma-delta analog-to-digital converter (ADC) circuit, comprising: a loop filter circuit configured to generate a difference signal from a difference of an analog input signal and an analog feedback signal and filter the difference signal to generate a change signal; a multi-bit quantization circuit configured to quantize the change signal and generate a 2.sup.N−1 bit thermometer coded signal; a quad signal generator circuit configured to generate four 2.sup.N−1 bit control signals in response to a sampling clock and the 2.sup.N−1 bit thermometer coded signal; a digital-to-analog converter (DAC) circuit having 2.sup.N−1 unit resistive DAC elements, wherein each unit resistive DAC element includes four switching circuits controlled by corresponding bits of the four 2.sup.N−1 bit control signals; wherein outputs of the 2.sup.N−1 unit resistive DAC elements are summed to generate the analog feedback signal; and wherein the quad signal generator circuit controls generation of the four 2.sup.N−1 bit control signals such that all logic states of bits of the four 2.sup.N−1 bit control signals remain constant for at least a duration of one cycle of the sampling clock.

13. The circuit of claim 12, wherein the 2.sup.N−1 bit thermometer coded signal is generated with data weighted averaging (DWA).

14. The circuit of claim 13, further including a DWA circuit configured to apply data weighted averaging to a 2.sup.N−1 bit thermometer coded output signal from the multi-bit quantization circuit in order to generate the 2.sup.N−1 bit thermometer coded signal.

15. The circuit of claim 12, wherein the quad signal generator circuit controls generation of the four 2.sup.N−1 bit control signals such that all changes in logic state of bits of the four 2.sup.N−1 bit control signals occur in response to a same leading or trailing edge of the cycles of the sampling clock.

16. The circuit of claim 12, wherein the quad signal generator circuit includes a frequency divider circuit configured to divide the sampling clock and generate a divided sampling clock, and wherein the quad signal generator circuit controls generation of the four 2.sup.N−1 bit control signals such that all changes in logic states of bits of the four 2.sup.N−1 bit control signals occur in response to edges of the divided sampling clock.

17. The circuit of claim 12, wherein four switching circuits of each unit resistive DAC element comprise: a first switching circuit configured to switch a first common node between a first and second reference voltages in response to a first control signal of the four 2.sup.N−1 bit control signals and a logical inversion of a second control signal of the four 2.sup.N−1 bit control signals; a second switching circuit configured to switch the first common node between the first and second reference voltages in response to a third control signal of the four 2.sup.N−1 bit control signals and a logical inversion of a fourth control signal of the four 2.sup.N−1 bit control signals; a third switching circuit configured to switch a second common node between the first and second reference voltages in response to the second control signal of the four 2.sup.N−1 bit control signals and a logical inversion of the first control signal of the four 2.sup.N−1 bit control signals; and a fourth switching circuit configured to switch the second common node between the first and second reference voltages in response to the fourth control signal of the four 2.sup.N−1 bit control signals and a logical inversion of the third control signal of the four 2.sup.N−1 bit control signals.

18. The circuit of claim 17, further comprising: a first resistive circuit coupled between the first common node and a first summing output node for providing a first component of the analog output signal; and a second resistive circuit coupled between the second common node and a second summing output node for providing a second component of the analog output signal.

19. The circuit of claim 18, wherein the first and second components are differential currents of the analog output signal.

20. The circuit of claim 17, wherein the quad signal generator circuit comprises: a frequency divider circuit configured to divide the sampling clock and generate a divided sampling clock; a first logic circuit configured to logically combine each bit of the 2.sup.N−1 bit thermometer coded signal with the divided sampling clock to generate a corresponding bit of the second control signal; a second logic circuit configured to logically combine each bit of the 2.sup.N−1 bit thermometer coded signal with a logical inverse of the divided sampling clock to generate a corresponding bit of the fourth control signal; a third logic circuit configured to logically combine each bit of a logical inverse of the 2.sup.N−1 bit thermometer coded signal with the divided sampling clock to generate a corresponding bit of the first control signal; and a fourth logic circuit configured to logically combine each bit of the logical inverse of the 2.sup.N−1 bit thermometer coded signal with the logical inverse of the divided sampling clock to generate a corresponding bit of the third control signal.

21. The circuit of claim 20, wherein the quad signal generator circuit further comprises a latching circuit for each of the four 2.sup.N−1 bit control signals that is configured to latch the bits of the four 2.sup.N−1 bit control signals in response to a delayed sampling clock generated by applying a delay to the sampling clock.

22. A sigma-delta analog-to-digital converter (ADC) circuit, comprising: a loop filter configured to receive an analog input signal and a first analog feedback signal and generate an integrated signal; a multi-bit quantization circuit configured to quantize the integrated signal and generate a 2.sup.N−1 bit thermometer coded signal; a quad signal generator circuit configured to generate four 2.sup.N−1 bit control signals in response to a sampling clock and the 2.sup.N−1 bit thermometer coded signal; a first digital-to-analog converter (DAC) circuit having 2.sup.N−1 unit resistive DAC elements, wherein each unit resistive DAC element includes four switching circuits controlled by corresponding bits of the four 2.sup.N−1 bit control signals; wherein outputs of the 2.sup.N−1 unit resistive DAC elements of the first DAC circuit are summed to generate the first analog feedback signal; and wherein the quad signal generator circuit controls generation of the four 2.sup.N−1 bit control signals such that all logic states of bits of the four 2.sup.N−1 bit control signals remain constant for at least a duration of one cycle of the sampling clock.

23. The circuit of claim 22, wherein the loop filter is at least third order and further receives a second analog feedback signal to generate the integrated signal, and further comprising: a second digital-to-analog converter (DAC) circuit having 2.sup.N−1 unit resistive DAC elements, wherein each unit resistive DAC element includes four switching circuits controlled by corresponding bits of the four 2.sup.N−1 bit control signals; and wherein outputs of the 2.sup.N−1 unit resistive DAC elements of the second DAC circuit are summed to generate the second analog feedback signal.

24. The circuit of claim 22, further including a data weighted averaging (DWA) circuit configured to apply data weighted averaging to a 2.sup.N−1 bit thermometer coded output signal from the multi-bit quantization circuit in order to generate the 2.sup.N−1 bit thermometer coded signal.

25. The circuit of claim 22, wherein four switching circuits of each unit resistive DAC element comprise: a first switching circuit configured to switch a first common node between a first and second reference voltages in response to a first control signal of the four 2.sup.N−1 bit control signals and a logical inversion of a second control signal of the four 2.sup.N−1 bit control signals; a second switching circuit configured to switch the first common node between the first and second reference voltages in response to a third control signal of the four 2.sup.N−1 bit control signals and a logical inversion of a fourth control signal of the four 2.sup.N−1 bit control signals; a third switching circuit configured to switch a second common node between the first and second reference voltages in response to the second control signal of the four 2.sup.N−1 bit control signals and a logical inversion of the first control signal of the four 2.sup.N−1 bit control signals; and a fourth switching circuit configured to switch the second common node between the first and second reference voltages in response to the fourth control signal of the four 2.sup.N−1 bit control signals and a logical inversion of the third control signal of the four 2.sup.N−1 bit control signals.

26. The circuit of claim 25, further comprising: a first resistive circuit coupled between the first common node and a first summing output node for providing a first component of the analog output signal; and a second resistive circuit coupled between the second common node and a second summing output node for providing a second component of the analog output signal.

27. The circuit of claim 26, wherein the first and second components are differential currents of the analog output signal.

28. The circuit of claim 25, wherein the quad signal generator circuit comprises: a frequency divider circuit configured to divide the sampling clock and generate a divided sampling clock; a first logic circuit configured to logically combine each bit of the 2.sup.N−1 bit thermometer coded signal with the divided sampling clock to generate a corresponding bit of the second control signal; a second logic circuit configured to logically combine each bit of the 2.sup.N−1 bit thermometer coded signal with a logical inverse of the divided sampling clock to generate a corresponding bit of the fourth control signal; a third logic circuit configured to logically combine each bit of a logical inverse of the 2.sup.N−1 bit thermometer coded signal with the divided sampling clock to generate a corresponding bit of the first control signal; and a fourth logic circuit configured to logically combine each bit of the logical inverse of the 2.sup.N−1 bit thermometer coded signal with the logical inverse of the divided sampling clock to generate a corresponding bit of the third control signal.

29. The circuit of claim 28, wherein the quad signal generator circuit further comprises a latching circuit for each of the four 2.sup.N−1 bit control signals that is configured to latch the bits of the four 2.sup.N−1 bit control signals in response to a delayed sampling clock generated by applying a delay to the sampling clock.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0015] For a better understanding of the embodiments, reference will now be made by way of example only to the accompanying figures in which:

[0016] FIG. 1 is a time domain block diagram of a conventional sigma-delta analog-to-digital converter circuit with single bit quantization;

[0017] FIG. 2 is a time domain block diagram of a conventional sigma-delta analog-to-digital converter circuit with multi bit quantization;

[0018] FIG. 3 is a time domain block diagram of a conventional sigma-delta analog-to-digital converter circuit with multi bit quantization and data weighted averaging;

[0019] FIG. 4A is a time domain block diagram of a continuous time sigma-delta analog-to-digital converter circuit with a multi bit quantizer, data weighted averaging and a quad signal generator controlling a quad switched digital-to-analog converter;

[0020] FIG. 4B illustrates in more detail a differential signal implementation of the circuit of FIG. 4A for a third-order continuous time sigma delta analog-to-digital converter;

[0021] FIG. 5 is a block diagram of a digital-to-analog converter (DAC) circuit as used in the circuit of FIG. 4B;

[0022] FIG. 6 is a block diagram of a the quad signal generator circuit as used in the circuit of FIG. 4B; and

[0023] FIG. 7 shows a timing diagram for operation of the quad signal generator circuit.

DETAILED DESCRIPTION

[0024] Reference is now made to FIG. 4A which shows a time domain block diagram of a continuous time sigma-delta analog-to-digital converter (modulator) circuit 100 with a multi bit quantizer, data weighted averaging and a quad signal generator controlling a quad switched digital-to-analog converter. The circuit 100 includes a continuous time sigma-delta modulator circuit 12 (illustrated here as a first-order circuit, but it being understood that the loop filter of the modulator can of any order suited to the circuit application requirements; see, for example, FIG. 4B for a third-order continuous time sigma delta modulator circuit) having an input configured to receive an analog input signal A and an output configured to generate a digital output signal B comprised of a stream of multi-bit thermometer coded data words. The thermometer coded values in the pulse stream of the signal B at a sampling rate fs are processed in a decimator circuit 14 (comprising a low pass filter and down sampler) to generate an equivalent digital signal C of the input signal A with a required resolution and a required output word rate fd, where fd<<fs, set by a decimation factor.

[0025] The first order sigma-delta modulator circuit 12 comprises a difference amplifier 20 (or summation circuit) having a first (non-inverting) input that receives the analog input signal A and a second (inverting) input that receives an analog feedback signal D. The difference amplifier 20 outputs an analog difference signal vdif in response to a difference between the analog input signal A and the analog feedback signal D (i.e., vdif(t)=A(t)−D(t)). The analog difference signal vdif is integrated by an integrator circuit 22 (of the loop filter, here of first order type, without limitation) to generate a change signal vc having a slope and magnitude that is dependent on the sign and magnitude of the analog difference signal vdif. An N-bit quantization circuit 24′ samples the change signal vc in response to a clock CLK at the sampling rate fs and generates the digital output signal B as a 2.sup.N−1 bit thermometer coded output word for each sample. The use of multi-bit quantization presents a number of advantages including: permitting operation of the modulator to achieve a given resolution using a lower sampling rate fs; or permitting operation of the modulator to achieve a higher resolution for a given sampling rate fs. A circuit 102 that implements a data weighted averaging (DWA) algorithm receives the 2.sup.N−1 bit thermometer coded output word and outputs a 2.sup.N−1 bit output DWA word providing for first order dynamic element matching (DEM). A quad signal generator circuit 104 receives the 2.sup.N−1 bit output DWA word and the sampling clock CLK and generates four 2.sup.N−1 bit control words DP1, DP2, DM1 and DM2 whose data values change at the same rate as the rate of the sampling clock CLK. A DAC circuit 126 includes 2.sup.N−1 unit resistive DAC elements that are respectively driven by corresponding bits of the 2.sup.N−1 bits of the control words DP1, DP2, DM1 and DM2 to generate currents which are summed at the output of the DAC circuit to produce an analog signal for the analog feedback signal D. The decimator circuit 14 low pass filters and down samples the 2.sup.N−1 bit code words in the stream of the digital output signal B to generate a digital signal C comprised of the stream of multi-bit (M-bit, the required resolution, where M>>N) digital words at an output word rate fd set by a decimation factor.

[0026] The implementation illustrated in FIG. 4A is a simplification. In a preferred implementation, the circuit is fully differential and includes a higher order sigma-delta modulator. FIG. 4B shows a circuit diagram for a differential signal implementation of the circuit of FIG. 4A using a third-order modulator. The loop filter is formed by operational amplifiers OP1, OP2 and OP3 to provide the difference amplifier 20 and integrator circuit 22 for the third-order implementation of the sigma-delta modulator circuit 12 in a configuration with cascaded integrators having feed forward as well as feedback (CIFF-FB). Because of the choice for a third-order implementation with CIFF-FB, two DACs 126 are needed. Each DAC 126 receives the 2.sup.N−1 bits of the control words DP1, DP2, DM1 and DM2 output from the quad signal generator circuit 104 and provides the differential output signal D (Outm and Outp). The operational amplifier OP1 receives the signals A (Inm and Inp) and D1 (Outm1 and Outp1 from one of the DACs) as differential signals. The operational amplifier OP3 receives the signal D2 (Outm2 and Outp2 from the other of the DACs) as a differential signal in combination with the differential signal output from the operational amplifier OP2 and the differential input signal A (Inp and Inm). The quantization circuit 24′ receives the signal vc output from the integrator circuit 22 as a differential signal.

[0027] Reference is now made to FIG. 5 which shows a block diagram of the DAC circuit 126. The DAC circuit 126 includes 2.sup.N−1 unit resistive DAC elements (UE) 110(1)-110(2.sup.N−1) that are selectively actuated in response to the control word output of the quad signal generator circuit 104 to generate the analog feedback signal. Each unit resistive DAC element 110 receives the corresponding bit from each of the control words DP1<2.sup.N−1:1>, DP2<2.sup.N−1:1>, DM1<2.sup.N−1:1> and DM2<2.sup.N−1:1>. For example, unit resistive DAC element 110(1) receives the first bits DP1(1), DP2(1), DM1(1) and DM2(1), unit resistive DAC element 110(2) receives the second bits DP1(2), DP2(2), DM1(2) and DM2(2), . . . , and the unit resistive DAC element 110(2.sup.N−1) receives the 2.sup.N−1 th bits DP1(2.sup.N−1), DP2(2.sup.N−1), DM1(2.sup.N−1) and DM2(2.sup.N−1). The quad signal generator circuit 104 generates the bits of the control words DP1<2.sup.N−1:1>, DP2<2.sup.N−1:1>, DM1<2.sup.N−1:1> and DM2<2.sup.N−1:1> from the 2.sup.N−1 bit output DWA word in a manner to be described in detail herein. The bits of the control words DP1<2.sup.N−1:1>, DP2<2.sup.N−1:1>, DM1<2.sup.N−1:1> and DM2<2.sup.N−1:1> change at the same rate as the rate of the sampling clock CLK.

[0028] For each given one X, where X is from 1 to 2.sup.N−1, the unit resistive DAC element 110(X) includes a first CMOS inverter (switching) circuit formed by a pMOS transistor 142 and an nMOS transistor 144 whose source-drain paths are coupled in series between a first reference voltage Vrefp and a second reference voltage Vrefm. The switching circuit switches between the first and second reference voltages in response to certain ones of the control words where: the gate of the pMOS transistor 142 receives the bit DP1B(X) which is the logical inversion (generated by inverter 146) of the bit DP1(X) of the control word DP1<2.sup.N−1:1>. The gate of the nMOS transistor 144 receives the bit DM1(X) of the control word DM1<2.sup.N−1:1>. The unit resistive DAC element 110(X) also includes a second CMOS inverter (switching) circuit formed by a pMOS transistor 152 and an nMOS transistor 154 whose source-drain paths are coupled in series between the first reference voltage Vrefp and the second reference voltage Vrefm. The switching circuit switches between the first and second reference voltages in response to certain ones of the control words where: the gate of the pMOS transistor 152 receives the bit DP2B(X) (generated by inverter 156) which is the logical inversion of the bit DP2(X) of the control word DP2<2.sup.N−1:1>. The gate of the nMOS transistor 124 receives the bit DM2(X) of the control word DM2<2.sup.N−1:1>. The common drain terminals of the transistors 142 and 144 are connected to the common drain terminals of transistors 152 and 154 at node 160. A resistor 162 is coupled between the node 160 and a first output node 164 of the unit resistive DAC element 110(X) to produce an output current signal.

[0029] The unit resistive DAC element 110(X) further includes a third CMOS inverter (switching) circuit formed by a pMOS transistor 172 and an nMOS transistor 174 whose source-drain paths are coupled in series between the first reference voltage Vrefp and the second reference voltage Vrefm. The switching circuit switches between the first and second reference voltages in response to certain ones of the control words where: the gate of the pMOS transistor 172 receives the bit DM1B(X) (generated by inverter 176) which is the logical inversion of the bit DM1(X) of the control word DM1<2.sup.N−1:1>. The gate of the nMOS transistor 174 receives the bit DP1(X) of the control word DP1<2.sup.N−1:1>. The unit resistive DAC element 110(X) also includes a fourth CMOS inverter (switching) circuit formed by a pMOS transistor 182 and an nMOS transistor 184 whose source-drain paths are coupled in series between the first reference voltage Vrefp and the second reference voltage Vrefm. The switching circuit switches between the first and second reference voltages in response to certain ones of the control words where: the gate of the pMOS transistor 182 receives the bit DM2B(X) (generated by inverter 186) which is the logical inversion of the bit DM2(X) of the control word DM2<2.sup.N−1:1>. The gate of the nMOS transistor 184 receives the bit DP2(X) of the control word DP2<2.sup.N−1:1>. The common drain terminals of the transistors 172 and 174 are connected to the common drain terminals of transistors 182 and 184 at node 190. A resistor 192 is coupled between the node 190 and a second output node 194 of the Unit resistive DAC element 110(X) to produce a current output signal.

[0030] The first reference voltage Vrefp and the second reference voltage Vrefm are selected by the circuit designer based on the design voltages for the circuit. In an embodiment, for example, the first reference voltage Vrefp=1.1V and the second reference voltage Vrefm=0V. Any suitable regulator voltage generator circuit can be used to provide first reference voltage Vrefp and the second reference voltage Vrefm.

[0031] The current output signals generated at the first output nodes 164 of the unit resistive DAC elements 110(1)-110(2.sup.N−1) are connected together at a summing node to generate a net output DAC current providing a first component Outp of the analog feedback signal D. The current output signals at the second output nodes 194 of the unit resistive DAC elements 110(1)-110(2.sup.N−1) are connected together at a summing node to generate a net output DAC current providing a second component Outm of the analog feedback signal D. In this implementation, the analog feedback signal D is a differential current signal formed by the Outp and Outm components. The Outp and Outm components are input to the amplifier OP input terminals.

[0032] It will be noted that although the circuit 10 is preferably implemented in differential form, it is possible to implement the circuit in single ended form.

[0033] Reference is now made to FIG. 6 which shows a block diagram of the quad signal generator circuit 104. The sampling clock CLK input to the quad signal generator circuit 104 is frequency divided by 2 using a frequency divider circuit 200 to output a divided by 2 clock (DCLK) and a logical inverse (i.e., 180° out of phase) divided by 2 clock (DCLKB). The 2.sup.N−1 bit output DWA word (DWAout<2.sup.N−1:1>) received from the DWA circuit 102 is logically inverted by circuit 202 to generate an inverted 2.sup.N−1 bit output DWA word (DWAoutB<2.sup.N−1:1>). A logic delay circuit 204 receives the sampling clock CLK and outputs a phase delayed sampling clock DlyCLK. The quad control words DP1<2.sup.N−1:1>, DP2<2.sup.N−1:1>, DM1<2.sup.N−1:1> and DM2<2.sup.N−1:1> are generated by logically combining the DWAout<2.sup.N−1:1> word, DWAoutB<2.sup.N−1:1> word, DCLK clock and DCLKB clock as follows. The control word DP1<2.sup.N−1:1> is generated by logically ANDing 210 the DWAout<2.sup.N−1:1> word with the DCLK clock, and then latching the result of the logical ANDing operation in a latch circuit 212 in response to the DlyCLK clock. The control word DP2<2.sup.N−1:1> is generated by logically ANDing 214 the DWAout<2.sup.N−1:1> word with the DCLKB clock, and then latching the result of the logical ANDing operation in a latch circuit 216 in response to the DlyCLK clock. The control word DM1<2.sup.N−1:1> is generated by logically ANDing 218 the DWAoutB<2.sup.N−1:1> word with the DCLK clock, and then latching the result of the logical ANDing operation in a latch circuit 220 in response to the DlyCLK clock. The control word DM2<2.sup.N−1:1> is generated by logically ANDing 222 the DWAoutB<2.sup.N−1:1> word with the DCLKB clock, and then latching the result of the logical ANDing operation in a latch circuit 224 in response to the DlyCLK clock.

[0034] FIG. 7 shows a timing diagram for operation of the quad signal generator circuit 104. It will be noted that changes in logic state of the control signals DP1(X), DP2(X), DM1(X) and DM2(X) occur in response to the same edge (in this case, the trailing edge) of the sampling clock CLK. Thus, changes in the logic state of the control signals DP1(X), DP2(X), DM1(X) and DM2(X) occur at a same rate as the rate of the sampling clock CLK. In other words, the logic state of the control signals DP1(X), DP2(X), DM1(X) and DM2(X) remains constant for a duration of time that is at least as long as the duration of one cycle of the sampling clock CLK. This operation occurs because the DCLK clock and DCLKB clock, at one-half the rate of the sampling clock CLK, are controlling the logical combination function through the ANDing operation which generates the control signals DP1(X), DP2(X), DM1(X) and DM2(X) from the DWAout(X) and DWAoutB(X) bits.

[0035] Although disclosed herein in the context of a continuous time delta sigma modulator, it will be understood that the disclosed circuit and operation herein is also applicable to discrete time modulators.

[0036] While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are considered illustrative or exemplary and not restrictive; the invention is not limited to the disclosed embodiments. Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims.