Constant Voltage Generation Circuit

Abstract

A constant voltage generation circuit is provided. The constant voltage generation circuit includes a differential pair including a first transistor having a gate input with a reference voltage and a second transistor having a gate input with a signal corresponding to an output voltage, an output transistor that has a gate connected to a connection point between a drain of one transistor out of the differential pair and a load of the one transistor and that is configured to output the output voltage, and a diode connected between the gate of the output transistor and a power source.

Claims

1. A constant voltage generation circuit comprising: a differential pair including a first transistor having a gate input with a reference voltage and a second transistor having a gate input with a signal corresponding to an output voltage; an output transistor having a gate connected to a connection point between a drain of one transistor of the differential pair and a load of the one transistor, and configured to output the output voltage; and a diode connected between the gate of the output transistor and a power source.

2. The constant voltage generation circuit of claim 1, further comprising: a third transistor having a drain with common connection to a drain of the first transistor and configuring the load of the one transistor; and a fourth transistor having a gate and a drain connected together with the drain also having a common connection to a drain of the second transistor, wherein the gate of the output transistor is connected to a connection point between the first transistor and the third transistor.

3. The constant voltage generation circuit of claim 1, further comprising a plurality of diodes, wherein a number of the plurality of diodes is set within a range in which a total forward voltage of the plurality of diodes is greater than a potential difference between the power source and the gate of the output transistor.

4. The constant voltage generation circuit of claim 2, further comprising a plurality of diodes, wherein a number of the plurality of diodes is set within a range in which a total forward voltage of the plurality of diodes is greater than a potential difference between the power source and the gate of the output transistor.

Description

BRIEF DESCRIPTION OF DRAWINGS

[0019] FIG. 1A is a circuit diagram illustrating an example of configuration of a constant voltage generation circuit according to an exemplary embodiment of the present disclosure;

[0020] FIG. 1B is a timing chart illustrating operation waveforms of respective elements of a constant voltage generation circuit according to an exemplary embodiment of the present disclosure;

[0021] FIG. 2A is a circuit diagram illustrating an example of configuration of a constant voltage generation circuit according to prior art; and

[0022] FIG. 2B is a timing chart illustrating operation waveforms of respective elements of a constant voltage generation circuit according to prior art.

DETAILED DESCRIPTION

[0023] Detailed explanation follows regarding a constant voltage generation circuit according to an exemplary embodiment of the present disclosure, with reference to FIG. 1.

[0024] As illustrated in FIG. 1A, a constant voltage generation circuit 10 according to the present exemplary embodiment is configured including N-type MOS transistors QN1, QN2, P-type MOS transistors QP1, QP2, QP3, resistors R1, R2, a current source 11, and diodes D1, D2. The constant voltage generation circuit 10 is a regulator circuit that for example steps down a 12V power source voltage Vp to 3.3V to be output as an output voltage Vout.

[0025] An example of configuration of a constant voltage generation circuit (regulator circuit) is a circuit combining a reference voltage generation circuit that generates a high precision reference voltage Vref, and an amplifier circuit that amplifies the reference voltage Vref to the target output voltage Vout to be supplied to a later stage circuit. In particular, a constant voltage needs to be maintained while supplying sufficient current to the later stage circuit at an output stage of the amplifier circuit, and so a single stage P-type MOS transistor with a large transistor size and open drain output is often employed therefor.

[0026] The constant voltage generation circuit 10 according to the present exemplary embodiment adopts the above configuration. FIG. 1A illustrates the amplifier circuit and the output stage of the above configuration. The reference voltage generation circuit is not directly relevant to the present disclosure and so illustration thereof is omitted. However, the output of the reference voltage generation circuit is connected to the terminal denoted Vref in FIG. 1A.

[0027] In FIG. 1A, the N-type MOS transistors QN1, QN2 and the current source 11 configure a differential pair. The P-type MOS transistor QP1 configures the load of the N-type MOS transistor QN1, and the P-type MOS transistor QP2 configures the load of the N-type MOS transistor QN2 to configure an amplifier circuit 20 as described above. The P-type MOS transistor QP3 and the resistors R1, R2 configure an output stage 21 as described above. The constant voltage generation circuit 10 also includes an overshoot suppression circuit 22 for suppressing the overshoot described earlier. The overshoot suppression circuit 22 is configured including the diodes D1, D2.

[0028] The reference voltage Vref is input to a gate of the N-type MOS transistor QN1 of the amplifier circuit 20, and a feedback voltage Va is input to a gate of the N-type MOS transistor QN2. The feedback voltage Va is a voltage that is divided from the output voltage Vout by the resistor R1 and resistor R2 that are connected to a drain of the P-type MOS transistor QP3. The feedback voltage Va is compared against the reference voltage Vref, and a comparison result difference is applied to a gate of the P-type MOS transistor QP3 as an error voltage, so as to maintain the output voltage Vout at a constant voltage value based on the reference voltage Vref.

[0029] Next, explanation follows regarding operation of the overshoot suppression circuit 22, with reference to FIG. 1B. FIG. 1B illustrates operating waveforms of the power source voltage Vp, a gate voltage Vg of the P-type MOS transistor QP3, and the output voltage Vout accompanying start-up of a power source.

[0030] The diodes D1, D2 configuring the overshoot suppression circuit 22 are connected between the power source voltage Vp and the gate of the P-type MOS transistor QP3 in the orientation illustrated in FIG. 1A. The diodes D1, D2 suppress the gate voltage Vg of the P-type MOS transistor QP3 configuring an output transistor from diverging (falling behind) excessively in response to a steep rise in the power source voltage Vp. As illustrated in FIG. 1B, as well as maintaining the effect of suppressing the gate voltage Vg from diverging (falling behind) excessively, the gate voltage Vg is also made to follow the power source voltage Vp, with the result of suppressing the occurrence of overshoot in the output voltage Vout.

[0031] More specifically, in cases in which the diodes D1 and D2 have the same specifications and each has a forward voltage drop of Vf, then a difference between the power source voltage Vp and the gate voltage Vg will always be 2Vf or below as illustrated in FIG. 1B. Namely, the gate voltage Vg is clamped at (Vp−2Vf) or higher. As illustrated in FIG. 1B, after the power source voltage Vp has been switched on, the gate voltage Vg is maintained at approximately 0V before rising from a timing t1 when 2Vf is reached, thereby suppressing a gate-source voltage Vgs of the P-type MOS transistor QP3 from diverging (increasing) excessively.

[0032] In other words, since the gate voltage Vg of the P-type MOS transistor QP3 is supplied via the diodes D1, D2, the gate voltage Vg starts to move faster than the feedback action of the amplifier circuit 20, enabling a period T1 during which the gate voltage Vg is extremely low (approximately 0V) to be ended swiftly. Note that in the constant voltage generation circuit 10 according to the present exemplary embodiment, a relationship between the gate voltage Vg when in a steady state (a state in which the output voltage Vout has reached a target voltage) and the power source voltage Vp is set so as to satisfy the relationship of Equation 1 below.

Vg>(Vp−2Vf)  (Equation 1)

[0033] Since power does not pass through the diodes D1, D2 as long as Equation 1 is satisfied, the overshoot suppression circuit 22 (the diodes D1, D2) do not affect normal operation of the constant voltage generation circuit 10.

[0034] Note that although an example has been given in the above exemplary embodiment in which two diodes configure the overshoot suppression circuit 22 is two, the number of diodes is not limited thereto. The number of diodes employed may be set as appropriate according to the design conditions and so on of the constant voltage generation circuit. However, the number of diodes configuring the overshoot suppression circuit 22 needs to be determined in consideration of a current value flowing in the P-type MOS transistor QP3 configuring the output transistor. Moreover, in principle, the overshoot suppression effect is reduced as the number of diodes increases, and so an upper limit for the number of diodes may be set based on permitted overshoot standards and the like.