Power regulator and power conversion circuitry for delivering power

Abstract

A DC-to-DC transformer converts power from an input source to a load using a fixed voltage transformation ratio. The density of point of load power conversion may be increased and the associated power dissipation reduced by removing the input driver circuitry from the point of load where it is not necessary. An output circuit may be located at the point of load providing fault tolerant rectification of the AC power from the secondary winding of a power transformer which may be located nearby the output circuit. The driver circuit may drive a plurality of transformer-output circuit pairs. The transformer and output circuit may be combined in a single module at the point of load. Alternatively, the output circuit may be integrated into point of load circuitry such as a processor core. The transformer may be deployed near the output circuit.

Claims

1. An apparatus comprising: a first assembly including a circuit board and an integrated circuit (IC) load mounted to the circuit board, the integrated circuit load requiring input power to be supplied via an IC power input at an IC voltage for operation, and the circuit board providing electrical connections to the integrated circuit load, wherein the integrated circuit load comprises a low voltage high current processor that requires a peak voltage less than or equal to 3 volts and a peak current greater than or equal to 100 amperes; power conversion circuitry including an input for receiving power at a conversion input voltage, V.sub.IN, an output for delivering power at a conversion output voltage, V.sub.OUT, one or more power switching elements, and a switch controller for operating the one or more power switching elements in a series of converter operating cycles, wherein the conversion circuitry is configured to convert power from the input to the output using an essentially fixed transformation ratio K=Vout/Vin, where K is less than 1, and wherein K is constant over a range of conversion input voltages; the IC power input being connected via the circuit board to receive power from the output of the power conversion circuitry; at least a portion of the power conversion circuitry being mounted to the circuit board in the first assembly; and a power regulator for supplying power to the input of the power conversion circuitry, the power regulator being external to the first assembly.

2. The apparatus of claim 1 wherein K< 1/10.

3. The apparatus of claim 1 wherein K< 1/48.

4. The apparatus of claim 1 wherein the power conversion circuitry includes input circuitry and output circuitry and the output circuitry is mounted to the circuit board.

5. The apparatus of claim 1 wherein at least a portion of the power conversion circuitry mounted to the circuit board includes one or more of the power switching elements.

6. The apparatus of claim 1 wherein the power conversion circuitry further comprises an inductive component and a current flowing in the inductive component charges and discharges capacitances in a bus converter reducing a voltage across one or more of the one or more power switching elements prior to turning said one or more of the one or more power switching elements ON.

7. The apparatus of claim 1 wherein the power conversion circuitry further comprises an inductive component and a current flowing in the inductive component charges and discharges capacitances in a bus converter and wherein a current through one or more of the one or more power switching elements is reduced prior to turning said one or more of the one or more power switching elements ON or OFF.

8. The apparatus of claim 1 wherein the power conversion circuitry further comprises a transformer, input circuitry including one or more primary power switching elements connected to drive the transformer, and output circuitry connected to receive power from the transformer.

9. The apparatus of claim 8 wherein the transformer is mounted to the circuit board.

10. The apparatus of claim 1 wherein the integrated circuit load comprises a semiconductor die including a microprocessor and at least a portion of the power conversion circuitry.

11. An apparatus comprising: an integrated circuit (IC) load requiring input power to be supplied via an IC power input at an IC voltage and an IC current for operation, where the IC voltage may vary over a range and is less than or equal to 3 volts and the IC current may vary over a range including a peak current greater than or equal to 100 amperes; power conversion circuitry including an input for receiving power at a conversion input voltage, V.sub.IN, an output for delivering power at a conversion output voltage, V.sub.OUT, one or more power switching elements, and a switch controller for operating the one or more power switching elements in a series of converter operating cycles, wherein the conversion circuitry is configured to convert power from the input to the output using an essentially fixed transformation ratio K=Vout/Vin, where K is less than 1, and wherein K is constant over a range of conversion input voltages; the IC power input being connected to receive power from the output of the power conversion circuitry; at least a portion of the power conversion circuitry being packaged with the integrated circuit load.

12. The apparatus of claim 11 wherein K< 1/10.

13. The apparatus of claim 11 wherein K< 1/20.

14. The apparatus of claim 11 wherein K< 1/48.

15. The apparatus of claim 11 wherein the portion of the power conversion circuitry is formed in the IC load.

16. The apparatus of claim 11 wherein the power conversion circuitry further comprises an inductive component and a current flowing in the inductive component charges and discharges capacitances in a bus converter reducing a voltage across one or more of the one or more power switching elements prior to turning said one or more of the one or more power switching elements ON.

17. The apparatus of claim 11 wherein the power conversion circuitry further comprises an inductive component and a current flowing in the inductive component charges and discharges capacitances in a bus converter and wherein a current through one or more of the one or more power switching elements is reduced prior to turning said one or more of the one or more power switching elements ON or OFF.

18. The apparatus of claim 11 wherein the power conversion circuitry further comprises a transformer, input circuitry including one or more primary power switching elements connected to drive the transformer, and output circuitry connected to receive power from the transformer.

19. The apparatus of claim 18 wherein the transformer is co-packaged with the integrated circuit load.

20. The apparatus of claim 11 further comprising a regulation stage having a regulator input connected to receive power from a source, a regulator output connected to deliver power to the input of the power conversion circuitry at the conversion input voltage, and regulation circuitry adapted to regulate the power deliver via the regulator output.

21. The apparatus of claim 11 wherein the integrated circuit load comprises a semiconductor die including a microprocessor and at least a portion of the power conversion circuitry.

22. An apparatus comprising: an integrated circuit (IC) load requiring input power to be supplied via an IC power input at an IC voltage for operation, where the IC voltage may vary over a range and is less than or equal to 3 volts, wherein the integrated circuit load comprises a processor that requires a peak current greater than or equal to 100 amperes; power conversion circuitry including an input for receiving power at a conversion input voltage, V.sub.IN, an output for delivering power at a conversion output voltage, V.sub.OUT, one or more power switching elements, and a switch controller for operating the one or more power switching elements in a series of converter operating cycles to convert power from the input to the output, where a ratio of the conversion input voltage V.sub.IN to the conversion output voltage V.sub.OUT is 10 or more to 1, wherein the power conversion circuitry comprises a conversion stage that receives an input voltage and generates an output voltage and is configured to convert power from an input of the conversion stage to an output of the conversion stage using an essentially fixed transformation ratio K that is less than 1, and K is constant over a range of input voltages to the conversion stage; the IC power input being connected to receive power from the output of the power conversion circuitry; at least a first portion of the switching elements of the power conversion circuitry being packaged with the integrated circuit load in a same die.

23. The apparatus of claim 22 further comprising a circuit board and wherein the integrated circuit load is mounted to the circuit board and at least a second portion of the power conversion circuitry is mounted to the circuit board.

24. The apparatus of claim 23 wherein the power conversion circuitry comprises an essentially fixed transformation ratio, K=V.sub.OUT/V.sub.IN.

25. The apparatus of claim 24 wherein K= 1/20 or less.

26. The apparatus of claim 24 wherein K= 1/48 or less.

27. The apparatus of claim 24 further comprising a regulation stage having a regulator input connected to receive power from a source, a regulator output connected to deliver power to the input of the power conversion circuitry at the conversion input voltage, and regulation circuitry adapted to regulate the power delivered via the regulator output.

28. The apparatus of claim 24 wherein the power conversion circuitry further comprises an inductive component and a current flowing in the inductive component charges and discharges capacitances in a bus converter reducing a voltage across one or more of the one or more power switching elements prior to turning said one or more of the one or more power switching elements ON.

29. The apparatus of claim 24 wherein the power conversion circuitry further comprises an inductive component and a current flowing in the inductive component charges and discharges capacitances in a bus converter and wherein a current through one or more of the one or more power switching elements is reduced prior to turning said one or more of the one or more power switching elements ON or OFF.

30. The apparatus of claim 24 wherein the power conversion circuitry further comprises a transformer, input circuitry including one or more primary power switching elements connected to drive the transformer, and output circuitry connected to receive power from the transformer.

31. An apparatus comprising: an integrated circuit (IC) load requiring input power to be supplied via an IC power input at an IC voltage for operation, where the IC voltage may vary over a range and is less than or equal to 3 volts, wherein the integrated circuit load comprises a processor that requires a peak current greater than or equal to 100 amperes; power conversion circuitry having an input for receiving power at a conversion input voltage, V.sub.IN, and an output circuit including an output for delivering power at a conversion output voltage, V.sub.OUT, and one or more power switching elements; the power conversion circuitry further including a driver circuit including a switch controller for operating the one or more power switching elements in a series of converter operating cycles, wherein the conversion circuitry is configured to convert power from the input to the output using an essentially fixed transformation ratio K=V.sub.OUT/V.sub.IN, where K is less than 1, and wherein K is constant over a range of conversion input voltages; wherein a first assembly includes the output circuit of the power conversion circuitry and the integrated circuit load, and an electrical connection between the output circuit of the power conversion circuitry and the IC power input for delivery of power from the power conversion circuitry to the integrated circuit load; wherein the driver circuit is separated by a distance from the output circuit and connected to provide one or more control signals to the output circuit for operating the one or more power switching elements in the output circuit.

32. The apparatus of claim 31 wherein K< 1/10.

33. The apparatus of claim 31 wherein K< 1/48.

34. The apparatus of claim 31 wherein the first assembly includes a circuit board, the integrated circuit load is mounted to the circuit board, the power conversion circuitry includes input circuitry and output circuitry, and the output circuitry is mounted to the circuit board.

35. The apparatus of claim 31 wherein the first assembly includes a circuit board, at least a portion of the power conversion circuitry is mounted to the circuit board, and the portion of the power conversion circuitry mounted to the circuit board includes one or more of the one or more power switching elements.

36. The apparatus of claim 31 wherein the power conversion circuitry further comprises an inductive component and a current flowing in the inductive component charges and discharges capacitances in a bus converter reducing a voltage across one or more of the one or more power switching elements prior to turning said one or more of the one or more power switching elements ON.

37. The apparatus of claim 31 wherein the power conversion circuitry further comprises an inductive component and a current flowing in the inductive component charges and discharges capacitances in a bus converter and wherein a current through one or more of the one or more power switching elements is reduced prior to turning said one or more of the one or more power switching elements ON or OFF.

38. The apparatus of claim 31 wherein the power conversion circuitry further comprises a transformer, input circuitry including one or more primary power switching elements connected to drive the transformer, and output circuitry connected to receive power from the transformer.

39. The apparatus of claim 38 wherein the first assembly includes a circuit board, and the transformer is mounted to the circuit board.

40. The apparatus of claim 31 wherein the processor comprises a semiconductor die including at least a portion of the power conversion circuitry.

41. The apparatus of claim 40 wherein the semiconductor die includes at least some of the power switching elements.

42. An apparatus comprising: a first assembly including a circuit board and an integrated circuit (IC) load mounted to the circuit board, wherein the integrated circuit load is configured to receive input power supplied via an IC power input at an IC voltage for operation, the circuit board provides electrical connections to the integrated circuit load; power conversion circuitry including a power regulator and a power converter, wherein the power conversion circuitry includes an input connected to receive power from a source and an output for delivering power at the IC voltage, the power converter includes one or more primary power switching elements, one or more secondary power switching elements, and switch control circuitry for operating the primary and secondary power switching elements in a series of converter operating cycles, the power converter is configured to convert power from an input of the power converter to an output of the power converter using an essentially fixed transformation ratio, the ratio is at least 10 to 1, and the ratio is constant over a range of conversion input voltages; wherein the IC power input is connected via the circuit board to receive power from the output of the power conversion circuitry; wherein the integrated circuit load comprises a semiconductor die including a microprocessor, at least some of the secondary power switching elements, and a portion of the switch control circuitry for controlling the secondary power switching elements in the semiconductor die; and wherein the primary switching elements and a portion of the switch control circuitry for controlling the primary switching elements are external to the first assembly.

43. The apparatus of claim 42 wherein the switch control circuitry in the semiconductor die is configured to operate the secondary power switching elements in the semiconductor die to perform zero-voltage switching.

Description

DESCRIPTION OF DRAWINGS

(1) FIG. 1 shows a block diagram of a prior-art fault-tolerant power system.

(2) FIG. 2A shows the output circuitry portion of a prior art power converter.

(3) FIG. 2B shows the output circuitry portion of a prior art power converter.

(4) FIG. 3 shows an improved power converter having a half-bridge input circuit and a full-bridge output circuit including fault protection.

(5) FIG. 4 shows an improved half-bridge output circuit for a power converter including fault protection.

(6) FIG. 5 shows a multi-cell power converter including fault protection.

(7) FIG. 6 shows a fault tolerant power converter.

(8) FIG. 7 shows an improved dual p-channel MOSFET device.

(9) FIG. 8 shows an improved dual n-channel MOSFET device.

(10) FIG. 9 shows the die of a prior art semiconductor device.

(11) FIG. 10 shows the die of an interdigitated common-source dual MOSFET semiconductor device.

(12) FIG. 11 shows the schematic of an improved fault-tolerant power converter.

(13) FIGS. 12A-12D show timing waveforms for operating the switches in the converter of FIG. 11.

(14) FIG. 13 shows a resonant primary circuit for modifying the converter of FIG. 11 to a SAC based topology.

(15) FIG. 14 shows a modular fault-tolerant converter based on the SAC topology.

(16) FIG. 15 shows the modular fault-tolerant converter of FIG. 14 with load circuitry.

(17) Like references symbols in the various drawings indicate like elements.

DETAILED DESCRIPTION

(18) I. Cycle-by-Cycle Fault Tolerance

(19) A DC transformer delivers a DC output voltage, V.sub.out, which is a fixed fraction of the voltage, V.sub.in delivered to its input. The voltage transformation ratio or voltage gain of the DC transformer (which may be defined as the ratio, K=V.sub.out/V.sub.in, of its output voltage to its input voltage at a load current) is fixed by design, e.g. by the converter topology, its timing architecture, and the turns ratio of the transformer included within it. In certain practical implementations without a feedback loop, using non-idealized components, the effective output resistance of the DC transformer will cause some droop in output voltage as a function of load current.

(20) Referring to FIG. 3, an improved DC transformer topology is shown having an input circuit 50 coupled to the primary winding 82 of transformer 81, and an output circuit 100 coupled to secondary winding 83 for delivering high-current, low-voltage in fault-tolerant applications. The input circuit 50 as shown may use a half-bridge switching circuit for driving the primary winding 82 with power received from the input. Two primary switches 51, 52 are connected in a series circuit leg across the input. Two capacitors 53, 54 are also connected in a series circuit leg across the input. The primary winding is connected across the two legs, with one end of the winding connected to the junction 57 of switches 51, 52 and the other end of the winding connected to the junction 58 of capacitors 53, 54. The primary switches 51, 52 are alternately turned ON and OFF in opposition by switch controllers 55, 56 respectively. Although separate switch controllers 55, 56 are shown in FIG. 3 and referenced in the description below, the control functions may be combined in a single integrated controller, e.g. a primary side switch controller, for control of the primary switches. By appropriate selection of the capacitors 53, 54 and transformer characteristics, such as leakage inductance, the DC transformer of FIG. 3 may be operated as a SAC using the control architecture described in the SAC patent.

(21) In operation, the primary switches 51, 52 are alternately turned ON and OFF to drive the primary winding 82 in a series of converter operating cycles. Because the voltage at the junction of the capacitors will be approximately one half of the input voltage, V.sub.in, during steady-state operation, the half-bridge circuit 50 provides 2-to-1 voltage division at the primary of the transformer which is beneficial in low output voltage applications. Fault tolerance may be built into the input circuit 50 by preventing one primary switch from turning ON or staying ON while the opposite switch may be conducting, e.g. by sensing the voltage across the opposite switch. Switch controllers 55, 56 may therefore be configured to wait for the voltage across the opposite switch 52, 51 to increase to a level sufficient to ensure that it has turned OFF before turning its respective switch ON. Preferably, the controllers are configured to turn ON their respective switches at the occurrence of a maximum in the voltage across the opposite switch to provide zero voltage switching (“ZVS”) transitions for its respective switch. Thus if one switch should short, the other switch will not turn ON or stay ON preventing the converter input 50 from creating a short across the power bus used to provide power to other converters in the system. The fault tolerant input circuit 50 may be used to eliminate the need for a disconnect switch at the input of the converter. Additional fault tolerance functionality may be incorporated in the converter as discussed below in connection with FIG. 6.

(22) A. Full-Bridge Output

(23) The secondary side of converter 80 includes output circuit 100 connected to the secondary winding 83 of transformer 81. As shown, four switch rectifiers, 110, 120, 130, and 140 are connected in a full-bridge rectifier circuit. Switch Rectifiers 110, 120 and 130, 140 are connected in respective series circuit legs across the output. The secondary winding is connected across the two legs, with one end of the winding connected to the junction 101 of switches 110, 120 and the other end of the winding connected to the junction 102 of switch rectifiers 130, 140.

(24) As shown, the switch rectifiers 110, 120, 130, 140 may each comprise a MOSFET 111, 121, 131, 141 and a switch controller 112, 122, 132, 142, respectively. Although shown as p-channel and n-channel devices capable of blocking current in one direction because of the parasitic body diodes, MOSFETS 111, 131 and 121, 141 may be configured to block current in both directions. Each switch controller may turn its respective switch ON and OFF to function as a rectifier for example by sensing the polarity of voltage across its respective switch and turning it ON for a first polarity and OFF for the opposite polarity. A two terminal synchronous rectifier is described in Vinciarelli et al, Components Having Actively, Controlled Circuit Elements, U.S. Pat. No. 6,985,341 issued Jan. 10, 2006 (assigned to VLT, Inc. Sunnyvale, Calif. and incorporated herein in its entirety). For the n-channel enhancement mode MOSFET based switch rectifiers 120, 140 shown in the example of FIG. 3, the controllers 122, 142 may turn their respective MOSFETs 121, 141 ON only if its respective source terminal becomes more positive than its drain terminal. For the p-channel enhancement mode MOSFET based switch rectifiers 110, 130 shown in the example of FIG. 3, controllers 112, 132 may turn their respective MOSFETs 111, 131 ON only if its respective source terminal becomes more negative than its drain terminal.

(25) Because the secondary winding 83 is connected to the output through a full-bridge rectification circuit, two switches must be ON to complete the circuit. During the first half cycle, switch rectifiers 110 and 140 must be ON to complete the circuit and during the next half cycle, switch rectifiers 120 and 130 must be ON. As a result, the output circuit 100 presents potentially higher power losses in the rectifier circuit than a half-wave configuration (FIGS. 2A, 2B) for low output voltages and therefore seems disadvantageous. However, output circuit 100 has a significant advantage in its ability to decouple the failed output from the system bus 13 (FIG. 1) in the event of a fault. To prevent the output circuit 100 from creating a short across the system bus, the switches are controlled to ensure that no switch is turned ON until its complementary switch is OFF. For example, if switch rectifier 110 failed by shorting junction 101 to the positive side of the output, switch 121 would be disabled effectively isolating the fault and decoupling the converter output from the system bus.

(26) The polarity sensing switched rectifiers described above ensure that the switches will not short the output. For example if switch rectifier 110 failed by shorting junction 101 to the positive side of the output, the source of MOSFET 121, which is connected to the negative side of the output, cannot become more positive than its drain, which, being connected to junction 101, has been shorted by failed switched rectifier 110 to the positive output. Therefore, switch rectifier 120 will remain OFF. Similarly, if switch rectifier 120 failed by shorting junction 101 to the negative side of the output, the source of MOSFET 111 which is connected to the positive output terminal cannot become more positive than its drain, which being connected to junction 101 has been shorted by failed switched rectifier 120 to the negative output. Therefore, switch rectifier 110 will remain OFF. The same fault tolerant control protocol prevents a short across the output by the other series circuit leg. In this way, the fault tolerant output circuit 100 ensures that a single switch fault will not produce a short across the output.

(27) The output circuit may continue to operate for half-wave rectification even in the event of a shorted switch. For example, with switch rectifier 110 shorted, switch rectifier 120 would be disabled, however, switch rectifier 140 could continue to operate normally turning ON during half-cycles having a polarity that supplies power to the output and OFF for the alternate half-cycles. With switches capable of blocking current in both directions the converter could continue to operate in such a half-wave mode.

(28) However, caution should be exercised if switches capable of blocking current in only one direction, such as those shown schematically in FIG. 3, are used. For output voltages greater than the forward voltage drop of the body diodes, the body diode may clamp the secondary winding. Assume for example that switch rectifier 110 is shorted with the converter continuing to operate. Although switch rectifier 120 will remain OFF preventing a short across the output, the body diode of MOSFET 131 will clamp the secondary during the half cycles in which switch 120 would normally be ON to its forward voltage. Switches capable of blocking current in both directions are therefore necessary in applications where the output voltage is greater than the forward voltage of the body diodes if the converter is allowed to continue to operate after a fault.

(29) Because fault isolation is provided in the rectification circuit, the output circuit 100 (FIG. 3) of the converter may be connected directly to the system bus 13 (FIG. 1), avoiding the need for an additional isolation switch, e.g. 16, 20 (FIG. 1). Although the number of switches required on the output side increases from 3 to 4 and the output current still passes through two switches, the full-bridge fault-tolerant output circuit eliminates the need for an external fault detection and isolation circuit, saving system space and complexity. Additionally, the breakdown voltage rating for the output switches may be reduced by a factor of two: 2*Vo for the prior art half-wave rectified output vs. Vo in the full-bridge fault-tolerant output 100 of FIG. 3. Lower breakdown voltage MOSFETs tend to have lower ON resistance, which offers lower power loss in the full-bridge fault-tolerant output circuit 100. As discussed below, lowering the breakdown voltage to Vo may allow the MOSFETs to be integrated onto the same die as the circuitry to which it is supplying power such as a processor core. Furthermore, the full-wave rectified output of FIG. 3 requires half as many turns in the secondary winding than in the winding of the center-tapped half-wave rectified output (FIGS. 2A, 2B), which allows a larger gauge conductor, or a larger multiplicity of parallel conductors, to be used in the secondary winding potentially reducing secondary conduction losses. At low output voltages and high currents utilizing low resistance switch rectifiers, the winding losses can exceed the losses in the switch rectifiers favoring the fault-tolerant full-bridge output circuit.

(30) B. Half-Bridge Output

(31) Referring to FIG. 4, a half-bridge fault-tolerant output circuit 150 is shown connected to secondary winding 83. In contrast to the output circuit of FIG. 3, only two switch rectifiers 110, 120 are shown in FIG. 4 forming a half-bridge rectifier for secondary winding 83. Like output circuit 100 (FIG. 3), switch rectifiers 110, 120 are connected in a series circuit leg across the output. However, voltage doubling capacitors 135, 145 (FIG. 4) are connected in a series circuit leg across the output in place of switch rectifiers 130, 140 of FIG. 3. The secondary winding is connected across the two legs, with one end of the winding connected to the junction 151 of switches 110, 120 and the other end of the winding connected to the junction 152 of capacitors 135, 145. The output circuit of FIG. 4 uses half as many switches as the output circuit 100 of FIG. 3, but also produces twice the output voltage which may be disadvantageous in low voltage applications.

(32) Each switch rectifier 110, 120 may, as described above in connection with FIG. 3, include a MOSFET 111, 121 and a switch controller 112, 122 to turn their respective switches ON and OFF to function as rectifiers. For the n-channel enhancement mode MOSFET device 120, the controller 122 may turn MOSFET 121 ON only when its source terminal becomes more positive than its drain terminal. For the p-channel enhancement mode MOSFET device 110, the controller 112 may turn MOSFET 111 ON only when its respective source terminal becomes more negative than its drain terminal. With the switch rectifiers 110, 120 functioning as rectifiers, a short failure in either switch will prevent the other switch from turning ON to create a short across the output. Similarly, in the unlikely event of a short in either capacitor, the other capacitor will prevent a short across the output and the switches will remain reverse biased and OFF.

(33) Output circuits 100, 150 may be used together with a half-bridge input circuit 50 or a full bridge input circuit (such as shown in FIGS. 11, 14 and discussed below) to provide fault tolerance in a power converter without requiring disconnect switches such as input disconnect switches 15, 19 and output disconnect switches 16, 20 shown in FIG. 1. Each switch controller 55, 56, 112, 122, 132, 142 may include a disable input (not shown) for receiving a disable signal in response to which each switch controller would turn OFF its respective switch(es) for over-riding normal operation. Referring to FIG. 6, a power converter 85, similar to the converter 80 of FIG. 3, is shown including an input circuit 50 coupled to an output circuit 100 via transformer 81. The power converter 85 as shown includes a fault-detection circuit 84 having a plurality of inputs 86, 87 for monitoring operating conditions, such as voltage transitions and voltages across one or more switches, output voltage, input voltage, temperature, etc. in the converter for detecting faults such as a switch failure, over-temperature, over voltage, etc. For example, the fault detection circuit 84 may monitor input nodes 57, 58 or output nodes 101, 102 for voltage transitions and voltages across switches. The failure of one node to complete a voltage transition or exhibit a certain voltage polarity may signal a switch failure in response to which the detection circuit 84 may disable the converter. In operation, in response to a detected fault condition, the fault-detection circuit 84 may send a disable signal to the disable input 88 of the primary side switch controllers 55, 56 and the disable input 89 of switch rectifiers 110, 120, 130, 140 in response to which each controller may turn its respective switches OFF. Although output circuit 100 is shown in FIG. 6, output circuit 150 may be used instead.

(34) II. Cell-by-Cell Fault Tolerance

(35) Referring to FIG. 5, a multi-cell power converter 90 is shown having two input cells 50A, 50B having inputs connected in parallel with an input, V.sub.in, and connected to drive parallel primary windings 82A, 82B respectively with power received from the input. Four secondary windings 83A-83D coupled to the primary windings via transformer 81A are connected to a respective output circuit 100A-100D, the outputs of which are connected in parallel to provide an output voltage, V.sub.o to a load (not shown). All of the input circuits 50 may employ the same topology, e.g. half-bridge as shown in FIG. 3 or full-bridge, as the other input circuits. Similarly, all of the output circuits 100 may employ the same topology, e.g. full-bridge output circuit 100 (FIG. 3) or half-bridge output circuit 150 (FIG. 4), as the other output circuits. In operation, the input cells 50A, 50B each drive the transformer 81 in a power-sharing array of cells. Similarly, the output cells 100A, 100B, 100C, 100D form a power-sharing array in supplying power to the output. Because the input and output cells are fault-tolerant, the converter 90 may continue to operate, albeit at a reduced power throughput capacity, after a fault. For example, in the event one of the input cells fails, e.g. 50A, the converter 90 may continue to operate processing power through input cell 50B. Similarly, if one or more of the output cells fail, e.g. 100A, 100B, the power converter 90 may continue to operate, processing power through output cells 100C, and 100D. The power converter 90 of FIG. 5 therefore provides a more granular fault-tolerant power-sharing solution than might be possible with individual power converters. For the multi-cell converter of FIG. 5, it is preferable to use switches that are capable of blocking current in both directions as discussed above in connection with FIG. 3. A fault detection circuit such as detection circuit 84 (FIG. 6) may be used with the multi-cell converter 90 shutting down individual cells or all cells depending on the nature of the fault.

(36) III. Common Source Synchronous Rectifier

(37) Referring to FIGS. 7 and 8, common-source dual synchronous rectifier devices particularly adapted for use in synchronous rectification applications including the fault-tolerant full-bridge output circuit 100 (FIG. 3) and in standard center-tapped output circuits are shown. A common-source dual p-channel enhancement mode MOSFET device 300 is shown in FIG. 7. As shown, the device includes two p-channel MOSFET switches 311A, 311B having their respective source terminals connected to a common terminal 301. The drains of switches 311A, 311B are connected to terminals 302, 303 respectively. Each switch 311A, 311B is turned ON and OFF by a respective control circuit 312A, 312B which has an output connected to the gate terminal of the switch. Each control circuit 312A, 312B, which may include an amplifier as shown, has inputs for sensing the source-to-drain voltage of its respective switch 311A, 311B. The offset and gain of the control circuit may be set to ensure that its switch turned ON when the drain of its switch is more positive than the source by a predetermined threshold, such as 5 mV, and fully ON when the drain of its switch is more positive than the source by a predetermined positive level, such as 10 mV.

(38) The p-channel common-source dual synchronous-rectifier 300 may be self-powered, e.g. for use in a three terminal package as shown in FIG. 7, by connecting the negative power supply rail of control circuit 312A to the drain terminal 303 of the complementary device 311B. Similarly, the negative power supply rail of control circuit 312B may be connected to the drain terminal 302 of its complementary device 311A. In operation, only one switch 311A, 311B may be turned ON at a time because the power to turn each switch ON is derived from a reverse bias across the other switch. The three-terminal dual synchronous-rectifier 300 is particularly well adapted for use in the output circuit 100 of FIG. 3. For example, switched rectifiers 110 and 130 may be replaced with a single common source device 300. The device 300 may also be used in a center-tap output circuit 30A (FIG. 2A) in place of MOSFETs 31A, 32A.

(39) A common-source dual n-channel enhancement mode MOSFET device 350 is shown in FIG. 8. As shown, the device includes two n-channel MOSFET switches 361A, 361B having their respective source terminals connected to a common terminal 351. The drains of switches 361A, 361B are connected to terminals 352, 353 respectively. Each switch 361A, 316B is turned ON and OFF by a respective control circuit 362A, 362B which has an output connected to the gate terminal of the switch. Each control circuit 362A, 362B, which may include an amplifier as shown, has inputs for sensing the source-to-drain voltage of its respective switch 361A, 361B. The offset and gain of the control circuit may be set to ensure that its switch is turned ON when the drain of its switch is more negative than the source by a predetermined threshold, such as −5 mV, and fully ON when the drain of its switch is more negative than the source by a predetermined negative level, such as −10 mV.

(40) The n-channel common-source dual synchronous-rectifier 350 also may be self-powered, e.g. for use in a three terminal package as shown in FIG. 8, by connecting the positive power supply rail of control circuit 362A to the drain terminal 353 of the complementary device 361B. Similarly, the positive power supply rail of control circuit 362B may be connected to the drain terminal 352 of its complementary device 361A. In operation, only one switch 361A, 361B may be turned ON at a time because the power to turn each switch ON is derived from a reverse bias across the other switch. The three-terminal dual synchronous-rectifier 350 is particularly well adapted for use in the output circuit 100 of FIG. 3. For example, switched rectifiers 120 and 140 may be replaced with a single common source device 350. The device 350 may also be used in a center-tap output circuit 30B (FIG. 2B) in place of MOSFETs 31B, 32B.

(41) The dual common-source synchronous rectifiers of FIGS. 7 and 8 may be deployed in the output circuit 100 of FIG. 3 to provide an additional benefit in which a switch adjacent (e.g. switches 110 and 130 are adjacent each other, switches 120 and 140 are adjacent each other) a shorted switch is prevented from turning ON because its power is derived from the reverse bias of the adjacent switch. The dual common-source synchronous rectifiers may also be used in the output circuits of FIGS. 11 and 14 as discussed below.

(42) The dual common-source synchronous-rectifier devices shown in FIGS. 7 and 8 may use the common-source MOSFET device described below in connection with FIG. 10 to reduce the interconnection resistance and thus reduce the ON resistance and further reduce the power losses in the rectifiers. The dual common-source interdigitated MOSFETs and the control circuits of FIGS. 7 and 8 may be integrated onto a single die. Alternatively, one or two separate MOSFET die and a controller die may be mounted to a substrate, such as a printed circuit board providing interconnections between the die and terminals for connection to an external circuit (e.g. output circuit 100), and over molded into a system in a package (“SIP”). The SIP may have three terminals as shown in FIGS. 7 and 8, or may include additional terminals for providing external power to the control circuits, or a disable input for disabling the switches.

(43) IV. Common-Source FETs

(44) Referring to FIG. 9, a die 510 of a prior art dual MOSFET device is shown having two macro MOSFET devices 510A and 510B each comprising a multiplicity of individual elements 511A, 511B respectively. As shown, the die is conceptually and logistically divided in two by a dashed line with the individual elements 511A, 511B making up each MOSFET 510A, 510B segregated.

(45) Referring to FIG. 10, an improved dual common-source MOSFET device 550 is shown including a multiplicity of individual elements 551A, 551B arranged in columns. The pattern illustrated includes three columns of elements for each device: starting from left to right with a single column of 551A elements, a pair of columns of 551B elements, a pair of columns of 551A elements, and ending with a single column of 551B elements. The elements in the columns labeled 551A make up macro device 551A and the elements in the columns labeled 551B make up macro device 551B. The source and drain terminals of each individual element is labeled with an S and D. As shown, the source and drain terminals of individual elements within a column may be arranged to match those of the adjacent column of elements. In other words, all of the drains are available on one side and all the sources are available on the other side of a column of elements. This arrangement of elements with alternating columns of drains and sources is advantageous for making interconnections.

(46) Referring to FIG. 10, interconnections 561-567 are shown schematically with simple straight lines in the same plane as the individual elements. It should be understood, however, that the interconnections between individual elements, groups of elements, and external terminations such as a ball grid array are typically made in layers above the individual elements for example as described in Briere, Flip Chip FET Device, U.S. Pat. No. 6,969,909 issued Nov. 29, 2005 (the entire contents of which are incorporated here by reference). As shown in FIG. 10, the odd numbered interconnections 561, 563, 565, 567 are used for the drain connections and include a suffix, A or B, indicating to which MOSFET device they belong: the drains of the elements forming device 551A are connected to interconnect 561A and 565A and the drains of the elements forming device 551B are connected to interconnect 563B and 567B. The even numbered interconnections 562, 564, 566 are used for the source connections. As shown in FIG. 10, the source connections 562, 564, 566 are shared by both MOSFET devices 551A, 551B, i.e. the sources of the elements in columns 551A and 551B are connected together by interconnections 562, 564, 566.

(47) The alternating pattern of interleaved elements, e.g. the alternating columns of elements in FIG. 10, may be said to be “interdigitated.” Using interdigitation in a multi-component device, such as the two MOSFET device in FIG. 10, allows for improved interconnection schemes. For example, only one source interconnection is required for the dual MOSFET device of FIG. 10 allowing for larger conductors to be used, only three high current conductors (Drain A, Drain B, and the common source) rather than the customary four (Drain A, Source A, Drain B, Source B) are required for making connections to the die 550. Although alternating pairs of columns of individual elements are shown, other alternating patterns, e.g. alternating rows, may be used depending upon the interconnection scheme to achieve the benefits of interdigitated MOSFET elements on the die. Additionally, alternating patterns of groups of individual elements may also be interdigitated to form for example checkerboard patterns.

(48) As described above, the interdigitated common-source dual-MOSFET devices may be used together with the type of control circuit shown in FIGS. 7 and 8 in a three or four terminal device. Alternatively, the interdigitated common-source dual-MOSFET devices may be provided as five terminal devices (Drain A, Drain B, Gate A, Gate B, Source) for use in applications which use external control circuitry such as in the input circuits 250, 420 shown in FIGS. 11 and 14 respectively.

(49) V. Regulating Efficiency and Output Resistance in DC Transformers and SACs.

(50) Referring to FIG. 11, another improved fault-tolerant power converter 200 is shown. The primary side of converter 200 includes a full-bridge input circuit 250 connected to primary winding 82 of transformer 81. As shown, four primary switches S1 251, S2 252, S3 253, and S4 254 are connected to form a full-bridge driver circuit. Switches 251, 252 and 253, 254 are connected in respective series circuit legs across the input, 211, 212. The primary winding is connected across the two legs, with one end of the winding connected to node 257 (the junction of switches 251, 252) and the other end of the winding connected to node 258 (the junction of switches 253, 254). Converter 200 may be based upon the Sine Amplitude Converter topology described in the SAC Patent and the POL SAC Patent, in which case a resonant capacitor may be inserted in series with one or both ends of primary winding 82, i.e. between the winding and nodes 257 and/or 258 for example as shown in FIG. 13.

(51) The secondary side of converter 200 is shown including a full-bridge output circuit 270 connected to the secondary winding 83 of transformer 81. As shown, four secondary switches R1 271, R2 272, R3 273, and R4 274 are connected in a full-bridge rectification circuit. Switches 271, 272 and 273, 274 are connected in respective series circuit legs across the output 213, 214. The secondary winding is connected across the two legs, with one end of the winding connected to node 277 (the junction of switches 271, 272) and the other end of the winding connected to node 278 (the junction of switches 273, 274).

(52) A. Operating Cycle Phases

(53) Referring to FIG. 12, converter 200 may be operated in a series of converter operating cycles having an operating period T. Beginning with a first power transfer phase (“IN+”), from time t0 to t1 in FIG. 12, switches S1 and S4 are ON, connecting primary winding 82 across the input source allowing the primary current to ramp up for a first half-cycle. The magnetizing energy in the transformer also increases in magnitude during the power transfer phase.

(54) An energy-recycling interval (ZVS.sub.1-2) is initiated at time t1, when switch S1 is turned OFF (switch S4 remains ON) and the magnetizing current flowing in the transformer primary is allowed to charge and discharge the capacitances associated with node 257. The capacitances at node 257 may include the parasitic capacitances associated with switches S1, S2 and added capacitance. At the end of the ZVS.sub.1-2 energy-recycling interval, when the voltage at node 257 reaches zero (or a minimum if there is insufficient magnetizing current to fully charge and discharge the capacitances at node 257), switch S2 may be turned ON at time t2 with essentially zero voltage across it. An energy recycling interval may be defined as a time interval during which energy stored in the transformer or other inductive components is used to charge or discharge capacitances across one or more switches to reduce the voltage across the switch in preparation for turning the switch ON.

(55) During the interval from time t2 to time t3, switches S2 and S4 are both ON clamping the primary winding 82 (the “CL.sub.2-4” phase). The windings and switches may be chosen to have minimal resistance which minimizes the resistance in the clamp circuit path that includes the primary winding 82, switch S2 and switch S4. As a result, the primary winding may be clamped for relatively long times without any appreciable decay in the magnetizing current which may be used for the next ZVS transition. The clamp phases may be used to control the effective output resistance of the converter or to reduce power dissipation during light loads as discussed further below. A clamp phase may be defined as a time interval during which: (i) one or more windings of the transformer is shunted, (ii) there is essentially zero voltage across the clamped winding or windings, (iii) energy is retained in the transformer, and (iv) essentially no current flows between the secondary winding and the output of the converter.

(56) Another energy-recycling interval (“ZVS.sub.4-3”) may be initiated at time t3 when switch S4 is turned OFF and the magnetizing current which is still flowing in the primary winding begins to charge and discharge the capacitances associated with node 258. The capacitances at node 258 may include the parasitic capacitances associated with switches S3, S4 and any added capacitance. At the end of the ZVS.sub.4-3 energy-recycling interval, when the voltage at node 258 reaches Vin (or a maximum if there is insufficient magnetizing current to fully charge and discharge the capacitances at node 258 to Vin), switch S3 may be turned ON at time t4 with essentially zero voltage across it.

(57) A second power transfer phase (IN−) occurs from time t4 to t5, during which switches S2 and S3 are ON, the primary winding 82 is connected across the input source and the primary current is allowed to ramp up. In the IN− phase, the primary winding 82 is connected in reverse and the primary current flows in the opposite direction than during the IN+ phase.

(58) An energy-recycling interval, ZVS.sub.2-1, may be initiated at time t5 when switch S2 is turned OFF (switch S3 remains ON) and the magnetizing current flowing in the transformer primary is allowed to charge and discharge the capacitances associated with node 257. When the voltage at node 257 reaches Vin (or a maximum if there is insufficient magnetizing current to fully charge and discharge the capacitances at node 257), switch S1 may be turned ON at time t6 with essentially zero voltage across it.

(59) Another clamp phase “CL.sub.1-3” may be entered from time t6 to time t7 with switches S1 and S3 both ON and clamping the primary winding 82. Like the circuit path for the CL.sub.2-4 phase, the resistance of the circuit for the CL.sub.1-3 phase may be minimized by appropriate selection of switches S1 and S3 allowing the primary winding to be clamped in the CL.sub.1-3 phase for relatively long times without any appreciable decay in the magnetizing current. Note that a second clamp phase is optional, therefore either of the CL.sub.1-3 or CL.sub.2-4 phases may be omitted extending the remaining clamp phase accordingly.

(60) A final energy-recycling interval, ZVS.sub.3-4, may be initiated at time t7 when switch S3 is turned OFF and the magnetizing current which is still flowing in the primary winding begins to charge and discharge the capacitances associated with node 258. At the end of the ZVS.sub.3-4 transition, when the voltage at node 258 reaches zero (or a minimum if there is insufficient magnetizing current to fully charge and discharge the capacitances at node 258 to zero), switch S4 may be turned ON with essentially zero voltage across it at time T+t0 beginning another converter operating cycle.

(61) Although FIGS. 12A-12D are labeled S1-S4 corresponding to the primary switches 251-254 in FIG. 11, the same timing may be applied to the secondary switches 271-274 respectively: switches S1 and R1, S2 and R2, S3 and R3, and S4 and R4 may be operated as shown in FIGS. 12A, 12B, 12C, and 12D respectively. For example, a switch controller 201 (FIG. 11) may control the primary and secondary switches. Control signals 202 may be connected to the primary switches 251-254 and their respective counterparts 271-274 (using the appropriate level shifters, pulse transformers, etc.) to drive each primary-secondary switch pair (e.g. switch pairs S1-R1, S2-R2, S3-R3, S4-R4) together. In this way, both primary and secondary windings would be clamped during each of the CL.sub.2-4 and CL.sub.1-3 phases preventing unwanted ringing due to the transformer leakage inductance. Clamping both windings of the transformer may increase the efficiency of the clamp because the primary and secondary clamp circuits are effectively connected in parallel which further reduces the resistance of the clamp circuit. In other words the clamp circuit becomes more ideal: the current passes through a lower resistance reducing dissipation and the voltage across each clamped winding is reduced further towards zero.

(62) B. SAC Topology Considerations

(63) The converter 200 of FIG. 11 may be configured using the Sine Amplitude Converter (“SAC”) topology described in the SAC Patent. The SAC topology typically includes a primary-side series resonant circuit. Referring to FIG. 13, a primary-side series resonant circuit 260 adapted for use with full bridge input circuit 250 of FIG. 11 is shown having a resonant capacitor 261, (and a second, optional, resonant capacitor for symmetry) 262 connected to each end of the primary winding 82. The resonant capacitors 261, 262 and the primary-reflected leakage inductance of the transformer form the series resonant circuit 260 defining the characteristic resonant frequency and period (the “operational resonant frequency” and “operational resonant period”) of the SAC. The ends, 257 and 258, of the series-resonant primary circuit 260 connect to the similarly labeled nodes of input circuit 250 in place of the transformer primary winding 82 shown in FIG. 11. Referring to FIG. 12, the duration of the IN+ and IN− phases for the SAC topology will be determined by the operational resonant frequency. As more fully explained in the SAC patent, the current in the primary winding is the sum of two components: a resonant current and the magnetizing current. Each of the IN+ and IN− phases are approximately equal in duration to a half cycle of the resonant current and therefore will be approximately equal to one half of the operational resonant period.

(64) As described above, the clamp phases are intended to clamp the transformer, typically by shunting one or more windings of the transformer, storing energy in the transformer for later use, e.g. to charge and discharge capacitances facilitating a ZVS transition. Closing the primary switches (S2-S4 or S1-S3) during a clamp phase in the SAC topology, however, shunts the resonant circuit 260, rather than the primary winding 82, allowing the magnetizing current to interact with the resonant capacitors, i.e. forming a resonant circuit between the magnetizing inductance of the transformer and the resonant capacitors 261, 262. The magnetizing inductance, typically being much larger than the leakage inductance, resonates with the resonant capacitors 261, 262 at a frequency (the “clamp resonant frequency”) much lower than the operating resonant frequency of the SAC. Although the oscillations during a clamp phase will occur over a much longer time scale, the magnetizing current will resonantly charge and discharge the resonant capacitors placing limits on the duration of the clamp phases using the primary switches in the SAC topology. It may be preferable therefore to clamp the secondary winding in the SAC topology rather than the primary resonant circuit.

(65) C. Control Strategies

(66) The power losses in a power converter include load dependent power dissipation and fixed losses due to operating the converter. Load dependent losses may include for example the power lost in the ON resistance of the switches and winding resistance which are a function of load. Fixed power losses may include power lost in turning the switches ON and OFF, i.e. charging and discharging the gate capacitances of MOSFET switches and core losses both of which may be a function of converter operating frequency. Typically power converters are optimized for operation at or near full load which may fix the gate drive levels and operating frequency. At light loads, however, the fixed losses can become significant impairing converter operating efficiency.

(67) 1. Efficiency Regulation

(68) One way to control the converter 200 of FIG. 11 and the SAC-based modification (described above in connection with FIG. 13), is to improve converter efficiency at light loads. Inserting one or more clamp phases (FIG. 12) in the operating cycle, in effect reduces the average number of converter operating cycles available to power the load which increases the average power the converter must process during each converter operating cycle. As the duration of the clamp phases is increased, the power processed by the converter during each operating cycle increases. In addition to allowing the converter to operate in a more efficient power range, the clamp phases help spread the fixed losses associated with each converter operating cycle over longer periods reducing the average fixed power losses at light loads while still allowing the power conversion to happen at the frequency set for peak efficiency. Although the load dependent losses may increase as the converter is forced to process more power during each converter operating cycle, the net result is more efficient converter operation at lower power levels.

(69) For example, the SAC version of the converter of FIG. 11 designed to deliver a nominal output voltage of 1V over a current range of 0-180 A optimized for loads greater than 30 A may have fixed losses of about 1.8 W. For loads from 30 to 180 Amps, the converter may operate at or above 93% efficiency, perhaps peaking at 95% efficiency at about 75 A. However, as the load decreases, the efficiency falls dramatically 85% at 10 A, 74% at 5 A, etc. By using variable duration clamp phases, increasing the duration as the load decreases, the same converter power train may achieve the same 93% or higher efficiency down to very light loads (e.g. 5 Amps or lower) with little or no penalty at higher loads. Assuming the characteristic period of the resonant circuit is 570 nS, each IN+ and IN− phase will be approximately 285 nS long. Further assuming minimum ZVS transitions of 5.7 nS each, with no clamp phases, the converter may be operated at 98% duty cycle peak. As the load decreases the clamp phases may be added and increased in duration e.g. up to 20 times the characteristic period each, reducing the effective duty cycle of the converter to 5%. At 5% duty cycle the fixed losses may be reduced almost by a factor of 20 dramatically improving the low load performance of the converter.

(70) 2. Output Resistance Regulation

(71) DC-to-DC voltage transformers, e.g. SACs, the converter 200 of FIG. 11, and the SAC based modification of converter 200 may be used to convert power from a Factorized Bus at a controlled voltage for delivery to a load, e.g. as described in the FPA and Micro FPA patents. The output voltage of the DC-to-DC voltage transformer may droop slightly as a function of load current due to the output resistance of the particular converter. Methods for compensating for the droop include using a feedback loop from the load to the power regulator supplying the Factorized Bus. It may be desirable in some applications to control the output resistance of the converter. The clamp phases may be used to control the effective output resistance of the converter of FIG. 11 (and the SAC based converter described above) is a function of the effective duty cycle. At the converters maximum duty cycle (e.g. 98% for the example above), the output resistance is minimized. As the clamp phases are added and the total clamp phase duration is increased, the output resistance will also increase. Using the example above, as the load decreases from 180 Amps to 10 Amps, the total clamp duration may be increased from 0 to 11.4 microseconds (corresponding to a decrease in duty cycle from 98% down to 5%), increasing the output resistance of the converter from less than 0.4 milliohms to more than 6 milliohms. By increasing the output resistance as the load decreases and vice versa, the output droop can be minimized in effect minimizing the effective output resistance of the converter.

(72) The controller 201 in FIG. 11 may be used to control the clamp phase duration as a function of load current to maximize efficiency over the operating range, to minimize the effective output resistance over the load range, or even to provide micro-regulation using variations in the output resistance at a particular operating point depending on the control algorithm and feedback loops. For example the clamp phase duration may be maximized for each load to reduce fixed converter losses, or may be controlled as a function of load to provide a linear decrease in output resistance with increasing load, or may be varied as a function of the difference between the output voltage and a reference voltage to control the output voltage independently of load current.

(73) The converter 200 of FIG. 11 and the SAC-based modification of converter 200 may be operated in the fault tolerant mode discussed above. Controller 201 may monitor nodes 257 and 258 for the primary-side voltage transitions, e.g. during the ZVS.sub.1-2, ZVS.sub.4-3, ZVS.sub.2-1, and ZVS.sub.3-4 phases, and nodes 277, 278 for secondary-side transitions to ensure that one switch opens before the next switch is closed. In the event of a switch failure all switches may be disabled to prevent a short across the input or output. Thus the input circuit 250 and output circuit 270 also provide fault tolerance as discussed above in connection with FIGS. 3-6. The input circuit 250 and output circuit 270 are full bridge circuits in which the interdigitated common-source MOSFET devices described above in connection with FIG. 10 may advantageously be used. The controller 201 in FIG. 11 operates the primary, and optionally the secondary switches, obviating the need for internal control circuits 312A, 312B (FIG. 7) and 362A, 362B (FIG. 8) in the input circuit 250 and output circuit 270 if operated by controller 201. Therefore the three-terminal common-source synchronous rectifiers of FIGS. 7 and 8 may not be necessary in the converter of FIG. 11, but may be used in the output circuitry if desired.

(74) VI. POL SAC with Remote Driver

(75) Referring to FIG. 14, a fault-tolerant converter 400 similar to the converter 200 of FIG. 11 modified with the series resonant circuit 260 of FIG. 13 is shown. The converter 400 includes a fault tolerant driver 420 connected to drive one or more point-of-load (“POL”) circuits 430 connected to the driver 420 via an AC bus 410. The driver 420 may comprise a full-bridge fault-tolerant input circuit such as input circuit 250 of FIG. 11 and a switch controller 425 similar to the switch controller described above in connection with FIG. 11. The POL circuit 430 may include a transformer circuit 440 and an output circuit 450. The transformer circuit 440 may include resonant capacitors 441, 442 connected to the primary winding 82 of transformer 81. Although shown connected to the primary winding, the resonant capacitors may instead be connected to the secondary winding. Similarly, a single resonant capacitor may be used instead of the two resonant capacitors shown in the symmetrical balanced circuit of FIG. 14. The secondary winding may be connected to a full-bridge fault-tolerant rectification circuit 450 as shown in FIG. 14. The full-bridge fault-tolerant rectification circuit 450 may use switches, R1, R2, R3, R4, operated as rectifiers in the manner described above in connection with the output circuit 100 of FIG. 3 and may preferably employ the common-source synchronous rectifiers described in connection with FIGS. 7 and 8. Note that a simplified symbol is used in FIG. 14 for switches S1-S4 and R1-R4 (instead of the enhancement mode MOSFET symbols used, e.g. in FIGS. 2-4, 7, 8, 11) in which the arrow indicates the direction of current flow through the intrinsic body drain diode when the switch is open.

(76) In contemporary electronic systems, space is at a premium on customer circuit boards, e.g. on a circuit board near a processor. Additionally, thermal management considerations place limits on the efficiency and power dissipation of power supplies at or near the point of load. As its name implies, the POL circuit 430 (FIG. 14) is designed to be deployed at the point of load, where space and thermal requirements are stringent. However, because the driver circuit 420 is not necessary at the point of load, it may be deployed elsewhere, away from the point of load, reducing the space required by the POL circuitry and reducing the power dissipation at the point of load. Because the driver circuitry is removed from the POL, a slightly larger transformer structure and output switches (R1-R4) may be used improving overall converter efficiency and reducing dissipation at the POL. Similarly, larger input switches (S1-S4) may be used in the driver circuit to further improve overall efficiency without impacting space considerations at the POL.

(77) However counter intuitive separating the driver 420 from the POL circuitry 430 and deploying an AC bus may initially seem, closer inspection refutes such objections. For example, power carried by the AC bus 410 is spectrally pure (sine wave) and has voltage and current slew rates less than those typically found in the signal paths of computer circuitry reducing concerns about noise and emissions.

(78) Although the driver circuit 420 is shown in FIG. 14 connected to only one POL circuit 430, it may in fact drive a plurality of POL circuits. The POL circuit 430 may be enclosed as a single module, i.e. packaged for deployment as a single self-contained unit, or as a pair of modules for deployment as component pairs, e.g. 440 and 450. Because switches R1-R4, need only withstand the output voltage, the output circuit 450 may be integrated (with or without the control circuitry, e.g. as shown in FIGS. 7 and 8) onto a die with circuitry to which it supplies power, e.g. a processor core.

(79) FIG. 15 is a diagram of an example of the fault-tolerant converter 400 of FIG. 14 with load circuitry 460, in which the switches R1-R4 are integrated onto a die 462 with the load circuitry 460.

(80) A number of embodiments of the invention have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. For example, the switch rectifiers may be operated by a common controller, or the synchronous rectifier function and fault tolerant functions may be combined into a single controller. A single clamp phase (e.g. CL.sub.2-4) may used rather than the dual clamp phase (CL.sub.2-4, CL.sub.1-3) operating cycle shown in FIG. 12. As described above, the secondary switches may be used to clamp the secondary winding during the clamp phase in addition to or instead of clamping the primary winding. A SAC topology including a half-bridge input circuit and a full-bridge output circuit may be used with the output switches providing the clamp function. The switch controller may recycle the energy from the gate capacitances for example as described in Vinciarelli, Low-Loss Transformer-Coupled Gate Driver, U.S. Pat. No. 6,911,848, issued on Jun. 28, 2005 (assigned to VLT, inc. of Sunnyvale, Calif., the entire disclosure of which is incorporated herein by reference).

(81) Accordingly, other embodiments are within the scope of the following claims.