Nanoelectromechanical devices with metal-to-metal contacts

Abstract

Nanoelectromechanical systems (NEMS) devices/switches and methods for implementing and fabricating the same with conducting contacts are provided. A nanoelectromechanical system (NEMS) switch can include a substrate; a source cantilever formed over the substrate and configured to move relative to the substrate; a drain electrode and at least one gate electrode formed over the substrate; wherein the source cantilever, drain and gate electrodes comprises a metal layer affixed to a support layer, at least a portion of the metal layer at the contact area extending past the support layer; and an interlayer sandwiched between the support layer and substrate.

Claims

1. A nanoelectromechanical system (NEMS) switch comprising: a substrate; a source cantilever formed over the substrate and configured to move relative to the substrate; a drain electrode and at least one gate electrode formed over the substrate, wherein the source cantilever, the drain, and the at least one gate electrode comprises a metal layer; and an interlayer sandwiched between a support layer and the substrate, wherein the drain electrode is connected to the substrate via the interlayer.

2. The NEMS switch of claim 1, wherein said metal layer comprises molybdenum silicide, platinum, gold, tungsten, or nickel.

3. The NEMS switch of claim 1, wherein said interlayer is an insulator.

4. The NEMS switch of claim 3, wherein said insulator comprises silicon, silicon dioxide, or silicon nitride.

5. The NEMS switch of claim 1, wherein the gate electrode is connected to the substrate via the interlayer.

6. A nanoelectromechanical system (NEMS) switch comprising: a substrate; a source cantilever formed over the substrate and configured to move relative to the substrate; a drain electrode and at least one gate electrode formed over the substrate, wherein the source cantilever, the drain, and the at least one gate electrode comprises a metal layer; and an interlayer sandwiched between a support layer and the substrate, wherein the source cantilever is connected to the substrate via the interlayer.

7. The NEMS switch of claim 6, wherein said metal layer comprises molybdenum silicide, platinum, gold, tungsten, or nickel.

8. The NEMS switch of claim 6, wherein said interlayer is an insulator.

9. The NEMS switch of claim 8, wherein said insulator comprises silicon, silicon dioxide, or silicon nitride.

10. The NEMS switch of claim 6, wherein the gate electrode is connected to the substrate via the interlayer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) FIG. 1 shows a schematic of an exemplary NEMS switch of the disclosed technology showing the source, drain and gate terminals as well as the air gaps, in accordance with an embodiment.

(2) FIG. 2 shows a plot of an exemplary COMSOL™ electrostatics simulation of the feedthrough effect, in accordance with an embodiment.

(3) FIG. 3A is the first in a series of schematic diagrams illustrating the results of progressive process stages in fabricating an all-metal NEMS switch apparatus, in accordance with the embodiments, in accordance with an embodiment.

(4) FIG. 3B is a schematic representation of a stage of fabrication of an all-metal NEMS switch apparatus, in accordance with an embodiment.

(5) FIG. 3C is a schematic representation of a stage of fabrication of an all-metal NEMS switch apparatus, in accordance with an embodiment.

(6) FIG. 3D is a schematic representation of a stage of fabrication of an all-metal NEMS switch apparatus, in accordance with an embodiment.

(7) FIG. 3E is a schematic representation of a stage of fabrication of an all-metal NEMS switch apparatus, in accordance with an embodiment.

(8) FIG. 3F is a schematic representation of a stage of fabrication of an all-metal NEMS switch apparatus, in accordance with an embodiment.

(9) FIG. 4 shows a scanning electron microscopy (SEM) image of an exemplary fully released free standing MoSi.sub.2 switch, in accordance with an embodiment.

(10) FIG. 5 shows a plot of an X-ray Photoelectron Spectroscopy (XPS) scan of an exemplary MoSi.sub.2 surface showing peaks for silicon, Mo 3d, oxygen and the adventitious hydrocarbon, in accordance with an embodiment.

(11) FIG. 6 shows an exemplary plot in which voltage ramps were applied to G1 until the source was in full contact with the drain, in accordance with an embodiment.

(12) FIG. 7 shows an exemplary plot, with the device pre-biased at 45 V, in which voltage ramps were applied to G2 to fully bring the source in contact with the drain, in accordance with an embodiment.

(13) FIG. 8 shows an exemplary plot showing that increasing the drain voltage generates additional electric field that abruptly attracts the source to contact the drain terminal, in accordance with an embodiment.

(14) FIG. 9 shows an exemplary Current-Voltage plot of measurements of the exemplary source-drain terminals of the closed switch, in accordance with an embodiment.

(15) FIG. 10 shows an exemplary plot of a high resolution XPS scan, in accordance with an embodiment.

(16) FIG. 11 shows a scanning electron microscopy (SEM) image of an exemplary fully released free standing gold switch, in accordance with an embodiment.

(17) FIG. 12 shows a scanning electron microscopy (SEM) image of an exemplary fully released free standing platinum-platinum contact switch, in accordance with an embodiment.

(18) FIG. 13A is the first in a series of schematic diagrams illustrating the results of progressive process stages in fabricating a NEMS switch apparatus, in accordance with the embodiments.

(19) FIG. 13B is a schematic representation of a stage of fabrication of a NEMS switch apparatus, in accordance with an embodiment.

(20) FIG. 13C is a schematic representation of a stage of fabrication of a NEMS switch apparatus, in accordance with an embodiment.

(21) FIG. 13D is a schematic representation of a stage of fabrication of a NEMS switch apparatus, in accordance with an embodiment.

(22) FIG. 13E is a schematic representation of a stage of fabrication of a NEMS switch apparatus, in accordance with an embodiment.

(23) FIG. 13F is a schematic representation of a stage of fabrication of a NEMS switch apparatus, in accordance with an embodiment.

(24) FIG. 13G is a schematic representation of a stage of fabrication of a NEMS switch apparatus, in accordance with an embodiment.

(25) FIG. 13H is a schematic representation of a stage of fabrication of a NEMS switch apparatus, in accordance with an embodiment.

(26) FIG. 14A is a schematic representation of a stage of fabrication of a NEMS switch apparatus, in accordance with an embodiment.

(27) FIG. 14B is a schematic representation of a stage of fabrication of a NEMS switch apparatus, in accordance with an embodiment.

DETAILED DESCRIPTION OF EMBODIMENTS

(28) Techniques, systems, and devices are described in detail herein and below related to nanoelectromechanical systems (NEMS) devices and for implementing and fabricating nanoelectromechanical systems (NEMS) devices with conductive contacts. In one aspect, a NEMS device can include a substrate, a source cantilever formed over the substrate and configured to move relative to the substrate, a drain formed over the substrate, and first, second and third gates formed over the substrate and separated from the source by first, second and third gaps, respectively. The source cantilever, the drain, the first, second and third gates form a NEMS actuator switch in which the source cantilever moves relative to the substrate in response to control voltages applied to the source cantilever, the drain, and the first, second and third gates. In some implementations of the device, for example, the device can be pre-biased at an electrical signal substantially close to a gate contact voltage. In some implementations of the device, for example, the substrate can include Si, Ge, SiC, pyrex and glass.

(29) The source cantilever, the drain, and the first, second and third gates can include a metal or a metal affixed to a support structure. In some implementations of the device, for example, the third gate can be electrically floating, the drain can be set at an electrical potential, and the source cantilever can be configured to switch between different positions in response to varying control voltages applied to the first and second gates. In some implementations of the device, for example, the device can further include a junction gate field effect transistor (JFET) formed over the substrate to include a JFET drain, a JFET source, and a JFET gate, in which the JFET gate is coupled to the source cantilever to form a JEFT-NEMS actuator switch.

(30) In one embodiment, for example, an exemplary NEMS-based actuator device can include a NEMS switch design in which the air gaps are configured to be larger such that there is no pull-in during the operation of the switch. For example, a metal can be used as the structural and conducting contact material for the NEMS switch in this exemplary design.

(31) To reduce gate leakage current and polydepletion effects in future generations of advanced transistors such as the FinFET or Ultrathin-Body MOSFET, the International Roadmap for Semiconductors (ITRS) has suggested the use of high-k gate dielectrics and dual-metal-gate electrodes. The inventor has recognized that molybdenum silicide (MoSi.sub.x) and pure Molybdenum (Mo) seem to be the ideal metal gate stack because of the appropriate workfunctions to n-channel and p-channel devices respectively. Hence, MoSi.sub.2 is a material in commercial foundries.

(32) At the same time, MEMS technology is currently leveraging various materials such as silicon, silicon dioxide and MoSi.sub.2 layers that are present in CMOS technology. Besides MoSi.sub.2 being a great midgap metal for the next generation of transistors, it has a high Young's modulus (430 GPa) which makes it ideal as a structural material for nanostructures such as accelerometers, switches and gyroscopes. MoSi.sub.2 also exhibits a superb etch resistance to HF and Buffered Oxide Etch. Herein, described in an embodiment, is the use of MoSi.sub.2 as a structural material for a NEMS switch. NEMS switches are favored for their near zero ideal power dissipation and abrupt ON-OFF state transitions. But some of the major challenges in NEMS switches are stiction of the source terminal to the drain, high switching voltages, stress gradient in the structural material used and maintaining a low contact resistance. Disclosed is an exemplary NEMS switch that is CMOS compatible and addresses some of these challenges.

(33) The disclosed NEMS switch is designed to operate in non-pull-in fashion. Pull-in is an instability phenomenon where, for example, in a parallel plate capacitor with the bottom plate fixed and the top plate free to move displaces one-third of the actuation gap and the electrical force becomes larger than the mechanical restoring force. Under this condition, the top plate becomes unstable and snaps or pulls-in to the bottom plate.

(34) The pull-in voltage is given by the following equation:

(35) $\begin{array}{cc}{V}_p=\sqrt{\frac{8}{27}}\frac{{\mathrm{Kd}}_o}{\mathrm{.Math.}A}& \mathrm{Eq}.\left(1\right)\end{array}$

(36) where V.sub.p represents the pull-in voltage, K is the spring constant of the cantilever, d.sub.o is the initial actuation gap, ε is the permittivity of the dielectric in the actuation gap, in this case its air and A is the actuation area. Equation 1 stipulates that to prevent pull-in the actuation gap has to be increased. FIG. 1 shows a schematic of an exemplary device which shows multiple electrodes as well as air gaps. In this example, the contact gap (g.sub.sd) was designed to be (300 nm) such that the source is fully in contact with the drain before pull-in at either g.sub.01 (900 nm) or g.sub.02 (700 nm). The source cantilever is 25 μm long, 500 nm wide and has a thickness of 1 μm.

(37) FIG. 1 shows a schematic of an exemplary NEMS switch of the disclosed technology showing the source, drain and gate terminals as well as the air gaps. The exemplary device operation is as follows: (1.) The source and G.sub.2 are grounded and G.sub.3 is floating. The drain is set at a potential. (2.) Sweep G.sub.1 until the source contacts the drain. This is the gate contact voltage (V.sub.c). (3.) Pre-bias the device close to the gate contact voltage. (4.) Apply switching voltage (V.sub.sh) to G.sub.2 to usher full contact.

(38) The advantage of pre-biasing the device is that the switching voltage of the switch can be dramatically decreased to sub-1 V because the contact gap that needs to be closed is very small and as a result, small voltage on G.sub.2 causes switching. Pre-bias is similar to the back-bias used in CMOS for adjusting the transistor threshold voltage. For example, sub-500 μV switching voltages demonstrated using the pre-bias scheme. Also, since the All-Metal structure is formed on an insulating layer (oxide layer), voltage transients applied to G.sub.1 feedthrough the buried oxide layer and air to G.sub.3 to generate a floating potential. FIG. 2 shows the electric field distribution when G.sub.1 voltage is ramped to 50 V. With 50 V applied to G.sub.1, G.sub.3 acquires a floating potential of 11 V which serves as a restoring electrostatic force on the source cantilever when G.sub.1 voltage is switched off. This automatic pull-back mechanism helps to mitigate the stiction problem which plagues NEMS switches.

(39) FIG. 2 shows a plot of an exemplary COMSOL™ electrostatics simulation of the feedthrough effect that is generated when voltage ramps are applied to G.sub.1. The electric field lines couple through air and the dielectric layer to terminate on G.sub.3. The acquired floating potential on G.sub.3 provides additional restoring force to the source cantilever.

(40) The fabrication of the device is detailed in FIG. 3. An N-type silicon wafer is oxidized to grow 1.5 μm of dielectric (SiO.sub.2). 1 μm of metal is sputter deposited on the wafer in the presence of Ar gas. Standard photolithography steps are used to pattern the switch electrodes. With the resist serving as an etch mask, the metal layer is either ion milled or etched with Reactive Ion Etching. The exemplary devices were released by Buffered Oxide Etch and finally dried with a critical point dryer or vapor Hydrofluoric acid to prevent stiction.

(41) Referring to FIGS. 3A through 3F, in accordance with an embodiment, is a method for fabricating an all-metal NEMS switch.

(42) In FIG. 3A a substrate 302 is shown, and FIG. 3B shows an interlayer 304. In FIG. 3C, a metal layer 306 is deposited on the interlayer 304. In FIG. 3D, a photoresist 308 is spun on the metal layer 306 and standard lithography steps pattern the photoresist 308. In FIG. 3E, using the photoresist 308 as an etch mask, the metal layer 306 is etched with an ion mill, RIE or ICP process.

(43) In FIG. 3F, either a wet or dry isotropic etch is used to etch the underlying interlayer 304 to freely suspend the source cantilever.

(44) FIG. 4 shows an SEM micrograph of the exemplary device. The exemplary device was first tested in ambient to investigate its switching behavior. It was optically observed that even though there was full contact of the source to the drain, no current would flow. For example, freshly sputtered MoSi.sub.2 when exposed to air for 5 minutes forms SiO.sub.2 and tiny amount of MoO.sub.2 and after 24 hr exposure, the SiO.sub.2 content increased and the MoO.sub.2 was converted to MoO.sub.3. An exemplary reaction that occurs at the MoSi.sub.2 interface is given by Equation 2 and Equation 3:
⅓MoSi.sub.2+O.sub.2=⅔SiO.sub.2+⅓MoO.sub.2  (2)
2MoO.sub.2+O.sub.2=2MoO.sub.3  (3)

(45) The MoSi.sub.2 surface is believed to be covered with a duplex oxide layer of SiO.sub.2+MoO.sub.3. This duplex layer can easily absorb carbonaceous contaminants as well as water vapor and hydrocarbons.

(46) FIG. 4 shows a scanning electron microscopy (SEM) image of an exemplary fully released free standing MoSi.sub.2 switch. As seen in the image, there is no stress gradient in the source cantilever. The drain and source contact areas were covered with this duplex oxide layer, water vapor and hydrocarbons.

(47) FIG. 5 shows an exemplary X-ray Photoelectron Spectroscopy (XPS) analysis of the MoSi.sub.2 film which was conducted with Surface Science Instrument using a monochromated Aluminum K-alpha x-rays. A 300 μm beam spot size was used for scanning and a flood gun was used to neutralize charging effects. Oxygen was used as a reference in analyzing the data. As seen in FIG. 5, the spectra display the presence of the adventitious hydrocarbon (C is at 284.6 eV) as well as a high peak of oxygen (O 1s at 532 eV). The highest peak of Mo 3d occurs at 228 eV.

(48) FIG. 5 shows a plot of an XPS scan of an exemplary MoSi.sub.2 surface showing peaks for silicon, Mo 3d, oxygen and the adventitious hydrocarbon. The 2.95 eV shift in the O 1s peak was used to compensate for this measured results. The inset of FIG. 5 shows a high resolution scan which shows the presence of the Mo 3d5/2 and Mo 3d3/2 of the consolidated MoSi.sub.2.

(49) When the switch was tested in a vacuum probe station, at low pressures of 0.1 mbars, there was not significant current flow from the drain to the source until the pressure reached ˜4e-4 mbars. At this pressure, the water vapor and the hydrocarbons desorbed from the contact area. To investigate the gate contact voltage, the source was grounded and 8 V applied to the drain. G.sub.2 and G.sub.3 were made to float and a 100 nA current compliance set for the drain and source currents. Voltage ramps were applied to G.sub.1 until the source contacted the drain. Both the source and drain currents were monitored. FIG. 6 is the measured gate contact voltage of 48.2 V with an OFF state drain current of 83 pA and I.sub.ON/I.sub.OFF ratio was 1204.

(50) FIG. 6 shows plots of exemplary voltage ramps that were applied to G.sub.1 until the source was in full contact with the drain. For example, the OFF state drain current was 83 pA with an I.sub.ON/I.sub.OFF ratio of 1204.

(51) With the gate contact voltage determined as 48.2V, the device was pre-biased to 45 V and voltage ramps applied to G.sub.2 to usher in full contact. FIG. 7 is the measured switching voltage of 6.1 V. This switching voltage is scalable depending on the gate contact voltage. So as the pre-bias voltage is increased, less voltage is required by G.sub.2 for switching.

(52) FIG. 7 shows an exemplary plot, with the device pre-biased at 45 V, in which voltage ramps were applied to G.sub.2 to fully bring the source in contact with the drain.

(53) The drain voltage has an effect on the switching voltage. As the source-drain gap decreases, any additional drain voltage will generate excess electric field that will abruptly attract the source to the drain. This phenomenon is similar to the conventional pull-in effect in NEMS devices but here, the source cantilever does not have to be displaced one-third of the air gap before it experiences instability and initiate a pull-in effect. FIG. 8 shows the effect of the drain voltage on the switching voltage of the device. From FIG. 8, the switching voltage can be tuned from 8 V to 6.1 V by increasing the drain voltage from 5 V to 8 V.

(54) FIG. 8 shows an exemplary plot showing that increasing the drain voltage generates additional electric field that abruptly attracts the source to contact the drain terminal.

(55) FIG. 8 also shows that IDS increases 100 folds from V.sub.DS=5 V to V.sub.DS=8 V. This drastic increment in drain current could be attributed to the fact that as V.sub.DS was increased, the electric field at the source and drain contact was also increased to a point where there was a partial breakdown of the SiO.sub.2+MoO.sub.3 duplex layer.

(56) To further investigate the possibility of the partial breakdown of the duplex layer, the switch was fully closed and the drain voltage ramped from 0 V to 8 V. FIG. 9 shows that substantial current conduction begins at V.sub.DS=7.3 V where the duplex layer was partially broken down. The duplex layer is broken down and current begins to flow and the linear IV characteristics from 7.3 V to 8 V shows that an ohmic contact is established between the source and drain contacts. The source-drain current conduction path is very resistive (80 MΩ) which is due to the formation of the duplex layer and high contact resistance. Sputtering of oxide-resistant materials such as Platinum or Iridium around the MoSi.sub.2 structures can also be implemented to decrease this resistance.

(57) FIG. 9 shows an exemplary Current-Voltage plot of measurements of the exemplary source-drain terminals of the closed switch that shows that active current conduction begins at V.sub.DS=7.3 V.

(58) The reliability of the switch was examined in exemplary implementations by pre-biasing G.sub.1 at 45 V and 8 V applied to the drain with the source grounded. A 50% duty cycle AC signal was applied to G.sub.2 with a peak-to-peak voltage of 18 V, running at 10 KHz. The drain current was sampled every 2 seconds and the implementation terminated when the value of the drain current reduced 8 times. For example, 302,240 cycles where accrued. For example, dielectric charging of the duplex layer may have caused the source to be stuck to the drain in this exemplary implementation. The exemplary device utilized in this exemplary implementation was inspected using SEM, but showed that the source was separated from the drain. For example, it is possible that during the transfer of the switch to the SEM, the dielectric layer was fully discharged.

(59) FIG. 10 shows an exemplary plot of a high resolution XPS scan showing a 2.95 eV shift in the O 1s peak which was caused by the use of the flood gun to neutralize the charging of the sample. Various techniques could be used to improve the source-drain contact resistance by depositing a conductive material (2D material, metal or alloy) at the contact or forming the entire switch from non-oxidizing metal.

(60) In one embodiment, the entire switch was fabricated from metal (i.e., gold) as shown in FIG. 11. As shown, the source cantilever exhibited an extensive amount of stress gradient.

(61) In another embodiment, to control the amount of stress gradient in the source cantilever, the metal layer was affixed to a structural support layer as shown in FIG. 12. The support layer could be silicon, silicon dioxide, silicon nitride, another metal or alloy.

(62) In addition, to ensure that a metal-to-metal contact is achieved between the source cantilever and the drain electrode, the portion of the support layer at the contact area could be removed either by dipping the device in a solution that etches the support layer or by using an isotropic dry etch to perform the undercut. FIG. 12 illustrates a NEMS switch with a platinum metal layer affixed to a silicon structural support layer. An isotropic dry RIE etch was used to remove a portion of the silicon support layer at the contact area.

(63) Referring to FIGS. 13A through 13H, in accordance with an embodiment, is a method for fabricating a NEMS switch with overhang metal contacts is shown.

(64) In FIG. 13A a substrate 1302 is shown, and FIG. 13B shows an interlayer 1304 and a support layer 1306. In FIG. 13C, a metal layer 1308 is deposited on the support layer 1306. In FIG. 13D, a photoresist 1310 is spun on the metal layer 1308 and standard lithography steps pattern the photoresist 1310 and etch the metal layer 1308 and the support layer 1306.

(65) In FIG. 13E, a photoresist layer 1310 is spun. In FIG. 13F, standard lithography steps pattern the photoresist 1310 at the contact areas of the source, drain and gate electrode. In FIG. 13G, a dry isotropic etch is used to etch the support layer 1306 to produce a metal overhang at the contact area of the source 1314, drain 1312 and gate 1316.

(66) In FIG. 13H, either a wet or dry isotropic etch is used to etch the underlying interlayer 1304 to freely suspend the source cantilever.

(67) In another embodiment, using the same process flow as illustrated in FIG. 13A-13F, instead of using an isotropic dry etch to create the metal overhang, a Focused Ion Beam could be used to achieve the undercut as shown in FIGS. 14A and 14B.

(68) The process described in FIGS. 13A-13H and 14A and 14B are not limited to the fabrication of NEMS switches but could be adapted to any N/MEMS device with at least two contacting points.

(69) While various embodiments have been described and illustrated herein, those of ordinary skill in the art will readily envision a variety of other means and/or structures for performing the function and/or obtaining the results and/or one or more of the advantages described herein, and each of such variations and/or modifications is deemed to be within the scope of the embodiments described herein. More generally, those skilled in the art will readily appreciate that all parameters, dimensions, materials, and configurations described herein are meant to be exemplary and that the actual parameters, dimensions, materials, and/or configurations will depend upon the specific application or applications for which the teachings is/are used. Those skilled in the art will recognize, or be able to ascertain using no more than routine experimentation, many equivalents to the specific embodiments described herein. It is, therefore, to be understood that the foregoing embodiments are presented by way of example only and that, within the scope of the appended claims and equivalents thereto, embodiments may be practiced otherwise than as specifically described and claimed. Embodiments of the present disclosure are directed to each individual feature, system, article, material, kit, and/or method described herein. In addition, any combination of two or more such features, systems, articles, materials, kits, and/or methods, if such features, systems, articles, materials, kits, and/or methods are not mutually inconsistent, is included within the scope of the present disclosure.

(70) The above-described embodiments of the described subject matter can be implemented in any of numerous ways. For example, some embodiments may be implemented using hardware, software or a combination thereof. When any aspect of an embodiment is implemented at least in part in software, the software code can be executed on any suitable processor or collection of processors, whether provided in a single device or computer or distributed among multiple devices/computers.

(71) Only a few implementations and examples are described and other implementations, enhancements and variations can be made based on what is described and illustrated in this patent document.