TIME-DELAY CIRCUIT FOR A DIGITAL SIGNAL, PARTICULARLY FOR A CLOCK SIGNAL

Abstract

The invention relates to a time-delay circuit (1) for a digital signal (3), particularly for a clock signal, comprising:

an input (2) for the digital signal (3);
an oscillator (4) for generating an internal clock signal (5);
at least one delay channel (6) adding a certain delay to the digital input signal (3) based on the internal clock signal (5); and
an output (7) for a delayed digital signal (8).

Claims

1. A time-delay circuit for a digital signal, comprising: an input for the digital signal; an oscillator configured to generate an internal clock signal; at least one delay channel configured to add a certain delay to the digital input signal based on the internal clock signal; and an output configured to provide for a delayed digital signal.

2. The time-delay circuit according to claim 1, wherein the time-delay circuit comprises multiple delay channels, wherein each delay channel adds a certain delay to a part of the digital input signal based on the internal clock signal, and wherein the delayed digital signal is an aggregation of the delayed parts of the input signal by the multiple delay channels.

3. The time-delay circuit according to claim 2, wherein the multiple delay channels have the same or different delays.

4. The time-delay circuit according to claim 1, wherein the certain delay of the at least one delay channel is adjustable, particularly for each delay channel.

5. The time-delay circuit according to claim 4, further comprising a delay selector for adjusting the certain delay of the at least one delay channel.

6. The time-delay circuit according to claim 1, wherein the certain delay of the at least one delay channel is adjustable by dividing the internal clock signal, preferably within each channel for multiple delay channels.

7. The time-delay circuit according to claim 1, wherein the oscillator is a process, voltage and temperature compensated oscillator.

8. The time-delay circuit according to claim 1, further comprising an edge detector for the digital input signal, wherein the edge detector assigns a rising edge of the digital input signal to a first part of the delay channels and a falling edge of the digital input signal to a second part of the delay channel.

9. The time-delay circuit according to claim 8, wherein the edge detector is part of the input of the time-delay-circuit and/or part of the delay channel, particularly of each of the multiple delay channels.

10. The time-delay circuit according to claim 8, wherein the output of the delay channel aggregates the delayed signals for the rising edge and the falling edge.

11. The time-delay circuit according to claim 1, wherein the at least one delay channel comprises multiple delay components each providing a delay to the input signal of the delay channel, wherein the certain delay of the at least one delay channel is defined by a selection of one or more of the delays provided by the multiple delay components.

12. The time-delay circuit according to claim, wherein the at least one delay channel comprises a multiplexer for selecting the one or more delays provided by the multiple delay components.

13. The time-delay-circuit according to claim 10, wherein the multiple delay components are programmable.

14. The time-delay circuit according to claim 1, wherein the oscillator is programmable.

Description

SHORT DESCRIPTION

[0027] In the following embodiments of this disclosure will be explained with respect to the following figures.

[0028] FIG. 1 illustrates a block diagram of a first embodiment of a time-delay circuit according to some embodiments of the invention.

[0029] FIG. 2 illustrates a block diagram of a second embodiment of a time-delay circuit according to some embodiments of the invention.

[0030] FIG. 3 illustrates signal diagrams for a single channel and dual channel time-delay circuit according to some embodiments of the invention.

[0031] FIG. 4 illustrates a signal diagram for a dual channel time-delay circuit with different delay components for the rising and falling edges.

[0032] FIG. 5 illustrates a schematic block diagram of a third embodiment of a time-delay circuit according to the invention.

[0033] FIG. 6 illustrates a schematic block diagram of different embodiments of time-delay circuits according to the invention combined in one diagram.

DETAILED DESCRIPTION

[0034] FIG. 1 shows a block diagram of a first embodiment of a time-delay circuit 1 for a digital signal 3, particularly a clock signal, according to the invention. The time-delay circuit 1 comprises an input 2 for the digital signal 3 and an output 7 for a delayed digital signal 8.

[0035] The time-delay circuit 1 further comprises an oscillator 4 for generating an internal clock signal 5 and multiple delay channels 6. Each delay channel 6 adds a certain delay to a part of the digital input signal 3 based on the internal clock signal 5. Advantageously, the pulses of the digital input signal 3 are sequentially divided to the different delay channels 6, thereby enhancing the maximum supported input frequency. According to the embodiment of FIG. 1 the time-delay circuit 1 comprises n channels and the first pulse of the input signal 3 is assigned to the first delay channel 6, the second pulse of the input signal 3 is assigned to the second delay channel 6, the third pulse of the input signal 3 is assigned to the third delay channel 6, up to the n-th pulse of the input signal 3 that is assigned to the n-th delay channel 6.

[0036] According to some embodiments the delayed digital signal 8 of the output 7 is an aggregation of the delayed signals of the multiple delay channels 6.

[0037] Preferably, the certain delay of the delay channels 6 is adjustable for each delay channel 6. In this way the time-delay circuit 1 can be customized for a particular application, i.e. for providing a certain delayed digital signal 8 at the output 7.

[0038] For example, the certain delay of the delay channels 6 is adjustable by dividing the internal clock signal 5 within each delay channel 6. The delay channels 6 can have the same or different delays, for example by using the same division or different divisions of the internal clock signal 5. If the pulses of the digital input signal 3 are sequentially distributed to the different delay channels 6, these delay channels 6 preferably have the same delay.

[0039] The time-delay circuit 1 of FIG. 1 further comprises a delay selector 10 for adjusting the certain delay of the multiple delay channels 6, e.g. by amending the division of the internal clock signal 5 within each delay channel 6.

[0040] Advantageously, the oscillator 4 is a process, voltage and temperature compensated oscillator 4. Thus, the time-delay circuit 1 according to some embodiments is less susceptible to process, voltage and temperature variations.

[0041] Furthermore, the oscillator 4 is programmable, so that the internal clock signal 5 can be amended before and/or during operation. This further enables customization of the time-delay circuit 1 for different applications and/or variations during operation.

[0042] FIG. 2 shows a block diagram of a second embodiment of a time-delay circuit 1 for a digital signal 3, particularly a clock signal, according to some embodiments. The time-delay circuit 1 of FIG. 2 comprises an input 2 for the digital signal 3, an oscillator 4 for generating an internal clock signal 5, single delay channel 6 and an output 7 for a delayed signal 8. The output of the single delay channel 6 is also the output 7 of the time-delay circuit 1.

[0043] According to the second embodiment of FIG. 2 the input 2 comprises an edge detector 9 for the digital input signal 3. The edge detector 9 particularly comprises a rising edge detector 11 (also referred to as rising edge delay enable) and a falling edge detector 12 (also referred to as falling edge delay enable) for detecting the respective edges of the digital input signal 3.

[0044] The edge detector 9 assigns the rising edge and the falling edge of the digital input signal 3 to different parts 13, 14 of delay channel 6. Particularly, the delay channel 6 has two separate parts 13, 14, one part 13 for the rising edge of the digital input signal 3 and one part 14 for the falling edge of the digital input signal 3.

[0045] According to the second embodiment of FIG. 2 each part 13, 14 of the delay channel 6 comprises multiple delay components 15. Each delay component 15 provides a delay to the input signal 3 of the delay channel 6. In this embodiment the rising and falling edges of the input signal are assigned to parts 13, 14 of the delay channel and each part of the delay channel 6 comprises multiple delay components providing the certain delay for the rising respectively falling edge of the input signal 3. The certain delay of the delay channel 6 is defined by a selection of one or more of the delays provided by the multiple delay components 15.

[0046] The time delay circuit 1, particularly the delay channel 6, can further comprises two multiplexers 16, one for each group 13, 14 of delay channels 6. The signals of the multiple delay components 15 of one group 13, 14 are the input of one multiplexer 16 and the multiplexer 16 can select one or more of these delay component signals and forward these signals to the output 7.

[0047] The output of the delay channel aggregates the delayed signals for the rising edge and the falling edge and corresponds to the output 7 of the time-delay circuit 1.

[0048] Preferably the delay of the delay components 15 is adjustable for each delay component 15. Advantageously, the delay of the delay components 15 is programmable, i.e. can be modified/adapted. For example, the delay of the delay components 15 is adjustable by dividing the internal clock signal 5 within each delay component 15.

[0049] The delay channels 6 can have the same or different delays.

[0050] Like in the first embodiment shown in FIG. 1 the oscillator 4 is a process, voltage and temperature compensated oscillator 4 and preferably is programmable.

[0051] FIG. 3a shows a signal diagram for a single channel 6 time-delay circuit 1 according to some embodiments. The upper part shows the digital input signal 3 and the lower part shows the delayed output signal 8. The rising edges r1 and falling edges f1 are marked by corresponding arrows on the signals. The signal diagram for FIG. 3a could refer to the second embodiment of a time-delay circuit 1 shown FIG. 2.

[0052] FIG. 3b shows a signal diagram for a dual channel 6 time-delay circuit 1 according to some embodiments. The input signal 3 is sequentially, i.e. alternating, assigned to the first channel 6 and second channel 6 of the time-delay circuit 1. The first and second channel 6 provide the same time delay. The output signal 8 is an aggregation of the delayed signals of the first and second delay channel 6, symbolized by the OR-element in FIG. 3b. The rising and falling edges are correspondingly marked as r1, r2 respectively f1, f2 or a single or double arrow in FIG. 3b. The rising and falling edges can be delayed by separate delay components 15, as disclosed with respect to FIG. 2 and shown in more detail in FIG. 4.

[0053] FIG. 4 shows a signal diagram for a dual channel 6 time-delay circuit 1 with different parts 13, 14 for the rising and falling edges. The rising edges r1 of the input signal 3 are assigned to a first part 13 of the first delay channel 6 and the falling edges f1 of the input signal 3 are assigned to a second part 14 of the first delay channel 6. Accordingly, the rising edges r2 of the input signal 3 are assigned to a first part 13 of the second channel 6 and the falling edges f2 of the input signal 3 are assigned to a second part 14 of the second channel 6.

[0054] FIG. 5 shows a schematic block diagram of a third embodiment of a time-delay circuit 1 according to the invention. The digital input signal 2 is first divided into rising edges r1-rn and falling edges f1-fn, wherein n is the number of different delay channels 6 of the time-delay circuit 1. The rising and falling edges r1-rn, f1-fn are afterwards sequentially assigned to the different delay channels 6, number 1-n accordingly. Each delay channel 6 comprises a first group 13 of delay components 15 and a second group 14 of delay components 15. The rising edges r1-rn of the signal are processed by the first group 13 of the respective delay channel 6 and the falling edges f1-fn of the signal are processed by the second group 14 of the respective delay channel 6. The delay components 15 in each group 13, 14 provide different delays to the input signal assigned to the delay channel 6, specifically to the rising edge r1-rn or falling edge f1-fn of that signal. A multiplexer 16 selects the signal of that delay component 15 or multiple delay components 15 of both groups 13, 14 that provide the current desired delay. At the output of each delay channel 6 the rising edges r1-rn and falling edges f1-fn are aggregated. The signals of all delay channels 6 numbered 1 to n are aggregated to provide the final output signal 8 at the output 7 of the time-delay circuit shown in FIG. 5. The internal components of the delay channels 6 numbered 2 to n are identical to the details shown in the first delay channel 6. Thus, the third embodiment shown in FIG. 5 is a combination of the first embodiment shown in FIG. 1 and the second embodiment shown in FIG. 2.

[0055] FIG. 6 shows a schematic block diagram of different embodiments of time-delay circuits 1 according to some embodiments of the invention combined in one diagram.

[0056] A time-delay circuit 1 for a digital signal 3, particularly for a clock signal, in general comprises an input 2 for the digital signal 3, an oscillator 4 for generating an internal clock signal 5 and one or more delay channels 6, each adding a certain delay to the digital signal 3 based on the internal clock signal, and an output 7 for a delayed digital signal 8.

[0057] The internal layout of the input 2 for the digital signal 3 depends on the number of delay channels 6. In case of a single delay channel 6 the pulse of the digital signal 3 are sequentially forwarded to the single delay channel 6. This variant is shown in the upper part of the input 2 in FIG. 6. If the time-delay circuit 1 comprises two separate delay channels 6, the input 2 alternatingly assigns the pulses of the digital input signal 3 to the two delay channels 6. This variant is shown in the middle part of the input 2 in FIG. 6. Alternatively, the time-delay circuit 1 can comprise multiple delay channels 6. In this variant, the input 2 sequentially assigns the pulses of the digital input signal 3 to the different delay channels 6, which is shown in the lower part of the input 2 in FIG. 6. The advantage of multiple delay channels 6 is that higher frequencies of the digital input signal 3 can be supported.

[0058] Each delay channel 6 adds a certain delay to the digital input signal 3 respectively a part of the digital input signal 3 in case of multiple delay channels. For multiple delay channels 6, the delayed digital signal 8 at the output 7 of the time-delay circuit 1 is an aggregation of the delayed parts of the input signal 3 by the multiple delay channels 6. Preferably, the multiple delay 6 channels have the same certain delay, so that digital signal 8 at the output 7 is only delayed compared to the digital input signal 3, without changing the digital signal.

[0059] In an advantageous embodiment of the invention the certain delay of the one or more delay channels 6 is adjustable, for example using a delay selector 10. The certain delay of the one or more delay channels 6 is for example adjustable by dividing the internal clock signal 5.

[0060] Advantageously, the oscillator 4 is a process, voltage and temperature compensated oscillator 4. Furthermore, the oscillator 4 can be programmable.

[0061] The time-delay circuit 1 can further comprise an edge detector 9 for the digital input signal 3, wherein the edge detector 9 assigns the rising edge of the digital input signal 3 to a first part of the delay channel 6 and the falling edge of the digital input signal 3 to a second part of the delay channel 6.

[0062] According to FIG. 6 the edge detector 9 comprises a first part 9a, referred to as edge detect, separating the rising and falling edges of the digital input signal 3 depending on the number of delay channels 6, particularly by generating pulses R1, F1, R2, F2 to Rn, Fn for the rising and falling edges of the digital input signal 3. This first part 9a of the edge detector 9 is part of the input 2 according to FIG. 6. In case of a single delay channel 6, the first part 9a of the edge detector 9 generates pulses R1 and F1 for the rising and falling edges of the digital input signal 3. In case of two delay channels 6, the first part 9a of the edge detector 9 generates pulses R1, F1 and R2, F2 for alternating pulses of the digital input signal 3. In case of n delay channels 6 the first part 9a of the edge detector 9 generates pulses R1, F1, R2, F2 up to Rn, Fn for sequential pulses of the digital input signal 3. Each delay channels 6 comprises a second part 9b, referred to as delay enable, of the edge detector 9 that detects the generated pulses R1, F1, R2, F2 to Rn, Fn, wherein the first delay channel 6 receives the signals R1, F1, the second delay channel 6 receives the signal R2, F2 up to the n-th delay channel 6 receiving the signal Rn, Fn. The second part 9b of the edge detector 9 in each delay channel 6 comprises a rising edge detector 11 and a falling edge detector 12. Thus, according to the embodiment of FIG. 6 the edge detector 9 is part of the input 2 and each delay channel 6.

[0063] The rising and falling edges of the digital input signal 3 are delayed separately within each delay channel 6 and the output of the delay channel 6 aggregates the delayed signals for the rising edge and falling edge.

[0064] According to the embodiment shown in FIG. 6 each delay channel 6 comprises multiple delay components 15 each providing a delay to the input signal of the delay channel 6, wherein the certain delay of the at least one delay channel 6 is defined by a selection of one or more of the delays provided by the multiple delay components 15. Particularly, each delay channel 6 comprises a first part 13 and a second part 14 of delay components 15, wherein the first part 13 delays the rising edge of the input signal of the delay channel 6 and the second part 14 delays the falling edge of the input signal of the delay channel 6. The delay channels 6 comprise multiplexer 16 for the first and second part 13, 14 of delay components 15, wherein the multiplexer 16 selects one or more delays provided by the multiple delay components 15. According to FIG. 6 the multiplexers 16 are controlled by the selector 10.

LIST OF REFERENCE NUMERALS

[0065] 1 time-delay circuit [0066] 2 input [0067] 3 digital signal [0068] 4 oscillator [0069] 5 internal clock signal [0070] 6 delay channel [0071] 7 output [0072] 8 delayed digital signal [0073] 9 edge detector [0074] 9a edge detector (edge detect) [0075] 9b edge detector (delay enable) [0076] 10 channel selector [0077] 11 rising edge detector [0078] 12 falling edge detector [0079] 13 first part of channel group [0080] 14 second part of channel group [0081] 15 delay component [0082] 16 multiplexer