System and method for controlling switching network of a power regulation circuit

Abstract

A system for controlling a switching network of a power regulation circuit arranged to regulate power transfer between a first and second circuit connected with the power regulation circuit includes one or more controllers receiving one or more first signals indicative of power characteristics of the first circuit and one or more second signals indicative of power characteristics of the second circuit. The controllers determine, based on the received signals and reference signals, a required power output for regulating power transfer between the first and second circuit, and then select, dynamically, a switching scheme, from predetermined switching schemes, based on the determination result. The predetermined switching schemes represent unique switching schemea for controlling switching of respective switches of the switching network. The controllers generate, based on the dynamically selected switching scheme, output signals for controlling switching of respective switches to regulate power transfer between the first and second circuit.

Claims

1. A system for controlling a switching network of a power regulation circuit, wherein the switching network comprises a first pair of switches and a second pair of switches arranged in parallel with each other, and the switching network has a power output related to a voltage across a first node between the first pair of switches and a second node between the second pair of switches, the system comprising: one or more controllers arranged to: receive first signals indicative of power characteristics of an AC power circuit connected with the power regulation circuit and second signals indicative of power characteristics of a DC power circuit connected with the power regulation circuit, the first signals comprising a first current signal indicative of a current in the AC power circuit and a first voltage signal indicative of a voltage across the AC power circuit, and the second signals comprising a second current signal indicative of a current in the DC power circuit and a second voltage signal indicative of a voltage across the DC power circuit; determine, based on the first and second signals received and a reference current signal indicative of a reference current for the AC power circuit, a required power output of the switching network for regulating power transfer between the AC power circuit and the DC power circuit, wherein the required power output of the switching network is determined based on a ratio G defined by a required per-switching-period-mean voltage across the first and second nodes to a voltage across the DC power circuit, where −1≤G≤1, and the determination includes comparing the first current signal indicative of the current in the AC power circuit with the reference current signal; select, dynamically, a switching scheme from a plurality of predetermined switching schemes based on the ratio G, wherein each of the predetermined switching schemes represents a unique switching scheme having a unique switching pattern for the first and second pairs of switches per switching period T for controlling switching of the first and second pairs of switches, and wherein for each of the respective predetermined switching schemes, the duty cycles of the first and second pairs of switches are changeable; and generate, based on the dynamically selected switching scheme, output signals for controlling switching of respective switches of the switching network to regulate the voltage across the first and second nodes so as to regulate power transfer between the AC power circuit and the DC power circuit.

2. The system of claim 1, wherein the plurality of predetermined switching schemes comprises two or more of the following: a first switching scheme arranged to control the first and second pairs of switches such that the power output of the switching network is a first voltage value during 0 to ta1 and ta2, to T for each switching period T, where ta1 and ta2 represent time instances in the switching period T, and 0<ta1<ta2<T; a second switching scheme arranged to control the first and second pairs of switches such that the power output of the switching network is the first voltage value during tb1 to tb2 and tb3 to tb4 for each switching period T, where tb1, tb2, tb3, and tb4 represent time instances in the switching period T, and 0<tb1<tb2<tb3<tb4<T; a third switching scheme arranged to control the first and second pairs of switches such that the power output of the switching network is a second voltage value during 0 to tc1 and tc2 to T for each switching period T, where tc1 and tc2 represent time instances in the switching period, and 0<tc1<tc2<T, and the second voltage value is an additive inverse of the first voltage value; a fourth switching scheme arranged to control the first and second pairs of switches such that the power output of the switching network is the second voltage value during td1 to td2 and td3 to td4 for each switching period T, where td1, td2, td3, and td4 represent time instances in the switching period T, and 0<td1<td2<tl3<td4<T; a fifth switching scheme arranged to control the first and second pairs of switches such that the power output of the switching network is the first voltage value during 0 to te1 and te2 to T and the second voltage value during te1 to te2 for each switching period T, where te1 and te2 represent time instances in the switching period T, and 0<te1<te2<T; and a sixth switching scheme arranged to control the first and second pairs of switches such that the power output of the switching network is the first voltage value during 0 to tf1 and tf4 to T and the second voltage value during tf2 to tf3 for each switching period T, where tf1, tf2, tf3, tf4 represent time instances in the switching period T, and 0<tf1<tf2<tf3<tf4<T; wherein all of the predetermined switching schemes have the same switching period T.

3. The system of claim 2, wherein the power output of the switching network is symmetric about T/2 for each switching period T, for all predetermined switching schemes.

4. The system of claim 2, wherein the plurality of predetermined switching schemes comprises: the first switching scheme, the third switching scheme, and one of: the second and fourth switching schemes; the fifth switching scheme; and the sixth switching scheme.

5. The system of claim 4, wherein the one or more controllers are arranged to select the first switching scheme when it is determined that ⅓<G≤1; select the third switching scheme when it is determined that −1≤G<−⅓; select one of the following: the second switching scheme when it is determined that 0≤G<⅓ and the fourth switching scheme when it is determined that −⅓<G≤0; the fifth switching scheme when it is determined that −⅓≤G≤⅓; and the sixth switching scheme when it is determined that −⅓≤G≤⅓.

6. The system of claim 2, wherein all of the predetermined switching schemes have the same maximum switching frequency for the first and second pairs of switches.

7. The system of claim 2, wherein each of the predetermined switching schemes requires at most two switching actions for each respective switch in one switching period T.

8. The system of claim 1, further comprising one or more storage, operably coupled with the one or more controllers, for storing the plurality of predetermined switching schemes.

9. The system of claim 1, wherein the one or more controllers is further arranged to generate one or more reference signals.

10. The system of claim 1, wherein the one or more controllers is further arranged to receive one or more reference signals.

11. The system of claim 1, wherein the first and second pairs of switches comprise semiconductor switches.

12. The system of claim 1, wherein the one or more controllers comprises a controller and a PWM modulator.

13. The system of claim 1, wherein the power regulation circuit is arranged to regulate bi-directional power transfer between the AC power circuit and the DC power circuit.

14. A power regulation circuit for regulating power transfer between a AC power circuit and a DC power circuit, comprising: a switching network comprises a first pair of switches and a second pair of switches arranged in parallel with each other, arranged between the AC and DC power circuits, and the switching network has a power output related to a voltage across a first node between the first pair of switches and a second node between the second pair of switches; one or more controllers arranged to: receive first signals indicative of power characteristics of the AC power circuit connected with the power regulation circuit and second signals indicative of power characteristics of the DC power circuit connected with the power regulation circuit, the first signals comprising a first current signal indicative of a current in the AC power circuit and a first voltage signal indicative of a voltage across the AC power circuit, and the second signals comprising a second current signal indicative of a current in the DC power circuit and a second voltage signal indicative of a voltage across the DC power circuit; determine, based on the first and second signals received and a reference current signal indicative of a reference current for the AC power circuit, a required power output of the switching network for regulating power transfer between the AC power circuit and the DC power circuit, wherein the required power output of the switching network is determined based on a ratio C defined by a required per-switching-period-mean voltage across the first and second nodes to a voltage across the DC power circuit, where −1≤G≤1, the determination includes comparing the first current signal indicative of the current in the AC power circuit with the reference current signal; select, dynamically, a switching scheme from a plurality of predetermined switching schemes based on the ratio C, wherein each of the predetermined switching schemes representing a unique switching scheme having a unique switching pattern for the first and second pairs of switches per switching period T for controlling switching of the first and second pairs of switches, and wherein for each of the respective predetermined switching schemes, the duty cycles of the first and second pairs of switches are changeable based on the ratio G; and generate, based on the dynamically selected switching scheme, output signals for controlling switching of respective switches of the switching network to regulate the voltage across the first and second nodes so as to regulate power transfer between the AC power circuit and the DC power circuit.

15. The power regulation circuit of claim 14, further comprising: one or more storage, operably coupled with the one or more controllers, for storing the plurality of predetermined switching schemes.

16. The power regulation circuit of claim 14, further comprising: an inductor arranged at an interface between the first node and the AC power circuit; and a capacitor across the DC power circuit, at an interface between the switching network and the DC power circuit.

17. The power regulation circuit of claim 14, wherein the power regulation circuit is arranged to regulate bi-directional power transfer between the AC and DC power circuits.

18. A method for controlling a switching network of a power regulation circuit, wherein the switching network comprises a first pair of switches and a second pair of switches arranged in parallel with each other, and the switching network has a power output related to a voltage across a first node between the first pair of switches and a second node between the second pair of switches; the method comprising: receiving first signals indicative of power characteristics of an AC power circuit connected with the power regulation circuit and second signals indicative of power characteristics of a DC power circuit connected with the power regulation circuit, the first signals comprising a first current signal indicative of a current in the AC power circuit and a first voltage signal indicative of a voltage across the AC power circuit, and the second signals comprising a second current signal indicative of a current in the DC power circuit and a second voltage signal indicative of a voltage across the DC power circuit; determining, based on the first and second signals received and a reference current signal indicative of a reference current for the AC power circuit, a required power output of the switching network for regulating power transfer between the AC power circuit and the DC power circuit, wherein the required power output of the switching network is determined based on a ratio G defined by a required per-switching-period-mean voltage across the first and second nodes to a voltage across the DC power circuit, where −1≤G≤1, and wherein the determination includes comparing the first current signal indicative of the current in the AC power circuit with the reference current signal; selecting, dynamically, a switching scheme from a plurality of predetermined switching schemes based on the ratio G, wherein each of the predetermined switching schemes represent a unique switching scheme having a unique combination of switching patterns of the first and second pairs of switches per switching period T for controlling switching of the first and second pairs of switches, and wherein for each of the respective predetermined switching schemes the duty cycles of the first and second pairs of switches are changeable based on the ratio G; and generating, based on the dynamically selected switching scheme, output signals for controlling switching of respective switches of the switching network to regulate the voltage across the first and second nodes so as to regulate power transfer between the AC power circuit and the DC power circuit.

19. The system of claim 18, wherein the plurality of predetermined switching schemes comprises two or more of the following: a first switching scheme arranged to control the first and second pairs of switches such that the power output of the switching network is a first voltage value during 0 to ta1 and ta2, to T for each switching period T, where ta1 and ta2 represent time instances in the switching period T, and 0<ta1<ta2<T; a second switching scheme arranged to control the first and second pairs of switches such that the power output of the switching network is the first voltage value during tb1 to tb2 and tb3 to tb4 for each switching period T, where tb1, tb2, tb3, and tb4 represent time instances in the switching period T, and 0<tb1<tb2<tb3<tb4<T; a third switching scheme arranged to control the first and second pairs of switches such that the power output of the switching network is a second voltage value during 0 to tc1 and tc2 to T for each switching period T, where tc1 and tc2 represent time instances in the switching period T, and 0<tc1<tc2<T, and the second voltage value is an additive inverse of the first voltage value; a fourth switching scheme arranged to control the first and second pairs of switches such that the power output of the switching network is the second voltage value during td1 to td2 and td3 to td4 for each switching period T, where td1, td2, td3, and td4 represent time instances in the switching period T, and 0<td1<td2<tl3<td4<T; a fifth switching scheme arranged to control the first and second pairs of switches such that the power output of the switching network is the first voltage value during 0 to te1 and te2 to T and the second voltage value during te1 to te2 for each switching period T, where te1 and te2 represent time instances in the switching period T, and 0<te1<te2<T; and a sixth switching scheme arranged to control the first and second pairs of switches such that the power output of the switching network is the first voltage value during 0 to tf1 and tf4 to T and the second voltage value during tf2 to tf3 for each switching period T, where tf1, tf2, tf3, tf4 represent time instances in the switching period T, and 0<tf1<tf2<tf3<tf4<T; wherein all of the predetermined switching schemes have the same switching period T.

20. The method of claim 19, wherein the power output of the switching network is symmetric about T/2 for each switching period T, for all predetermined switching schemes.

21. The method of claim 19, further comprising: selecting the first switching scheme when it is determined that ⅓<G≤1; selecting the third switching scheme when it is determined that −1≤G<−⅓; selecting one of the following: the second switching scheme when it is determined that 0≤G<⅓ and the fourth switching scheme when it is determined that −⅓<G≤0; the fifth switching scheme when it is determined that −⅓≤G≤⅓; and the sixth switching scheme when it is determined that −⅓≤G≤⅓.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

(1) Embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings in which:

(2) FIG. 1 is a block diagram showing general construction of a power electronics system with a power regulation circuit in accordance with one embodiment of the invention;

(3) FIG. 2 is a schematic diagram showing a power electronics system with a power regulation circuit in accordance with one embodiment of the invention;

(4) FIG. 3A is a first switching scheme that can be used by the power regulation circuit for controlling power transfer in accordance with one embodiment of the invention;

(5) FIG. 3B is a second switching scheme that can be used by the power regulation circuit for controlling power transfer in accordance with one embodiment of the invention;

(6) FIG. 3C is a third switching scheme that can be used by the power regulation circuit for controlling power transfer in accordance with one embodiment of the invention;

(7) FIG. 3D is a fourth switching scheme that can be used by the power regulation circuit for controlling power transfer in accordance with one embodiment of the invention;

(8) FIG. 3E is a fifth switching scheme that can be used by the power regulation circuit for controlling power transfer in accordance with one embodiment of the invention;

(9) FIG. 3F is a sixth switching scheme that can be used by the power regulation circuit for controlling power transfer in accordance with one embodiment of the invention;

(10) FIG. 4 is a graph showing a relationship between duty cycle of the switches and a ratio (G) of the required per-switching-period-mean of the switching network output v.sub.AB with respect to the DC-link voltage V.sub.dc for the switching schemes in FIGS. 3A-3F;

(11) FIG. 5A is a plot showing a switching network output v.sub.AB produced by one embodiment of the first switching scheme of FIG. 3A;

(12) FIG. 5B is a plot showing a switching network output v.sub.AB produced by one embodiment of the second switching scheme of FIG. 3B;

(13) FIG. 5C is a plot showing a switching network output v.sub.AB produced by one embodiment of the third switching scheme of FIG. 3C;

(14) FIG. 5D is a plot showing a switching network output v.sub.AB produced by one embodiment of the fourth switching scheme of FIG. 3D;

(15) FIG. 5E is a plot showing a switching network output v.sub.AB produced by one embodiment of the fifth switching scheme of FIG. 3E;

(16) FIG. 5F is a plot showing a switching network output v.sub.AB produced by one embodiment of the sixth switching scheme of FIG. 3F;

(17) FIG. 6A is a plot showing measured waveforms of v.sub.dc, v.sub.ac, and i.sub.ac at the full-load condition when tested with a power regulation circuit prototype built according to FIG. 2 using the first and third switching schemes (time base: 10 ms/div);

(18) FIG. 6B is a plot showing the measured waveforms of v.sub.ac, v.sub.ac, and i.sub.ac at the full-load condition when tested with a power regulation circuit prototype built according to FIG. 2 using the first and third switching schemes as well as the fifth switching scheme during zero-crossing (time base: 10 ms/div);

(19) FIG. 6C is a plot showing the measured waveforms of v.sub.ac, v.sub.ac, and i.sub.ac at the full-load condition when tested with a power regulation circuit prototype built according to FIG. 2 using the first and third switching schemes as well as the second and fourth switching schemes during zero-crossing (time base: 10 ms/div);

(20) FIG. 7 is a graph showing current total harmonic distortion versus output power for the three measurements in FIGS. 6A-6C;

(21) FIG. 8A is a plot showing a switching network output v.sub.AB obtained using the first, third, and fifth switching schemes, where the pulses are aligned at the beginning of each switching period T (“left-aligned”);

(22) FIG. 8B is a plot showing a switching network output v.sub.AB obtained using the first, third, and fifth switching schemes, where the pulses are aligned at T/2 of each switching period T (“center-aligned”);

(23) FIG. 8C is a plot showing a switching network output v.sub.AB obtained using the first, third, and fifth switching schemes, where the pulses are aligned at the end of each switching period T (“right-aligned”);

(24) FIG. 9A is a plot showing the measured waveforms of the measured waveforms of v.sub.dc, v.sub.ac, and i.sub.ac for the “left-aligned” scheme in FIG. 8A;

(25) FIG. 9B is a plot showing the measured waveforms of the measured waveforms of v.sub.dc, v.sub.ac, and i.sub.ac for the “center-aligned” scheme in FIG. 8B;

(26) FIG. 9C is a plot showing the measured waveforms of the measured waveforms of v.sub.dc, v.sub.ac, and i.sub.ac for the “right-aligned” scheme in FIG. 8C; and

(27) FIG. 10 is a graph showing current total harmonic distortion versus output power for the three measurements in FIGS. 9A-9C.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

(28) FIG. 1 shows a simplified power electronics system 100 with a power regulation circuit 106 in accordance with one embodiment of the invention. The power electronics system 100 includes a first power circuit 102, a second power circuit 104, and a power regulation circuit 106 arranged between the first and second power circuits 102, 104. The power regulation circuit 106 is coupled with the first circuit 102 via a first power transfer link 108 that is preferably a bi-directional link, and is coupled with the second circuit 104 via a second power transfer link 110 that is preferably a bi-directional link. The first power circuit 102 is preferably an AC power network, but may also be a DC power network. The second power circuit 104 is preferably a DC power network, but may also be an AC power network. Each of the first and second power circuits 102, 104 may include one or more power sources or loads connected therewith.

(29) The power regulation circuit 106 comprises a switching network 112 with switches, and one or more controllers 114 for controlling operation of the switches in the switching network 112. The one or more controllers comprise circuits and/or electronic elements that can provide processing function. For example, a controller may be a controller, a control circuit, a logic circuit, a microcontroller, a MCU, a CPU, etc., or any combination thereof. By controlling the operation of the switches in the switching network 112, the power output of the power regulation circuit 106 can be controlled to regulate power transfer between the first power circuit 102 and the second power circuit 104. The power regulation circuit 106 also includes a memory module 116 for storing switching schemes for the switches. The memory module 116 may be integrated with the controller(s) 114 as shown, or in some cases, be a separate module operably connected with the controller(s) 114.

(30) The controller(s) 114 is arranged to receive signals indicative of power characteristics of the first power circuit 102 and signals indicative of power characteristics of the second power circuit 104 through links 120, 122. In one example, these signals may include signals indicative of: a current at the input or output in the first power circuit 102, a voltage across the input or output of the first power circuit 102, a current at the input or output in the second power circuit 104, and a voltage across the input or output of the second power circuit 104. With the received signals, the controller(s) 114 then determine, based on one or more reference signals 118, a required power output of the switching network 112 for properly regulating power transfer between the two circuits 102, 104. In one example, the reference signals 118 may be a reference current signal, a reference voltage signal, or the like. The reference signal 118 may be generated by the controller(s) 114, or may be received from an external source. The reference signal 118 may be fixed or adjustable. Upon determining the required power output, the controller(s) 114 then select, dynamically, a switching scheme from various predetermined switching schemes stored in the memory 116. In the invention, each of the predetermined switching schemes represents a unique switching scheme for controlling switching of respective switches of the switching network 112, and preferably each scheme is more useful than others in different operation regimes. After selecting a switching scheme, the controller(s) 114 then generate, based on the dynamically selected switching scheme, output signals for controlling switching of respective switches of the switching network 112. The output signals are provided to the switches for controlling switching and hence to regulate power transfer between the two circuits 102, 104.

(31) FIG. 2 shows a power electronics system 200 with a power regulation circuit 206 in accordance with one embodiment of the invention. As shown, the power electronics system 200 is formed by an AC power network 202, a DC power network 204, and a power regulation circuit 206 in the form of an AC-DC converter for regulating power transfer between the two networks 202, 204. In the present embodiment, the power regulation circuit 206 includes a power conversion stage and a controller and modulator. The power conversion stage includes a switching network 212, an inductor L, and a capacitor C. The switching network 212 includes a first pair of switches S.sub.1, S.sub.4 and a second pair of switches S.sub.2, S.sub.3 arranged in parallel with each other. The switches S.sub.1 to S.sub.4 are preferably semiconductor switches such as MOSFETs. As shown in FIG. 2, the switching network 212 is connected, on one side, to the AC power network 202 through two power bus/lines connecting with node A between the first pair of switches S.sub.1, S.sub.4 and node B between the second pair of switches S.sub.2, S.sub.3. In this example, the inductor L is provided on the bus connected with node A, but in some other cases, the inductor L may be provided on the bus connected with node B. In this embodiment, the inductor L serves as a filter to reduce the ripple on the AC-side current i.sub.ac. The switching network 212 is connected, on the other side, to the DC power network through a parallel capacitor C connected across (parallel with) the first pair of switches S.sub.1, S.sub.4 and the second pair of switches S.sub.2, S.sub.3. In this embodiment, the capacitor C serves as another filter to stabilize and reduce the ripple on the DC-side voltage v.sub.dc.

(32) In operation, the switches S.sub.1 to S.sub.4 are switched at a frequency much higher than the frequency of the AC power network 202, so that the waveform of the inductor current i.sub.L, which is also the AC-side current i.sub.ac, can be profiled in a predefined waveform with respect to the AC-side voltage v.sub.ac. Advantageously, such high-frequency switching can reduce the physical size of the inductor L.

(33) In one example, the power regulation circuit 206 is operated as a power factor corrector, in which the AC-side current i.sub.ac is controlled to be in phase with and in the same wave shape as the AC-side voltage v.sub.ac. In another example, the power regulation circuit 206 is operated as a grid-tie inverter to deliver sinusoidal current to the AC power network.

(34) In the present embodiment, the controller 214 of the power regulation circuit 206 is used to profile the waveform of i.sub.ac. In particular, the controller 214 senses the inductor current i.sub.L (which is the same as i.sub.ac) and compares it with a current reference i.sub.ref to determine an error i.sub.e. The error i.sub.e, together with the AC-side voltage v.sub.ac, DC-side voltage v.sub.dc and DC-side current i.sub.dc, are processed by the controller 214. The current reference i.sub.ref may be received from an external source (not shown) or may be generated by the controller 214 internally. The current reference i.sub.ref may be adjustable. The controller 214, after processing the received current and voltage signals, generates a modulating signal v.sub.m to the modulator 216. The modulating signal v.sub.m relates to a required voltage output across nodes A and B of the switching network for regulating power transfer between two power networks 202, 204. The modulating signal v.sub.m is preferably slow-varying as the main function of the controller 214 is to compare the low-frequency components of i.sub.ref and i.sub.L and/or to regulate the DC-side voltage v.sub.dc.

(35) Preferably, the modulator 216 is a PWM modulator, and it includes a switching scheme (pattern) storage 220 for storing multiple predetermined switching schemes (patterns) for controlling the switches S.sub.1 to S.sub.4, and a switching scheme (pattern) selector 218 for selecting a suitable switching scheme based on the modulating signal v.sub.m. The modulator 216 is arranged to dynamically select a switching scheme from the predetermined switching schemes in the pattern storage 220 based on the received modulating signal v.sub.m. The modulator 216, along with drivers 222 for the respective switches S.sub.1 to S.sub.4, then generate and transmit gating signals to the respective switches S.sub.1 to S.sub.4 The output voltage v.sub.AB across nodes A and B can then be regulated to control power transfer between the two power networks 202, 204. The dynamic selection of the switching schemes allow the power regulation circuit 206 to readily respond to changes in power transfer condition between the two networks by changing switching schemes on demand.

(36) FIGS. 3A-3F show six different switching schemes that may be used in the controller(s) of FIG. 1 and the modulator in FIG. 2. Preferably, all six switching schemes have the same switching period is T. Preferably, for all switching schemes, the switches S.sub.1 to S.sub.4 have at most two switching actions (switch-on is one action, switch-off is one action) within one switching period. The maximum switching frequency of the switches S.sub.1 to S.sub.4 in all six schemes is preferably the same.

(37) In the first switching scheme (I) shown in FIG. 3A, the switches are controlled such that, in each period T, S.sub.1 is switched on during 0 to t.sub.a1 and t.sub.a2 to T; S.sub.2 is always off; S.sub.3 is always on; S.sub.4 is switched on during t.sub.a1 to t.sub.a2, where 0<t.sub.a1<t.sub.a2<T. The resulting voltage v.sub.AB produced has a value V.sub.dc during 0 to t.sub.a1 and t.sub.a2 to T, and is 0 otherwise, in the same period T.

(38) In the second switching scheme (II) shown in FIG. 3B, the switches are controlled such that, in each period T, S.sub.1 is switched on during 0 to t.sub.b2 and t.sub.b3 to T; S.sub.2 is switched on during 0 to t.sub.b1 and t.sub.b4 to T; S.sub.3 is switched on during t.sub.b1 to t.sub.b4; S.sub.4 is switched on during t.sub.b2 to t.sub.b3, where 0<t.sub.b1<t.sub.b2<t.sub.b3<t.sub.b4<T. The resulting voltage v.sub.AB produced has a value V.sub.dc during t.sub.b1 to t.sub.b2 and t.sub.b3 to t.sub.b4, and is 0 otherwise, in the same period T.

(39) In the third switching scheme (III) shown in FIG. 3C, the switches are controlled such that, in each period T, S.sub.1 is switched on during t.sub.c1 to t.sub.c2; S.sub.2 is always on; S.sub.3 is always off; S.sub.4 is switched on during 0 to t.sub.c1 and t.sub.c2 to T, where 0<t.sub.c1<t.sub.c2<T. The resulting voltage v.sub.AB produced has a value −V.sub.dc during 0 to t.sub.c1 and t.sub.c2 to T, and is 0 otherwise, in the same period T.

(40) In the fourth switching scheme (IV) shown in FIG. 3D, the switches are controlled such that, in each period T, S.sub.1 is switched on during 0 to t.sub.d1 and t.sub.d4 to T; S.sub.2 is switched on during 0 to t.sub.d2 and t.sub.d3 to T; S.sub.3 is switched on during t.sub.2 to t.sub.3; S.sub.4 is switched on during t.sub.d1 to t.sub.d4, where 0<t.sub.d1<t.sub.d2<t.sub.d3<t.sub.d4<T. The resulting voltage v.sub.AB produced has a value −V.sub.dc during t.sub.d1 to t.sub.d2 and t.sub.d3 to t.sub.d4, and is 0 otherwise, in the same period T.

(41) In the fifth switching scheme (V) shown in FIG. 3E, the switches are controlled such that, in each period T, S.sub.1 and S.sub.3 are switched on during 0 to t.sub.e1 and t.sub.e2 to T; S.sub.2 and S.sub.4 are switched on during t.sub.e1 to t.sub.e2, where 0<t.sub.e1<t.sub.e2<T. The resulting voltage v.sub.AB produced has a value V.sub.dc during 0 to te.sub.1 and te.sub.2 to T and a value −V.sub.dc during t.sub.e1 to t.sub.e2, in the same period T.

(42) In the sixth switching scheme (VI) shown in FIG. 3F, the switches are controlled such that, in each period T, S.sub.1 is switched on during 0 to t.sub.f2 and t.sub.f4 to T; S.sub.2 is switched on during t.sub.f1 to t.sub.f3; S.sub.3 is switched on during 0 to t.sub.f1 and t.sub.f3 to T; S.sub.4 is switched on during t.sub.f2 to t.sub.f4, where 0<t.sub.f1<t.sub.f2<t.sub.f3<t.sub.f4<T. The resulting voltage v.sub.AB produced has a value V.sub.dc during 0 to t.sub.f1 and t.sub.f4 to T, −V.sub.dc during t.sub.f2 to t.sub.f3, and is 0 otherwise, in the same period T.

(43) The cycle mean of v.sub.AB, V.sub.AB, of each of the switching schemes in FIGS. 3A-3F is given in Table I.

(44) TABLE-US-00001 TABLE I Cycle Mean of ν.sub.AB of each pattern (switching scheme) Pattern V.sub.AB I (d.sub.I, 1 + d.sub.I, 2) V.sub.dc II (d.sub.II, 1 + d.sub.II, 2)V.sub.dc III −(d.sub.III, 1 + d.sub.III, 2) V.sub.dc IV −(d.sub.IV, 1 + d.sub.IV, 2) V.sub.dc V [2 (d.sub.V, 1 + d.sub.V, 2) − 1] V.sub.dc VI (d.sub.VI, 1, 1 + d.sub.VI, 1, 2 − d.sub.VI, 2) V.sub.dc

(45) Consider that the patterns have the same value of V.sub.AB for a given V.sub.dc. That is,

(46) $\begin{array}{cc}\frac{{\stackrel{\_}{V}}_{\mathrm{AB}}}{V_{\mathrm{dc}}}=G\mathrm{If}G\ge o,& \left(1\right)\\ d_{I,1}+d_{I,2}=G& \left(2\right)\\ d_{\mathrm{II},1}+d_{\mathrm{II},2}=G& \left(3\right)\\ d_{V,1}+d_{V,2}=\frac{1}{2}\left(1+G\right)& \left(4\right)\\ d_{\mathrm{VI},1,1}+d_{\mathrm{VI},1,2}-d_{\mathrm{VI},2}=G& \left(5\right)\end{array}$

(47) As shown above, patterns III and IV cannot give positive value of G. Conversely, if G≤0, patterns I and II cannot give a negative value of G. Equations (4) and (5) still hold. Moreover,
d.sub.III,1+d.sub.III,2=−G  (6)
d.sub.IV,1+d.sub.IV,2=−G  (7)

(48) The duty cycle of the switches of each pattern are shown in Table II.

(49) TABLE-US-00002 TABLE II Duty Cycle of the Switches Pattern S.sub.1 S.sub.2 S.sub.3 S.sub.4 I* d.sub.I,1 + d.sub.I,2 0 1 1 − d.sub.I,1 − d.sub.I,2 II* $\frac{1}{2}\left(1+d_{\mathrm{II},1}+d_{\mathrm{II},2}\right)$ $\frac{1}{2}\left(1-d_{\mathrm{II},1}-d_{\mathrm{II},2}\right)$ $\frac{1}{2}\left(1+d_{\mathrm{II},1}+d_{\mathrm{II},2}\right)$ $\frac{1}{2}\left(1-d_{\mathrm{II},1}-d_{\mathrm{II},2}\right)$ III** 1 − d.sub.III,1 − d.sub.III,2 1 0 d.sub.III,1 + d.sub.III,2 IV** $\frac{1}{2}\left(1-d_{\mathrm{IV},1}-d_{\mathrm{IV},2}\right)$ $\frac{1}{2}\left(1+d_{\mathrm{IV},1}+d_{\mathrm{IV},2}\right)$ $\frac{1}{2}\left(1-d_{\mathrm{IV},1}-d_{\mathrm{IV},2}\right)$ $\frac{1}{2}\left(1+d_{\mathrm{IV},1}+d_{\mathrm{IV},2}\right)$ V d.sub.V,1 + d.sub.V,2 1 − d.sub.V,1 − d.sub.V,2 d.sub.V,1 + d.sub.V,2 1 − d.sub.V,1 − d.sub.V,2 VI 0$\frac{1}{2}\left(1+d_{\mathrm{VI},1,1}+d_{\mathrm{VI},1,2}-d_{\mathrm{VI},2}\right)$ $\frac{1}{2}\left(1-d_{\mathrm{VI},1,1}-d_{\mathrm{VI},1,2}+d_{\mathrm{VI},2}\right)$ $\frac{1}{2}\left(1+d_{\mathrm{VI},1,1}+d_{\mathrm{VI},1,2}-d_{\mathrm{VI},2}\right)$ $\frac{1}{2}\left(1-d_{\mathrm{VI},1,1}-d_{\mathrm{VI},1,2}+d_{\mathrm{VI},2}\right)$ *G ≥ 0; **G ≤ 0

(50) By substituting the above with equations (2)-(7), the duty cycle of the switches can be expressed in terms of G. Table III shows the duty cycles of the switches in various patterns.

(51) TABLE-US-00003 TABLE III Duty Cycle of the Switches in terms of G Pattern S.sub.1 S.sub.2 S.sub.3 S.sub.4 I* G 0 1 1 − G II* $\frac{1}{2}\left(1+G\right)$ $\frac{1}{2}\left(1-G\right)$ $\frac{1}{2}\left(1+G\right)$ $\frac{1}{2}\left(1-G\right)$ III** 1 + G 1 0 −G IV** $\frac{1}{2}\left(1+G\right)$ $\frac{1}{2}\left(1-G\right)$ 0$\frac{1}{2}\left(1+G\right)$ $\frac{1}{2}\left(1-G\right)$ V $\frac{1}{2}\left(1+G\right)$ $\frac{1}{2}\left(1-G\right)$ $\frac{1}{2}\left(1+G\right)$ $\frac{1}{2}\left(1-G\right)$ VI $\frac{1}{2}\left(1+G\right)$ $\frac{1}{2}\left(1-G\right)$ $\frac{1}{2}\left(1+G\right)$ $\frac{1}{2}\left(1-G\right)$ *G ≥ 0; **G ≤ 0

(52) FIG. 4 shows the duty cycle of the switches S.sub.1 to S.sub.4 versus G. The switches without switching in the patterns are not shown. Based on FIG. 4, it can be determined that 1) Patterns I and II only give a positive value of G while patterns III and IV only give a negative value of G. 2) The effective frequency of patterns II and IV is doubled and the two pulses in a switching period must be symmetrical about T/2. 3) Patterns I and III only require two high-frequency-switched devices, while the rest m require four high-frequency-switched devices. Thus, patterns I and III have better conversion efficiency. 4) In patterns I and III, the duty cycle of the switches is either very large or very small for small magnitude of G. If switches are commanded to switch at very small or very large duty cycle, they might not be able to respond accordingly. Thus, some short pulses might be dropped (namely “pulse-dropping”), causing harmonic distortion. As labelled in FIG. 4, the duty cycle of the switches are preferred to be operated between the minimum and maximum duty cycles. 5) Patterns I and III require introducing dead time to ensure that the polarity of v.sub.AB must be changed in synchronization with the AC-side voltage. Conversely, patterns II, IV-VI allow a slightly difference between the polarity of v.sub.AB and the AC-side voltage. Thus, no dead time is needed. 6) In patterns I-IV, the rate of change of the input inductor current at zero crossings is slow because of low grid voltage. Thus, the grid current is unable to follow the wave shape of the grid voltage, causing zero-crossing distortion. Such phenomenon is particularly obvious if the impedance of the AC power network is high, for example, under weak grid condition. Conversely, patterns V and VI can provide necessary voltage across the inductor. Thus, zero-crossing distortion can be avoided. 7) For −⅓<G<⅓, the duty cycles of the switches in patterns II, IV, V, and VI are less different than that in patterns I and III. 8) For G<−⅓ or G>⅓, the duty cycles of the switches in patterns I and III are less different than that in patterns II, IV, V, and VI.
The merits and limitations of each pattern/scheme are summarized in Table IV.

(53) TABLE-US-00004 TABLE IV Comparison of different patterns Pattern Merits Limitations I For G > ⅓, 1 ≥ G ≥ 0 smaller difference in For G < ⅓, larger difference in switches' duty cycles switches' duty cycles Two devices Zero-crossing dead time required for in high-frequency synchronizing the polarity of υ.sub.AB switching with the AC power network II Effective 1 ≥ G ≥ 0 frequency doubled For G > ⅓, larger difference in For G < ⅓, switches' duty cycles smaller difference in Zero-crossing distortion caused by switches' duty cycles low grid voltage Four devices in high-frequency switching III For G < −⅓, −1 ≤ G ≤ 0 smaller difference in For G > −⅓, larger difference in switches' duty cycles switches duty cycles Two devices Zero-crossing dead time required for in high-frequency synchronizing the polarity of υ.sub.AB switching with the AC power network IV Effective −1 ≤ G ≤ 0 frequency doubled For G < −⅓, larger difference in For G > −⅓, switches' duty cycles smaller difference in Zero-crossing distortion caused by switches' duty cycles low grid voltage Four devices in high-frequency switching V 1 ≥ G ≥ −1 For G < −⅓ or G > ⅓, larger For ⅓ ≥ G ≥ −⅓, difference in switches' duty cycles smaller difference in Two switches state changes switches' duty cycles simultaneously No zero-crossing Four devices in high-frequency dead time required switching VI 1 ≥ G ≥ −1 For G < −⅓ or G > ⅓, larger For ⅓ ≥ G ≥ −⅓, difference in switches' duty cycles smaller difference in Maximum voltage limited by the switches' duty cycles presence of the zero state No zero-crossing Four devices in high-frequency dead time required switching One switch state change

(54) In operation, the controller 114 or modulator 216 may use any of the switching schemes described, or their variation which can provide the same v.sub.AB profile. To avoid the occurrence of “pulse dropping” with small G (due to small duty cycles), patterns II, IV, V, and VI can be used. Alternatively, if the grid impedance is large, patterns V and VI are preferred to reduce zero-crossing distortion. If G is positive and large, patterns I can be used; if G is negative and its absolute value is large, patterns III can be used. It is because patterns I and III give a higher efficiency. In the present invention, instead of using only one pattern, the controller or modulator is arranged to change the switching scheme adaptively by selecting from various predetermined switching schemes. As discussed, the switching scheme is selected by considering the ratio G of the required cycle mean of the bridge output with respect to the DC-link voltage V.sub.dc.

(55) Since the output modulation signal of the controller 214 in FIG. 2 is slow varying and the frequency of the AC-side voltage is low compared to the switching frequency, the cycle mean of the voltage applied to the inductor L, before and after switching to another switching scheme, is also slow varying. However, in some applications, the cycle mean variation of the inductor current i.sub.L may be affected by the modulation technique.

(56) In order to minimize the cycle mean current variation after switching to another switching scheme, the voltage v.sub.AB patterns are preferably made symmetrical about T/2. That is, the output voltage v.sub.AB of the switching network is preferably “center-aligned” in one switching period T. FIGS. 5A-5F show the voltage patterns v.sub.AB that give the same cycle mean voltage and minimum cycle mean inductor current variation for patterns I-VI of FIGS. 3A-3F, respectively. For example, the pattern in FIG. 5A is the preferred waveform for the pattern in FIG. 3A, that is, the pulse pattern is center-aligned. Both patterns in FIGS. 3A and 5A give the same cycle mean voltage, but FIG. 5A gives the minimum inductor current deviation in a cycle. It should be noted that the PWM switching pulses of the switches need not be “center-aligned” to produce an output voltage v.sub.AB that is “center-aligned” in one switching period T.

(57) Experimental Results

(58) To verify the performance of the adaptive schemes, a 1 kW prototype with the schematic shown in FIG. 2 has been built. The root-mean-square (RMS) value of the input voltage and frequency of v.sub.ac are 230V and 50 Hz, respectively. The output voltage v.sub.dc is 400V. In the experiment, the prototype works as totem-pole power factor corrector (PFC) which provides power factor correction and draw power from the AC power network. The switching frequency of the switches is 45 kHz and the switching actions are determined by the controller and PWM modulator.

(59) FIG. 6A is a plot showing measured waveforms of v.sub.dc, v.sub.ac, and i.sub.ac at the full-load condition when tested with the power regulation circuit prototype built according to FIG. 2 using the first and third switching schemes (time base: 10 ms/div). In the test, pattern I was used for the positive half cycle and pattern III was used for the negative half cycle. It can be observed that when the value of G is very small (i.e., near zero-crossings of the AC-side voltage), pulse dropping appears. It can also be observed that i.sub.ac has zero-crossing distortion.

(60) FIG. 6B is a plot showing the measured waveforms of v.sub.dc, v.sub.ac, and i.sub.ac at the full-load condition when tested with the power regulation circuit prototype built according to FIG. 2 using the first and third switching schemes as well as the fifth switching scheme during zero-crossing (time base: 10 ms/div). In this test, pattern V is introduced during the zero-crossings, while patterns I and III are used for the remaining positive and negative half cycles. It can be seen that the zero-crossing distortion is reduced compared with FIG. 6A.

(61) FIG. 6C is a plot showing the measured waveforms of v.sub.dc, v.sub.ac, and i.sub.ac at the full-load condition when tested with the power regulation circuit prototype built according to FIG. 2 using the first and third switching schemes as well as the second and fourth switching schemes during zero-crossing (time base: 10 ms/div). In this test, patterns II and IV are introduced during the zero-crossings, while patterns I and III are used for the remaining positive and negative half cycles. It can be seen that the zero-crossing distortion is further reduced compared with FIGS. 6A and 6B.

(62) FIG. 7 shows a comparison of the current total harmonic distortion (THDi) versus output power for the tests of FIGS. 6A-6C. As shown, there is a significant reduction of the THDi for the arrangement in FIGS. 6B and 6C.

(63) FIGS. 8A-8C show the network output v.sub.AB obtained using the first, third, and fifth switching schemes, where the pulses are aligned differently. More specifically, FIG. 8A shows the voltage pattern of v.sub.AB with the pulses aligned at the beginning of switching cycles (that is “left-aligned”); and FIG. 9A shows the corresponding measured waveforms of v.sub.dc, v.sub.ac, and i.sub.ac. FIG. 8B shows the voltage pattern of v.sub.AB with the pulses center-aligned in every switching cycle (that is “center-aligned”); and FIG. 9B shows the corresponding measured waveforms of v.sub.dc, v.sub.ac, and i.sub.ac. FIG. 8C shows the voltage pattern of v.sub.AB with the pulses aligned at the end of switching cycles (that is “left-aligned”); and FIG. 9C shows the corresponding measured waveforms of v.sub.dc, v.sub.ac, and i.sub.ac. It is clear that the symmetric and center-aligned arrangement gives improved performance.

(64) FIG. 10 shows a comparison of the current total harmonic distortion (THDi) of i.sub.ac versus output power for the tests of FIGS. 8A-8C. It can once again be observed that the center-aligned pulses give improved performance.

(65) The embodiments of the power regulation system and method are advantageous in that different switching schemes each with their operational merits and limitations are provided for dynamic adjustment of the switching scheme. In particular, the PWM scheme is dynamically switched to an appropriate one, so that the performance of the entire system is maximized. In preferred embodiments, the pulses generated by the controller or modulator of the invention are center-aligned, thereby effectively minimizing changes in the circuit dynamics during the scheme switching.

(66) Although not required, the embodiments described with reference to the Figures can be implemented as an application programming interface (API) or as a series of libraries for use by a developer or can be included within another software application, such as a terminal or personal computer operating system or a portable computing device operating system. Generally, as program modules include routines, programs, objects, components and data files assisting in the performance of particular functions, the skilled person will understand that the functionality of the software application may be distributed across a number of routines, objects or components to achieve the same functionality desired herein. The controller in the above embodiment may be implemented using a control circuit, a logic circuit, a microcontroller, a controller, a MCU, a CPU, etc., or any combination thereof.

(67) It will also be appreciated that where the methods and systems of the invention are either wholly implemented by computing system or partly implemented by computing systems then any appropriate computing system architecture may be utilized. This will include stand-alone computers, network computers and dedicated hardware devices. Where the terms “computing system” and “computing device” are used, these terms are intended to cover any appropriate arrangement of computer hardware capable of implementing the function described.

(68) It will be appreciated by persons skilled in the art that numerous variations and/or modifications may be made to the invention as shown in the specific embodiments without departing from the spirit or scope of the invention as broadly described. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive.

(69) Any reference to prior art contained herein is not to be taken as an admission that the information is common general knowledge, unless otherwise indicated.