Devices and methods for generating a broadband frequency signal

Abstract

An example of a device for generating a broadband frequency signal comprises a first controlled oscillator, a second controlled oscillator, a phase-locked loop for feeding back an output signal of a controlled oscillator to the corresponding controlled oscillator, and a mixer. The mixer is configured to generate the broadband frequency signal by mixing an output signal of the first controlled oscillator and an output signal of the second controlled oscillator. The device may, for example, be realized by means of a single phase-locked loop. A further example relates to a device for generating a frequency signal with a controlled oscillator and a phase-locked loop with a further controlled oscillator and a mixer in the feedback path of the phase-locked loop. Examples further relate to a high-frequency device for emitting a high-frequency signal and a method for generating a broadband frequency signal.

Claims

1. A device for generating a broadband frequency signal, the device comprising: a first controlled oscillator; a second controlled oscillator; a phase-locked loop for feeding back a signal of the device based on an output signal of one of the controlled oscillators to both the first controlled oscillator and the second controlled oscillator; and a mixer, which is configured to generate the broadband frequency signal by mixing an output signal of the first controlled oscillator and an output signal of the second controlled oscillator, wherein the first and second controlled oscillators are configured to cause a frequency change in the opposite direction upon a change of an input voltage; or wherein the first and second controlled oscillators are configured to cause a frequency change in the same direction upon a change of an input voltage, and a signal processing unit, which inverts a control signal of the oscillator, is arranged at the input of one of the two controlled oscillators.

2. The device of claim 1, further comprising a reference signal source associated with both the first and second controlled oscillators.

3. The device of claim 1, wherein the output of the mixer is coupled to the phase-locked loop for feeding back the broadband frequency signal both the first controlled oscillator and to the second controlled oscillator.

4. The device of claim 1, the phase-locked loop further comprising a separate loop filter per controlled oscillator.

5. The device of claim 1, wherein the phase-locked loop is configured to generate a differential tune voltage pair for the oscillators.

6. The device of claim 1, the phase-locked loop further comprising: a differential charge pump, wherein a positive output of the differential charge pump is coupled to the first controlled oscillator and a negative output of the differential charge pump to the second controlled oscillator.

7. The device of claim 1, the phase-locked loop further comprising an additional controlled oscillator and an additional mixer in the feedback path of the phase-locked loop, in order to increase a frequency of a feedback signal of the phase-locked loop by means of the additional controlled oscillator and the additional mixer.

8. The device of claim 1, wherein an upper cut-off frequency of the first controlled oscillator is greater than or equal to a lower cut-off frequency of the second controlled oscillator.

9. The device of claim 1, wherein an upper cut-off frequency of the first controlled oscillator is smaller than a lower cut-off frequency of the second controlled oscillator, wherein the frequency difference between the upper cut-off frequency of the first controlled oscillator and the lower cut-off frequency of the second controlled oscillator corresponds to a lower cut-off frequency of the broadband frequency signal.

10. The device of claim 1, wherein a bandwidth of the generated frequency signal corresponds to the sum of respective bandwidths of the signals of the first controlled oscillator and the second controlled oscillator.

11. The device of claim 1, wherein the frequency signal, which can be generated, comprises a bandwidth of at least 10 GHz.

12. The device of claim 1, wherein the frequency signal, which can be generated, comprises a relative bandwidth of more than 20%.

13. The device of claim 1, wherein a lower cut-off frequency of the output signals of the controlled oscillators is bigger than 1 GHz.

14. The device of claim 1, wherein the frequency signal, which can be generated, is a ramp signal, a monofrequency signal and/or a signal with frequency shift keying or frequency hopping.

15. A high-frequency device for emitting a high-frequency signal, comprising a device according to claim 1.

16. A device for generating a frequency signal, the device comprising: at least one first controlled oscillator; and a phase-locked loop having a further controlled oscillator and an mixer in the feedback path of the phase-locked loop, in order to increase a frequency of a feedback signal of the phase-locked loop by means of the further controlled oscillator and the mixer.

17. The device of claim 16, further comprising: a second controlled oscillator; and a mixer, which is configured to generate the frequency signal by mixing an output signal of the first controlled oscillator and an output signal of the second controlled oscillator.

18. A method for generating a broadband frequency signal, the method comprising: operating a first controlled oscillator and a second controlled oscillator using at least one phase-locked loop with an adjustable divider for both the first controlled oscillator and the second controlled oscillator, wherein a ratio of a maximum divider value of the adjustable divider to a minimum divider value of the adjustable divider is less than 5; and mixing the output signals of the two controlled oscillators to produce the broadband frequency signal.

19. The method of claim 18, wherein a frequency ramp, a monofrequency signal and/or a signal with frequency shift keying or frequency hopping having a relative bandwidth of at least 20% is generated.

Description

BRIEF DESCRIPTION OF THE FIGURES

(1) Some examples of devices and/or methods will be described in the following by way of example only and with reference to the accompanying figures, in which:

(2) FIG. 1 shows a schematic illustration of a device with two controlled oscillators;

(3) FIG. 1a shows a schematic illustration of a device with two controlled oscillators and a common phase-locked loop;

(4) FIG. 2 shows a schematic illustration of a device with a controlled oscillator in a feedback path of a phase-locked loop;

(5) FIG. 3 shows a flowchart of exemplary methods for generating a broadband frequency signal;

(6) FIG. 4 shows a schematic illustration of a device with two controlled oscillators and respective phase-locked loops associated with the oscillators;

(7) FIG. 5 shows a schematic illustration of a device with two controlled oscillators and a common phase-locked loop;

(8) FIG. 6 shows a schematic illustration of a device with improved suppression of interference couplings;

(9) FIG. 7 shows a schematic illustration of a device with a differential charge pump device with improved suppression of interference couplings; and

(10) FIG. 8 shows a schematic illustration of a device with two controlled oscillators and a further controlled oscillator with a mixer in a feedback path of a common phase-locked loop of the two controlled oscillators.

DESCRIPTION

(11) Various examples will now be described more fully with reference to the accompanying figures in which some examples are illustrated. In the figures, the thicknesses of lines, layers and/or regions may be exaggerated for clarity.

(12) Accordingly, while further examples are capable of various modifications and alternative forms, some particular examples thereof are shown in the figures and will subsequently be described in detail. However, this detailed description does not limit further examples to the particular forms described. Further examples may cover all modifications, equivalents, and alternatives falling within the scope of the disclosure. Same or like numbers refer to like or similar elements throughout the description of the figures, which may be implemented identically or in modified form when compared to one another while providing for the same or a similar functionality.

(13) It will be understood that when an element is referred to as being “connected” or “coupled” to another element, the elements may be directly connected or coupled via one or more intervening elements. If two elements A and B are combined using an “or”, this is to be understood to disclose all possible combinations, i.e. only A, only B as well as A and B, if not explicitly or implicitly defined otherwise. An alternative wording for the same combinations is “at least one of A and B” or “A and/or B”. The same applies, mutatis mutandis, for combinations of more than two Elements.

(14) The terminology used herein for the purpose of describing particular examples is not intended to be limiting for further examples. Whenever a singular form such as “a,” “an,” and “the” is used and using only a single element is neither explicitly or implicitly defined as being mandatory, further examples may also use plural elements to implement the same functionality. Likewise, when a functionality is subsequently described as being implemented using multiple elements, further examples may implement the same functionality using a single element or processing entity. It will be further understood that the terms “comprises”, “comprising”, “includes” and/or “including,” when used, specify the presence of the stated features, integers, steps, operations, processes, elements, components and/or any group of the same, but do not preclude the presence or addition of one or more other features, integers, steps, operations, processes, elements, components and/or any group thereof.

(15) Unless otherwise defined, all terms (including technical and scientific terms) are used herein in their ordinary meaning of the art to which the examples belong.

(16) FIG. 1 shows a schematic illustration of a device 10 with two controlled oscillators 12, 13. The device 10 is configured to generate a broadband frequency signal 11 (e.g. an output signal f.sub.out). A phase-locked loop 14 of the device 10 is configured for feeding back a signal of the device 10, which is based on at least one output signal 15, 17 of one of the controlled oscillators 12, 13 to the corresponding controlled oscillator 12, 13. For example, the output signal 15 of the first controlled oscillator 12 is fed back to the input of the oscillator 12 via the phase-locked loop 14. For example, the device 10 comprises a further phase-locked loop 16, via which the output signal 17 of the second oscillator 13 is fed back. Alternatively, the broadband frequency signal 11 may be routed via the phase-locked loop 14 to both the input of the first oscillator 12 and the input of the second oscillator 13. The phase-locked loop 14 may illustrate a PLL circuit, e.g. including dividers, PFD, CP, reference signal, and/or loop filter etc.).

(17) Further, device 10 comprises a mixer 18, which is configured to generate the broadband frequency signal 11 by mixing the output signal 15 of the first controlled oscillator 12 and the output signal 17 of the second controlled oscillator 13. By mixing the two output signals 15, 17, the broadband frequency signal 11 with increased bandwidth may be generated, for example with a bandwidth corresponding to the sum of the bandwidths of the two output signals 15, 17.

(18) FIG. 1a shows a schematic illustration of a device 10a, also with two controlled oscillators 12, 13. The device 10a is also configured to generate a broadband frequency signal 11 (e.g. the output signal f.sub.out). A common phase-locked loop 14a of the device 10a is configured to feed back the broadband frequency signal 11 of the device 10a to both oscillators 12, 13.

(19) FIG. 2 shows a schematic illustration of a device 20 with a controlled oscillator 25 in a feedback path of a phase-locked loop 24 of the device 20. The device 20 is configured to generate a frequency signal 21 and comprises at least a first controlled oscillator 22 as well as a phase-locked loop 24 with the further controlled oscillator 25 and a mixer 26 in the feedback path of the phase-locked loop 24. Thus, a frequency of a feedback signal of the phase-locked loop 24 may be increased by means of the further controlled oscillator 25 and the mixer 26. For example, the fed back signal mixed upward to a higher frequency is passed on to a further frequency divider before a phase-frequency discriminator of the phase-locked loop 24.

(20) Increasing the frequency of the feedback signal enables, for example, a reduction of a relative frequency range of the signal received at the further frequency divider (e.g. with adjustable broken frequency ratio). That way, a ratio between a maximum and a minimum divider value of the further frequency divider may be reduced and thus, e.g., a variation of the loop gain of the phase-locked loop 24 may be reduced.

(21) Further details and aspects are described in connection with examples detailed further above or further below. The examples shown using FIG. 2 may comprise one or more optional additional features corresponding to one or more aspects described in connection with the proposed concept or one or more examples further above or further below (for example in connection with FIGS. 1 and 3-7, particularly in connection with FIG. 8).

(22) FIG. 3 shows a flowchart of a method 30 for generating a broadband frequency signal. Method 30 comprises operating 31 of a first controlled oscillator and a second controlled oscillator using a common phase-locked loop (e.g. operating and stabilizing 31a of the oscillators via a common phase-locked loop) and mixing 32 the output signals of the two controlled oscillators in order to generate the broadband frequency signal.

(23) Alternatively, a method is illustrated, which comprises operating and stabilizing 31b the oscillators via one phase-locked loop per oscillator. In the alternative method a mixing 32 of the output signals of the two controlled oscillators is also done, in order to generate the broadband output signal.

(24) Further details and aspects are described in connection with examples detailed further above or further below. The examples shown using FIG. 3 may comprise one or more optional additional features corresponding to one or more aspects described in connection with the proposed concept or one or more examples further above or further below (for example in connection with FIGS. 1, 2 and 4-8).

(25) FIG. 4 shows a schematic illustration of a device 40 with two controlled oscillators (here voltage-controlled oscillators, VCO) VCO-H, VCO-L and one phase-locked loop 44, 46 per oscillator VCO-H, VCO-L. For example, a frequency range of the one controlled oscillator VCO-H is higher than that of the other controlled oscillator VCO-L. A mixer 18 is configured to mix output signals f.sub.H, f.sub.L of the oscillators VCO-H, VCO-L to an output signal f.sub.out of the device 40.

(26) In the respective phase-locked loop 44, 46, a respective output signal f.sub.H, f.sub.L of the corresponding oscillators VCO-H, VCO-L is each divided by a first static frequency divider /N.sub.1, /N.sub.2 (integer divider) and an adjustable divider /K.sub.1, /K.sub.2 (fractional and/or integer divider) and compared with a reference signal f.sub.Ref of a reference signal source Ref, which is divided by respective dividers /R.sub.1, /R.sub.2 via a separate phase-frequency discriminator PFD each. A phase difference output by the PFD serves as the regulated variable and is converted into a regulated voltage, which sets the output frequency of the respective oscillator VCO-H, VCO-L such that the phase difference of the two input frequencies at the corresponding PFD is zero, by a charge pump (CP) and a loop filter F.sub.1(s), F.sub.2(s) each.

(27) For example, the high-frequency oscillators cover two adjacent frequency ranges (e.g. 80 GHz-100 GHz for VCO-L and 100 GHz-120 GHz for VCO-H) so that output signals having the combined bandwidth of both VCOs (e.g. from 0 Hz-40 GHz) may be generated behind the mixer.

(28) Further details and aspects are described in connection with examples detailed further above or further below. The examples shown using FIG. 4 may comprise one or more optional additional features corresponding to one or more aspects described in connection with the proposed concept or one or more examples further above or further below (for example in connection with FIGS. 1-3 and 5-8).

(29) FIG. 5 shows a schematic illustration of a device 50 with two controlled oscillators VCO-H, VCO-L and a common phase-locked loop 54. The phase-locked loop 54 comprises an integer divider /N and a fractional and/or integer adjustable divider /K via which the output signal f.sub.out of device 50 is routed to a common phase-frequency discriminator PFD. A reference signal f.sub.Ref of a reference signal source Ref is routed to the phase-frequency discriminator PFD via a divider /R. A phase difference output by the PFD serves as a regulated variable and is converted into a regulated voltage V.sub.tune via a common charge pump CP and a loop filter F(s).

(30) The regulated voltage V.sub.tune is used directly as input signal of the first voltage-controlled oscillator VCO-H. Further, an additional filter I(s) (e.g. inverting, e.g. subtraction amplifier) is intended, which processes and adapts the control signal or the regulated voltage V.sub.tune to the operating range of the second voltage-controlled oscillator in such a way that it passes through its entire operating range in the opposite direction to that of the first voltage-controlled oscillator. E.g. an output signal V.sub.offset−V.sub.tune of the additional filter I(s) is used as input signal of the second voltage-controlled oscillator VCO-L. Thus, for example, an increase of the regulated voltage V.sub.tune leads to a frequency increase of the signal f.sub.H of the first oscillator VCO-H and at the same time to a frequency reduction of the signal f.sub.L of the second oscillator VCO-L. That way, a broadband frequency signal f.sub.out may be generated with a common control signal.

(31) Thereby the circuit including both VCOs, I(s) and mixer performs e.g. like a single oscillator generating an output voltage f.sub.out from a control variable behind F(s). The signal f.sub.out divided down by the dividers /N and/K is compared with the reference frequency divided by the divider /R by the PLL 54 via the PFD, and the phase error via CP and F(s) is used to generate the control variable V.sub.tune.

(32) Further details and aspects are described in connection with examples detailed further above or further below. The examples shown using FIG. 5 may comprise one or more optional additional features corresponding to one or more aspects described in connection with the proposed concept or one or more examples further above or further below (for example in connection with FIGS. 1-4 and 6-8).

(33) FIG. 6 shows a schematic illustration of a device 50a with improved suppression of interference couplings. In contrast to the device 50 shown in FIG. 5, a phase-locked loop 54a of the device 50a comprises two separate loop filters F(s), I(s) which generate one control signal each for the oscillators from an output signal V.sub.CP of the charge pump CP. The signal V.sub.tune generated by the loop filter F(s) is used as input signal for the first oscillator VCO-H and the signal V.sub.offset-V.sub.tune generated by the loop filter I(s) is used as input signal for the second oscillator VCO-L.

(34) For example, signal lines of device 50a between the charge pump CP and the loop filters F(s), I(s) are kept very short in order to reduce the influence of interference couplings. The tune voltages behind the loop filters may be described as differential regulated signal pair, where interference couplings are reduced or eliminated by the mixing process of the the signals of the two VCOs.

(35) Further details and aspects are described in connection with examples detailed further above or further below. The examples shown using FIG. 6 may comprise one or more optional additional features corresponding to one or more aspects described in connection with the proposed concept or one or more examples further above or further below (for example in connection with FIGS. 1-5 and 7-8).

(36) FIG. 7 shows a schematic illustration of a device 50b with a phase-locked loop 54b with a differential charge pump CP.sub.D. The differential charge pump CP.sub.D is configured to generate differential output voltages. A first part CP+ of the differential charge pump CP.sub.D is configured to transmit a positive signal V.sub.CP− to the first loop filter F(s). A second part CP− of the differential charge pump CP.sub.D is configured to transmit a negative signal V.sub.CP− to the second loop filter I(s). This makes it possible to compensate more strongly for common mode interference couplings to the voltage signals V.sub.CP+ and V.sub.CP− or V.sub.tune, and V.sub.offset−V.sub.tune, using the mixing process in the mixer 18, due to the differential design of the device 50b.

(37) Further details and aspects are described in connection with examples detailed further above or further below. The examples shown using FIG. 7 may comprise one or more optional additional features corresponding to one or more aspects described in connection with the proposed concept or one or more examples further above or further below (for example in connection with FIGS. 1-6 and 8).

(38) FIG. 8 shows a schematic illustration of a device 50c with two controlled oscillators VCO-H, VCO-L and an additional voltage-controlled oscillator VCO-A as well as an additional mixer 26 in a feedback path of a common phase-locked loop 24 of the two controlled oscillators VCO-H, VCO-L.

(39) The broadening via the voltage-controlled oscillator VCO-A as well as the additional mixer 26 in device 50c allows for the output signal f.sub.out divided by the divider /N to be mixed upward with a frequency f.sub.A of the additional oscillator VCO-A. This may enable a reduction of a variation in loop gain, for example in order to enable the PLL 24 to be capable of stabilizing the maximum bandwidth of f.sub.out. As the divider /N is constant, the variation of the loop gain e.g. mainly depends on the transmission function of the oscillators VCO-H, VCO-L and on the adjustable divider /K. By upmixing the signal divided by divider /N with the frequency f.sub.A towards the upper frequency range, which the PLL 24 can process in normal operation at its input (before divider /K), the variation of the loop gain may be reduced via a smaller ratio of minimum value K.sub.min and maximum value K.sub.max of the divider /K.

(40) For example, for a device without an additional oscillator VCO-A with

(41) $\frac{f_{\mathrm{out}}}{N}=1\mathrm{.Math.}3\mathrm{GHz}\mathrm{and}\frac{f_{\mathrm{ref}}}{R}=100\mathrm{MHz}$
for minimum and maximum values K.sub.min, K.sub.max used at the adjustable divider,
the following would apply:

(42) $K_{\min }=\frac{1\mathrm{GHz}}{100\mathrm{MHz}}=10;K_{\max }=\frac{3\mathrm{GHz}}{100\mathrm{MHz}}=30.$
Thus a ratio of K.sub.max/K.sub.min=3 would be reached. In contrast, by means of the additional oscillator VCO-A the frequency of the output signal f.sub.out divided by the divider /N may be increased, for example by the frequency f.sub.A having a value of f.sub.A=5 GHz. For f.sub.A=5 GHz,

(43) $\frac{f_{\mathrm{out}}}{N}+f_A=6\mathrm{.Math.}8\mathrm{GHz},\mathrm{and}\frac{f_{\mathrm{ref}}}{R}=100\mathrm{MHz},$
follows

(44) $K_{\min }=\frac{6\mathrm{GHz}}{100\mathrm{MHz}}=60,K_{\max }=\frac{8\mathrm{GHz}}{100\mathrm{MHz}}=80.$
This results in an reduced ratio of

(45) $\frac{K_{\max }}{K_{\min }}=1,\stackrel{\_}{3}.$
As the phase-locked loop operates in a smaller operating range of the partial ratios of the adjustable divider /K, an occurring variation of the loop gain may be reduced during operation.

(46) For example, by using higher dividers /N, the ratio

(47) $\frac{K_{\max }}{K_{\min }}$
for the operation of the divider /K may be further reduced. For example, even without additional VCO-A, the variation of values of the divider /K may be reduced by higher dividers /N, however, some PLLs may require divider values of the divider /K>1. Thus, it can be advantageous to select the input frequencies of the PLL at the divider input/K at the upper edge of the input frequency range the PLL can use.

(48) In addition, the concept with additional oscillator VCO-A and mixer 26 with a shift of the PLL control frequency to higher frequencies is also applicable to e.g. PLL realizations with a single VCO (e.g. in a phase-locked loop according to FIG. 4) and may enable the use of commercial or already existing PLL devices which, for example, have a minimum divider /K of unequal 1 (e.g. >30) which, e.g., cannot process arbitrarily small input frequencies. Due to this minimum divider /K, it is not possible for a PLL to regulate low frequencies

(49) $\left(e.g.\frac{f_{\mathrm{out}}}{N\times K}<\frac{f_{\mathrm{ref}}}{R}\right),$
which may be necessary with the concepts shown, since, for example, broadband output frequencies of the signal f.sub.out between 0 Hz up to several 10 GHz are to be generated.

(50) The use of the additional mixer can be applied, as mentioned, not only to the signal generation principle with two VCOs shown in FIG. 8, but also to any signal generation circuits having a controlled oscillator and phase-locked loop (e.g. an oscillator with a phase-locked loop exclusively assigned to it).

(51) Further details and aspects are described in connection with examples detailed further above or further below. The examples shown using FIG. 8 may comprise one or more optional additional features corresponding to one or more aspects described in connection with the proposed concept or one or more examples further above or further below (for example in connection with FIGS. 1-7).

(52) One aspect of disclosure concerns a method for stabilizing two oscillators with a single phase-locked loop (PLL) to generate broadband signals.

(53) By means of the proposed concepts, for example, broadband output signals can be created in a simple manner using two very high-frequency VCOs, whereby, e.g., only one PLL is required, so that the switching complexity and power loss may be reduced, compared to other concepts. For example, the robustness of the signal generation against interference couplings may be improved by the proposed differential tune voltages (e.g. control voltages of the controlled oscillators). Further, in-loop phase noise may be reduced by regulating a common phase-locked loop with f.sub.out.

(54) The aspects and features mentioned and described together with one or more of the previously detailed examples and figures may as well be combined with one or more of the other examples in order to replace a like feature of the other example or in order to additionally introduce the feature to the other example.

(55) Examples may further be or relate to a computer program having a program code for performing one or more of the above methods, when the computer program is executed on a computer or processor. Steps, operations or processes of various above-described methods may be performed by programmed computers or processors. Examples may also cover program storage devices such as digital data storage media, which are machine, processor or computer readable and encode machine-executable, processor-executable or computer-executable programs of instructions. The instructions perform or cause performing some or all of the acts of the above-described methods. The program storage devices may comprise or be, for instance, digital memories, magnetic storage media such as magnetic disks and magnetic tapes, hard drives, or optically readable digital data storage media. Further examples may also cover computers, processors or control units programmed to perform the acts of the above-described methods or (field) programmable logic arrays ((F)PLAs) or (field) programmable gate arrays ((F)PGAs), programmed to perform the acts of the above-described methods.

(56) The description and drawings merely illustrate the principles of the disclosure. Furthermore, all examples recited herein are principally intended expressly to be only for illustrative purposes to aid the reader in understanding the principles of the disclosure and the concepts contributed by the inventor(s) to furthering the art. All statements herein reciting principles, aspects, and examples of the disclosure, as well as specific examples thereof, include equivalents thereof.

(57) A functional block denoted as “means for . . . ” performing a certain function may refer to a circuit that is configured to perform a certain function. Hence, a “means for s.th.” may be implemented as a “means configured to or suited for s.th.”, such as a device or a circuit configured to or suited for the respective task.

(58) Functions of various elements shown in the figures, including any functional blocks labeled as “means”, “means for providing a signal”, “means for generating a signal.”, etc., may be implemented in the form of dedicated hardware, such as “a signal provider”, “a signal processing unit”, “a processor”, “a controller”, etc. as well as hardware capable of executing software in association with appropriate software. When provided by a processor, the functions may be provided by a single dedicated processor, by a single shared processor, or by a plurality of individual processors, some of which or all of which may be shared. However, the term “processor” or “controller” is by far not limited to hardware exclusively capable of executing software, but may include digital signal processor (DSP) hardware, a network processor, an application specific integrated circuit (ASIC), a field programmable gate set (FPGA), read only memory (ROM) for storing software, random access memory (RAM), and non-volatile storage. Other hardware, conventional and/or custom, may also be included.

(59) A block diagram may, for instance, illustrate a rough circuit diagram implementing the principles of the disclosure. Similarly, a flow chart, a flow diagram, a state transition diagram, a pseudo code, and the like may represent various processes, operations or steps, which may, for instance, be substantially represented in computer readable medium and so executed by a computer or processor, whether or not such computer or processor is explicitly shown. Methods disclosed in the specification or in the claims may be implemented by a device having means for performing each of the respective acts of these methods.

(60) It is to be understood that the disclosure of multiple acts, processes, operations, steps or functions disclosed in the specification or claims may not be construed as to be within the specific order, unless explicitly or implicitly stated otherwise, for instance for technical reasons. Therefore, the disclosure of multiple acts or functions will not limit these to a particular order unless such acts or functions are not interchangeable for technical reasons. Furthermore, in some examples a single act, function, process, operation or step may include or may be broken into multiple sub-acts, —functions, —processes, —operations or —steps, respectively. Such sub acts may be included and part of the disclosure of this single act unless explicitly excluded.

(61) Furthermore, the following claims are hereby incorporated into the detailed description, where each claim may stand on its own as a separate example. While each claim may stand on its own as a separate example, it is to be noted that—although a dependent claim may refer in the claims to a specific combination with one or more other claims—other examples may also include a combination of the dependent claim with the subject matter of each other dependent or independent claim. Such combinations are explicitly proposed herein unless it is stated that a specific combination is not intended. Furthermore, it is intended to also include features of a claim to any other independent claim even if this claim is not directly made dependent to the independent claim.