Inspection Method for Pins and Vias of Differential Signal Lines
20210148965 ยท 2021-05-20
Inventors
Cpc classification
G01R31/2813
PHYSICS
International classification
Abstract
A method of inspecting a printed circuit board includes confirming whether all parts of the printed circuit board need to be inspected, if inspecting all parts of the printed circuit board, checking pins and vias belonging to each differential signal line on the printed circuit board, and outputting an inspecting result.
Claims
1. A method of inspecting a printed circuit board (PCB), comprising: confirming whether all parts of the printed circuit board need to be inspected; if inspecting all parts of the printed circuit board, checking pins and vias belonging to each differential signal line on the printed circuit board; and outputting an inspecting result.
2. The method of inspecting a printed circuit board of claim 1, wherein checking the pins and the vias belonging to each differential signal line on the printed circuit board comprises: checking radii of the vias belonging to each differential signal line on the printed circuit board.
3. The method of inspecting a printed circuit board of claim 1 further comprising: checking whether positions of copper cutout areas on the printed circuit board correspond to positions of the pins and the vias.
4. The method of inspecting a printed circuit board of claim 1 further comprising: checking number of layers and positions of layout restricted areas on the printed circuit board.
5. The method of inspecting a printed circuit board of claim 1, wherein checking the pins and the vias belonging to each differential signal line on the printed circuit board comprises: checking a relative slope and number of layers of a pair of differential signal lines on the printed circuit board, positions of pins of the pair of differential signal lines, and positions and sizes of vias of the pair of differential signal lines.
6. A method of inspecting a printed circuit board, comprising: confirming whether all parts of the printed circuit board need to inspected; if inspecting only a part of the printed circuit board, checking pins and vias belonging to differential signal lines on the part of the printed circuit board; and outputting an inspecting result.
7. The method inspecting a printed circuit board of claim 6, wherein checking the pins and the vias belonging to the differential signal lines on the part of the printed circuit board comprises: checking radii of the vias belonging to the differential signal lines on the part of the printed circuit board.
8. The method inspecting a printed circuit board of claim 6 further comprising: checking whether positions of copper cutout areas on the printed circuit board correspond to positions of the pins and the vias.
9. The method inspecting a printed circuit board of claim 6 further comprising: checking number of layers and positions of layout restricted areas on the part of the printed circuit board.
10. The method inspecting a printed circuit board of claim 6, wherein checking the pins and the vias belonging to the differential signal lines on the part of the printed circuit board comprises: checking a relative slope and number of layers of a pair of differential signal lines on the part of the printed circuit board, positions of pins of the pair of differential signal lines, and positions and sizes of vias of the pair of differential signal lines.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
[0007]
[0008]
DETAILED DESCRIPTION
[0009]
[0010] The printed circuit board layout diagram file 40 contains all the layout information of a printed circuit board, including the path of the signal lines, the pin and the vias of the signal lines, and the signal lines binding data. The signal lines binding data identifies the same pair of differential signal lines. For example, if one signal line A0 is marked to bind to another signal line A1 in the printed circuit board layout diagram file 40, it means that the signal lines A0 and A1 are a pair of differential signal lines.
[0011] The memory 20 is for storing a printed circuit board layout diagram file 40 and the automatic inspection program 50 for pins and vias of differential signal lines. The memory 20 may be a storage device such as a hard disk, a flash memory, and a solid state drive. The processor 10 is for to executing the automatic inspection program 50 for pins and vias of differential signal lines. The display 30 is for displaying the content of the printed circuit board layout diagram file 40, and for displaying the user interface for the user to input inspection parameters and displaying inspection results.
[0012] The automatic inspection program 50 for pins and vias of differential signal lines can be applied to inspect all the pins and the vias of differential signal lines in the printed circuit board layout diagram file 40 to ensure that copper areas other than the differential signal lines are cut out and to generate layout restricted areas. This allows engineers to make layout modifications to prevent signal interference for the circuits.
[0013]
[0014] S202: Start;
[0015] S204: Select all pins and vias on the printed circuit board;
[0016] S206: Is there any part on the printed circuit board that does not need to be inspected? If yes, proceed to step S208; if no, proceed to step S210;
[0017] S208: Deselect the pins and the vias that do not need to be inspected;
[0018] S210: Inspect the pins and the vias on the printed circuit board, excluding those pins and vias that do not belong to any differential signal lines;
[0019] S212: Inspect the parameters of the pins and the vias, including checking the radii of the vias, checking whether the copper cutout areas are consistent with the positions of the pins and the vias, checking the relative slope and the number of layers of a pair of differential signal lines, and checking the positions of the pins and the positions and sizes of the vias belonging to the pair of differential signal lines; if no errors are detected, proceed to step S216; if an error is detected, proceed to step S214;
[0020] S214: Report the position and the name of the signal lines having errors, and display the error icon indifferent colors; proceed to step S218;
[0021] S216: Report that no errors are detected;
[0022] S218: End of the process.
[0023] The programming inspection method 200 for pins and vias of differential signal lines requires parameters such as position of the pins and position, size and radii of the vias, and the routing layers of the differential signal lines. Without manual inspection by personnel, the programming inspection method 200 can determine whether the layout diagram violates any requirement according to the above parameters.
[0024] Step S210 can check the pins and the vias on the printed circuit board. If a pin or a via belongs to a power supply, ground, and other signal lines but not to a differential signal line, it will be excluded before proceeding further inspection.
[0025] In step S212, an error is reported if any of the following condition is detected: no layout restricted areas, the number of layers of the layout restricted areas not corresponding to the requirements, no copper cutout areas, the copper cutout areas being inconsistent with the position of the pins and the vias, and/or the copper cutout areas being inconsistent with the size of the vias.
[0026] In summary, the programming inspection method for pins and vias of differential signal lines on the printed circuit board according to the embodiment of the invention can provide a programming inspection method for engineers to check the pins and the vias of differential signal lines. Manual inspection can waste time and labor cost and also cannot ensure that the results satisfy the requirements. However, programming inspection for pin and vias is time efficient and low cost with higher inspection accuracy. It can quickly and accurately screen out differential signal lines with problems, thereby saving time and cost.
[0027] Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.