FAST REAL-TIME CARDIAC CINE MRI RECONSTRUCTION WITH RESIDUAL CONVOLUTIONAL RECURRENT NEURAL NETWORK

Abstract

A method includes using fully sampled retro cine data to train an algorithm, and applying the trained algorithm to real time MR cine data to yield reconstructed MR images.

Claims

1. A method comprising: using fully sampled retro cine data to train an algorithm, and applying the trained algorithm to real time MR cine data to yield reconstructed MR images.

2. The method of claim 1, further comprising using one or more of sub-sampled retro-cine data and sub-sampling masks to train the algorithm.

3. The method of claim 1, further comprising using retro cine data from individual coils of a multi-coil MR scanner to train the algorithm.

4. The method of claim 1, wherein the real time MR cine data comprises real time MR cine data from individual coils of a multiple coil MR scanner.

5. The method of claim 1, further comprising using fully sampled retro cine data to calculate loss during training, wherein the loss comprises one or more of mean square error loss, L1 loss, Structural Similarity Index (SSIM) loss, or Huber loss.

6. The method of claim 1, wherein the algorithm comprises a residual convolutional recurrent neural network.

7. The method of claim 1, wherein the real time MR cine data comprises under-sampled multi-coil real time MR cine data.

8. The method of claim 1, wherein the real time MR cine data comprises real time MR cine data from individual coils of a multiple coil MR scanner and the algorithm comprises a plurality of algorithms, each configured to be applied to data from a different individual coil of the multiple coil MR scanner.

9. The method of claim 8, comprising combining reconstructed images from the plurality of algorithms using a root sum of squares or coil sensitivity maps to generate a final combined image.

10. The method of claim 1, wherein the real time MR cine data comprises real time MR cine data from individual coils of a multiple coil MR scanner and the algorithm comprises a single algorithm configured to be applied to data from the individual coils of the multiple coil MR scanner.

11. A system comprising: s source of real time MR cine data; and computing circuitry implementing an algorithm trained using fully sampled retro cine data, wherein the trained algorithm is configured to yield reconstructed MR images when applied to real time MR cine data.

12. The system of claim 11, wherein the algorithm is trained using one or more of sub-sampled retro-cine data and sub-sampling masks.

13. The system of claim 11, wherein the algorithm is trained using retro cine data from individual coils of a multi-coil MR scanner.

14. The system of claim 11, wherein the real time MR cine data comprises real time MR cine data from individual coils of a multiple coil MR scanner.

15. The system of claim 14, wherein the fully sampled retro-cine data is used to calculate loss during training, wherein the loss comprises one or more of mean square error loss, L1 loss, Structural Similarity Index (SSIM) loss, or Huber loss.

16. The system of claim 11, wherein the algorithm comprises a residual convolutional recurrent neural network.

17. The system of claim 11, wherein the real time MR cine data comprises under-sampled multi-coil real time MR cine data.

18. The system of claim 11, wherein the real time MR cine data comprises real time MR cine data from individual coils of a multiple coil MR scanner and the algorithm comprises a plurality of algorithms, each configured to be applied to data from a different individual coil of the multiple coil MR scanner.

19. The system of claim 18, wherein the computing circuitry is configured to generate a final combined image by combining reconstructed images from the plurality of algorithms using a root sum of squares or coil sensitivity maps.

20. The method of claim 11, wherein the real time MR cine data comprises real time MR cine data from individual coils of a multiple coil MR scanner and the algorithm comprises a single algorithm configured to be applied to data from the individual coils of the multiple coil MR scanner.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In the following detailed portion of the present disclosure, the invention will be explained in more detail with reference to the example embodiments shown in the drawings. These embodiments are non-limiting exemplary embodiments, in which like reference numerals represent similar structures throughout the several views of the drawings, wherein:

[0019] FIG. 1 illustrates an exemplary process flow according to aspects of the disclosed embodiments;

[0020] FIG. 2 illustrates an embodiment of an exemplary system incorporating aspects of the disclosed embodiments;

[0021] FIG. 3 illustrates an embodiment of another exemplary system incorporating aspects of the disclosed embodiments;

[0022] FIG. 4 shows a schematic block diagram of an exemplary multi-coil MRI data source according to the disclosed embodiments;

[0023] FIGS. 5A and 5B illustrate different MRI multi-coil arrangements according to the disclosed embodiments;

[0024] FIG. 6 illustrates an exemplary architecture of computing circuitry in which an algorithm may be implemented according to the disclosed embodiments;

[0025] FIG. 7 illustrates an example of an algorithm in the form of a deep residual convolutional recurrent neural network; and

[0026] FIG. 8 illustrates an example of a bi-directional convolutional recurrent neural network cell.

DETAILED DESCRIPTION

[0027] In the following detailed description, numerous specific details are set forth by way of examples in order to provide a thorough understanding of the relevant disclosure. However, it should be apparent to those skilled in the art that the present disclosure may be practiced without such details. In other instances, well known methods, procedures, systems, components, and/or circuitry have been described at a relatively high-level, without detail, in order to avoid unnecessarily obscuring aspects of the present disclosure. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirits and scope of the present disclosure. Thus, the present disclosure is not limited to the embodiments shown, but to be accorded the widest scope consistent with the claims.

[0028] It will be understood that the term “system,” “unit,” “module,” and/or “block” used herein are one method to distinguish different components, elements, parts, section or assembly of different level in ascending order. However, the terms may be displaced by other expressions if they may achieve the same purpose.

[0029] It will be understood that when a unit, module or block is referred to as being “on,” “connected to” or “coupled to” another unit, module, or block, it may be directly on, connected or coupled to the other unit, module, or block, or intervening unit, module, or block may be present, unless the context clearly indicates otherwise. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

[0030] Generally, the word “module,” “unit,” or “block,” as used herein, refers to logic embodied in hardware or firmware, or to a collection of software instructions. A module, a unit, or a block described herein may be implemented as software and/or hardware and may be stored in any type of non-transitory computer-readable medium or another storage device. In some embodiments, a software module/unit/block may be compiled and linked into an executable program. It will be appreciated that software modules can be callable from other modules/units/blocks or from themselves, and/or may be invoked in response to detected events or interrupts. Software modules/units/blocks configured for execution on computing devices may be provided on a computer-readable medium, such as a compact disc, a digital video disc, a flash drive, a magnetic disc, or any other tangible medium, or as a digital download (and can be originally stored in a compressed or installable format that needs installation, decompression, or decryption prior to execution). Such software code may be stored, partially or fully, on a storage device of the executing computing device, for execution by the computing device. Software instructions may be embedded in firmware, such as an Erasable Programmable Read Only Memory (EPROM). It will be further appreciated that hardware modules/units/blocks may be included in connected logic components, such as gates and flip-flops, and/or can be included of programmable units, such as programmable gate arrays or processors. The modules/units/blocks or computing device functionality described herein may be implemented as software modules/units/blocks, but may be represented in hardware or firmware. In general, the modules/units/blocks described herein refer to logical modules/units/blocks that may be combined with other modules/units/blocks or divided into sub-modules/sub-units/sub-blocks despite their physical organization or storage. The description may be applicable to a system, an engine, or a portion thereof.

[0031] The terminology used herein is for the purposes of describing particular examples and embodiments only, and is not intended to be limiting. As used herein, the singular forms “a,” “an,” and “the” may be intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “include,” and/or “comprise,” when used in this disclosure, specify the presence of integers, devices, behaviors, stated features, steps, elements, operations, and/or components, but do not exclude the presence or addition of one or more other integers, devices, behaviors, features, steps, elements, operations, components, and/or groups thereof.

[0032] These and other features, and characteristics of the present disclosure, as well as the methods of operation and functions of the related elements of structure and the combination of parts and economies of manufacture, may become more apparent upon consideration of the following description with reference to the accompanying drawings, all of which form a part of this disclosure. It is to be expressly understood, however, that the drawings are for the purpose of illustration and description only and are not intended to limit the scope of the present disclosure. It is understood that the drawings are not to scale.

[0033] The disclosed embodiments are directed to a method comprising using fully sampled retro cine data to train an algorithm, and applying the trained algorithm to multi-coil real time MRI cine data to yield reconstructed MRI images.

[0034] The disclosed embodiments are further directed to a system comprising a source of fully sampled retro cine MR data, an algorithm configured to be trained using the fully sampled retro cine MR data, and a source of multi-coil real time MR cine data, wherein the trained algorithm may be applied to the multi-coil real time MR cine data to yield reconstructed MR images.

[0035] Referring to FIG. 1, a schematic block diagram of an exemplary system 100 incorporating aspects of the disclosed embodiments is illustrated. The system may include a source of multi-coil real time MR cine data 102, an algorithm 104, and a source of fully sampled retro cine MR data 106. The fully sampled retro cine data 106 may be used to train the algorithm 104, and the trained algorithm 104 may be applied to the multi-coil real time MR cine data 102 to yield reconstructed MR images 108.

[0036] FIGS. 2 and 3 illustrate embodiments of exemplary systems 200, 300 incorporating aspects of the disclosed embodiments. FIG. 2 illustrates an exemplary embodiment that provides independent multi-coil reconstruction by providing an algorithm in the form of a deep learning model for each coil of a multi-coil MR system. An inverse Fourier transform (iFT) may be performed on subsampled k-space real time multi-coil data 202 to yield multi-coil images 204 that include aliasing and artifacts due to the subsampling. The images 204 with aliasing and artifacts may be separated into individual images 206.sub.1-206.sub.n according to the individual coils from which they are obtained. An associated algorithm 208.sub.1-208.sub.n may be applied to each image 206.sub.1-206.sub.n to yield a corresponding reconstructed image 210.sub.1-210.sub.n and the reconstructed images 210.sub.1-210.sub.n may be combined to yield a combined reconstructed image 212. The reconstructed images from each individual coil may be combined using root sum of square (RSS) or coil sensitivity maps to generate the final combined reconstructed image 212.

[0037] FIG. 3 illustrates an exemplary embodiment that provides parallel multi-coil reconstruction by applying a single algorithm to images from the coils. An inverse Fourier transform (iFT) may be performed on subsampled k-space real time multi-coil data 302 to yield multi-coil images 304 that include aliasing and artifacts due to the subsampling. The images 304 with aliasing and artifacts may be separated into individual images 306.sub.1-306.sub.n according to the individual coils from which they are obtained. The images 306.sub.1-306.sub.n may be provided as input to a single algorithm 308 to yield a reconstructed image 310.

[0038] FIG. 4 shows a schematic block diagram of an exemplary multi-coil MRI data source in the form of an MRI apparatus 402 for providing multi-coil MRI data according to the disclosed embodiments. The MRI apparatus 402 may include an MRI scanner 404, control circuitry 406 and a display 408. The function, size, type, geometry, position, amount, or magnitude of the MRI scanner 404 may be determined or changed according to one or more specific conditions. For example, the MRI scanner 404 may be designed to surround a subject (or a region of the subject) to form a tunnel type MRI scanner, referred to as a closed bore MRI scanner, or an open MRI scanner, referred to as an open-bore MRI scanner. As another example, the MRI scanner may be portable and transportable down hallways and through doorways to a patient, providing MR scanning services to the patient as opposed to transporting the patient to the MRI scanner. In some examples, a portable MRI scanner may be configured to scan a region of interest of a subject, for example, the subject's brain, spinal cord, limbs, heart, blood vessels, and internal organs.

[0039] The MRI scanner 404 may include, as shown in cross section in FIG. 4, a magnetic field generator 410, a gradient magnetic field generator 412, and a Radio Frequency (RF) generator 414, all surrounding a table 416 on which subjects under study may be positioned. The MRI scanner 404 may also include one or more coil arrays 418, an ECG signal sensor 420 for capturing MRI data in the form of ECG signals from the subject under study during MRI scanning, and a camera 422 for capturing MRI data in the form of video images of the subject under study during MRI scanning.

[0040] In some embodiments, the MRI scanner 404 may perform a scan on a subject or a region of the subject. The subject may be, for example, a human body or other animal body. In some embodiments, the subject may be a patient. The region of the subject may include part of the subject. For example, the region of the subject may include a tissue of the patient. The tissue may include, for example, lung, prostate, breast, colon, rectum, bladder, ovary, skin, liver, spine, bone, pancreas, cervix, lymph, thyroid, spleen, adrenal gland, salivary gland, sebaceous gland, testis, thymus gland, penis, uterus, trachea, skeletal muscle, smooth muscle, heart, etc. In some embodiments, the scan may be a pre-scan for calibrating an imaging scan. In some embodiments, the scan may be an imaging scan for generating an image.

[0041] The main magnetic field generator 410 may create a static magnetic field B.sub.0 and may include, for example, a permanent magnet, a superconducting electromagnet, a resistive electromagnet, or any magnetic field generation device suitable for generating a static magnetic field. The gradient magnet field generator 412 may use coils to generate a magnetic field in the same direction as B.sub.0 but with a gradient in one or more directions, for example, along X, Y, or Z axes in a coordinate system of the MRI scanner 404.

[0042] In some embodiments, the RF generator 414 may use RF coils to transmit RF energy through the subject, or region of interest of the subject, to induce electrical signals in the region of interest. The resulting RF field is typically referred to as the Bi field and combines with the B.sub.0 field to generate MR signals that are spatially localized and encoded by the gradient magnetic field. The coil arrays 418 may generally operate to sense the RF field and convey a corresponding output to the control circuitry 406. In some embodiments, the coil arrays may operate to both transmit and receive RF energy, while in other embodiments, the coil arrays may operate as receive only.

[0043] FIGS. 5A and 5B illustrate different MRI multi-coil arrangements. The multi-coil arrangements may include phased array coil arrangements and parallel array coil arrangements. FIG. 5A shows an exemplary phased array coil arrangement where the coils overlap and are coupled together to enhance gain and signal to noise properties. FIG. 5B shows an exemplary parallel array arrangement where the coils are decoupled and optimized for parallel imaging. The coil arrangements may include any number of coils, depending on a particular application. Exemplary numbers of coils may include 12, 16, 24, 32, 64 or more.

[0044] Returning to FIG. 4, the control circuitry 406 may control overall operations of the MRI scanner 404, in particular, the magnetic field generator 410, the gradient magnetic field generator 412, the RF generator 414, and the coil arrays 418. For example, the control circuitry 406 may control the magnet field gradient generator to produce gradient fields along one or more of the X, Y, and Z axes, and the RF generator to generate the RF field. In some embodiments, the control circuitry 406 may receive commands from, for example, a user or another system, and control the magnetic field generator 410, the gradient magnetic field generator 412, the RF generator 414, and the coil arrays 418 accordingly.

[0045] The control circuitry 406 may be connected to the MRI scanner 404 through a network 424. The network 424 may include any suitable network that can facilitate the exchange of information and/or data for the MRI scanner 404. The network 424 may be and/or include a public network (e.g., the Internet), a private network (e.g., a local area network (LAN), a wide area network (WAN)), etc.), a wired network (e.g., an Ethernet network), a wireless network (e.g., an 802.11 network, a Wi-Fi network, etc.), a cellular network (e.g., a Long Term Evolution (LTE) network), a frame relay network, a virtual private network (“VPN”), a satellite network, a telephone network, routers, hubs, switches, server computers, and/or any combination thereof. Merely by way of example, the network 424 may include a cable network, a wireline network, a fiber-optic network, a telecommunications network, an intranet, a wireless local area network (WLAN), a metropolitan area network (MAN), a public telephone switched network (PSTN), a Bluetooth™ network, a ZigBee™ network, a near field communication (NFC) network, or the like, or any combination thereof. In some embodiments, the network 424 may include one or more network access points. For example, the network 424 may include wired and/or wireless network access points such as base stations and/or internet exchange points through which one or more components of the MRI scanner 402 may be connected with the network 424 to exchange data and/or information.

[0046] According to some embodiments, the algorithm may be implemented in computing circuitry of the control circuitry 406, while in other embodiments, the algorithm may be implemented in computing circuitry located remotely from the control circuitry 406.

[0047] FIG. 6 illustrates an exemplary architecture of the computing circuitry 600 according to the disclosed embodiments. The computing circuitry 600 may include computer readable program code stored on at least one computer readable medium 602 for carrying out and executing the process steps described herein. The computer readable program code for carrying out operations for aspects of the present disclosure may be written in any combination of one or more programming languages, including an object-oriented programming language such as Java, Scala, Smalltalk, Eiffel, JADE, Emerald, C++, C#, VB. NET, Python or the like, conventional procedural programming languages, such as the “C” programming language, Visual Basic, Fortran 2103, Perl, COBOL 2102, PHP, ABAP, dynamic programming languages such as Python, Ruby, and Groovy, or other programming languages. The computer readable program code may execute entirely on the computing circuitry 600, partly on the computing circuitry 600, as a stand-alone software package, partly on the computing circuitry 600 and partly on a remote computer or server or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the computing circuitry 600 through any type of network, including those mentioned above with respect to network 424.

[0048] The computer readable medium 602 may be a memory of the computing circuitry 600. In alternate aspects, the computer readable program code may be stored in a memory external to, or remote from, the computing circuitry 600. The memory may include magnetic media, semiconductor media, optical media, or any media which is readable and executable by a computer. The computing circuitry 600 may also include a computer processor 604 for executing the computer readable program code stored on the at least one computer readable medium 602. In some embodiments, the computer processor may be a graphics processing unit, or graphical processing unit (GPU). In at least one aspect, the computing circuitry 600 may include one or more input or output devices, generally referred to as a user interface 606 which may operate to allow input to the computing circuitry 600 or to provide output from the computing circuitry 600, respectively. The computing circuitry 600 may be implemented in hardware, software or a combination of hardware and software.

[0049] FIG. 7 illustrates an example of the algorithm in the form of a deep residual convolutional recurrent neural network (Res-CRNN) 700, and FIG. 8 illustrates an example of a bi-directional convolutional recurrent neural network cell 800. One feature of the deep residual convolutional recurrent neural network is that the state neurons of a conventional recurrent neural network (RNN) may be split into a section that is responsible for the positive time direction (forward states) and a section that is responsible for the negative time direction (backward states). In addition, outputs from forward states are not connected to inputs of backward states, and outputs from backward states are not connected to inputs of forward states.

[0050] The bi-directional convolutional RNN may model the dynamic information of cardiac cine data, the data consistency layer which makes sure the reconstructed data is consistent with observed data, as well as a residual connection, which promotes the network to learn high-frequency details and adds stability to the training process. The Res-CRNN 700 may include three such building blocks 702.sub.1-702.sub.3 and one extra residual connection 704.sub.1-704.sub.3. The complex values are represented as a two-channel tensor and fed into the network. The deep residual convolutional recurrent neural network may be trained with the same algorithms as a regular unidirectional RNN because there are no interactions between the two types of state neurons.

[0051] As shown in FIG. 7, multi-coil subsampled real time cine data 706 from the MRI scanner 404 may be provided to the algorithm 700. Reconstructed cine images from each stage may be provided to the next stage until final reconstructed cine images 708 are achieved.

[0052] The algorithm 700 may be trained using retro-cine data and images reconstructed by the algorithm 700. Fully sampled retro-cine data may be subsampled with sampling masks similar to those used in real-time cine during MRI image acquisition. One or more of the subsampled retro-cine data, sampling masks and the fully sampled data retro cine data may also be used to train the algorithm 700. The retro-cine training data may include fully sampled images from individual coils of the MRI scanner 404. In order to conserve memory consumption, for example where the algorithm computing circuitry includes a graphics processing unit, the retrocine images may be cropped to a smaller size for training.

[0053] During training, the fully sampled retro-cine may be used to calculate loss. The training loss may be implemented in one of, or any combination of, mean square error loss, L1 loss, Structural Similarity Index (SSIM) loss, Huber loss or any loss for image quality evaluation.

[0054] Once trained, the algorithm 700 may be applied to under-sampled real-time cine data for image construction, including images from multi-coil acquisitions and full size uncropped images.

[0055] Thus, while there have been shown, described and pointed out, fundamental novel features of the invention as applied to the exemplary embodiments thereof, it will be understood that various omissions, substitutions and changes in the form and details of devices and methods illustrated, and in their operation, may be made by those skilled in the art without departing from the spirit and scope of the presently disclosed invention. Further, it is expressly intended that all combinations of those elements, which perform substantially the same function in substantially the same way to achieve the same results, are within the scope of the invention. Moreover, it should be recognized that structures and/or elements shown and/or described in connection with any disclosed form or embodiment of the invention may be incorporated in any other disclosed or described or suggested form or embodiment as a general matter of design choice. It is the intention, therefore, to be limited only as indicated by the scope of the claims appended hereto.