HOUSING COMPRISING A SEMICONDUCTOR BODY AND A METHOD FOR PRODUCING A HOUSING WITH A SEMICONDUCTOR BODY

Abstract

A method for producing a component having a semiconductor body includes providing the semiconductor body including a radiation passage surface and a rear side facing away from the radiation passage surface, wherein the semiconductor body comprises on the rear side a connection location for the electrical contacting of the semiconductor body, providing a composite carrier including a carrier layer and a partly cured connecting layer, applying the semiconductor body on the composite carrier, such that the connection location penetrates into the partly cured connecting layer, curing the connecting layer to form a solid composite, applying a molded body material on the composite carrier after curing the connecting layer, wherein the molded body covers side surfaces of the semiconductor body, forming a cutout through the carrier layer and the connecting layer in order to expose the connection location, and filling the cutout with an electrically conductive material.

Claims

1. A method for producing a component comprising a semiconductor body, the method comprising: providing the semiconductor body comprising a radiation passage surface and a rear side facing away from the radiation passage surface, wherein the semiconductor body comprises on the rear side a connection location for the electrical contacting of the semiconductor body, providing a composite carrier comprising a carrier layer and a partly cured connecting layer applied on the carrier layer, applying the semiconductor body on the composite carrier, such that the connection location penetrates into the partly cured connecting layer, curing the connecting layer in order to form a solid composite comprising the semiconductor body and the composite carrier, applying a molded body material on the composite carrier in order to form a molded body after curing the connecting layer, wherein the molded body covers side surfaces of the semiconductor body, forming a cutout through the carrier layer and the connecting layer in order to expose the connection location, and filling the cutout with an electrically conductive material, such that the electrically conductive material is in electrical contact with the connection location and the carrier layer.

2. The method as claimed in claim 1, wherein the connecting layer is formed from a fiber-reinforced resin material and is clad over the whole area with the carrier layer formed as a metal foil.

3. The method as claimed in claim 1, wherein the carrier layer comprises a copper foil and the connecting layer comprises a glass-fiber-reinforced epoxy resin layer.

4. The method as claimed in claim 1, wherein the carrier layer comprises a copper layer and the connecting layer comprises formed by applying an adhesive on the carrier layer.

5. The method as claimed in claim 1, wherein the molded body material comprises a potting compound and the molded body is formed by a molding method, such that the molded body covers the side surfaces of the semiconductor body.

6. The method as claimed in claim 5, wherein the molded body is formed by film assisted molding, wherein the semiconductor body is surrounded by the molded body fully circumferentially in a lateral direction.

7. The method as claimed in claim 1, wherein the semiconductor body comprises on the rear side two electrical connection locations associated with different electrical polarities of the semiconductor body, wherein the forming the cutout through the carrier layer comprises two cutouts spaced apart laterally from one another are formed through the carrier layer and the connecting layer to expose the connection locations.

8. The method as claimed in claim 7, wherein the semiconductor body is electrically short-circuited directly after the cutouts have been filled, and wherein the method further comprises forming an intermediate trench between the filled cutouts such that the electrical short circuit is canceled by the intermediate trench.

9. The method as claimed in claim 1, further comprising filling the cutout with a material identical to the material of the carrier layer.

10. The method as claimed in claim 1, further comprising forming the connection location from copper or coating with copper, wherein the carrier layer is formed from copper and the cutout is filled with copper.

11. The method as claimed in claim 1, wherein the semiconductor body is provided as part of an unpackaged semiconductor chip comprising two electrical connection locations on the rear side and the component after completion comprises a housing for the semiconductor body, wherein the housing is formed from a continuous composite comprising the molded body, the carrier layer and the connecting layer.

12. The method as claimed in claim 1 for producing a plurality of such components, further comprising applying a plurality of semiconductor bodies on the composite carrier, wherein the connection locations of the semiconductor body penetrate into the partly cured connecting layer, producing isolation trenches between the semiconductor bodies in a lateral direction and through the carrier layer in a vertical direction, singulating the components along the isolation trenches, such that each component comprises one of the semiconductor bodies and a housing, wherein the housing is formed from a continuous composite comprising the molded body, the carrier layer and the connecting layer.

13. A component comprising: a semiconductor body; and a housing formed from a continuous composite comprising: a molded body, a composite carrier arranged substantially flush with the molded body, wherein the composite carrier comprises a carrier layer and a cured electrically insulating connecting layer; an electrical connection location for an electrical contacting of the semiconductor body on a rear side of the semiconductor body facing the carrier layer; wherein the electrical connection location is arranged in the electrically insulating connecting layer and is surrounded by the electrically insulating connecting layer fully circumferentially in lateral directions; and an electrically conductive connection column bonded to the electrical connection location; wherein the electrically conductive connection column extends entirely through the carrier layer and the electrically insulating connecting layer, wherein the semiconductor body comprises a radiation passage surface on a side of the semiconductor body opposite to the rear side of the semiconductor body; wherein the radiation passage surface is free of the molded body and the molded body is at least partially in direct contact with the semiconductor body.

14. The component as claimed in claim 13, wherein the connection location is formed from copper or coated with copper and the carrier layer is formed from copper, wherein the electrical connection location and the carrier layer extend into the electrically insulating connecting layer in order to form an electrical contact.

15. The component as claimed in claim 13, wherein the semiconductor body comprises on the rear side two electrical connection locations, of which a first electrical connection location is electrically conductively connected to a first semiconductor layer of a first charge carrier type of the semiconductor body and a second electrical connection location is electrically conductively connected to a second semiconductor layer of a second charge carrier type of the semiconductor body, wherein the carrier layer is subdivided into two partial regions, which are spaced apart from one another laterally, overlap the connecting layer in plan view and are electrically connected in each case to one of the two connection locations.

16. A component comprising: a semiconductor body, a molded body, a carrier layer, and a cured electrically insulating connecting layer, wherein the electrically insulating connecting layer comprises a glass-fiber-reinforced epoxy resin layer, wherein the component comprises an electrical connection location for the electrical contacting of the semiconductor body on a rear side of the semiconductor body facing the carrier layer, wherein the electrical connection location is arranged in the electrically insulating connecting layer arranged between the semiconductor body and the carrier layer and is surrounded by the electrically insulating connecting layer fully circumferentially in lateral directions, and wherein the molded body covers side surfaces of the semiconductor body, wherein in a plan view of the carrier layer the molded body surrounds the semiconductor body fully circumferentially and overlaps the electrically insulating connecting layer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In the drawings, like reference characters generally refer to the same parts throughout the different views. The drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the disclosed embodiments. In the following description, various embodiments described with reference to the following drawings, in which:

[0034] FIGS. 1 to 7 show various method stages of one exemplary embodiment of a method for producing one or a plurality of components in schematic sectional views, and

[0035] FIGS. 8 to 11 show further exemplary embodiments of a method for producing one or a plurality of components in schematic sectional views.

DETAILED DESCRIPTION

[0036] Elements that are identical, of identical type or act identically are provided with identical reference signs in the figures. The figures are in each case schematic illustrations and therefore not necessarily true to scale. Rather, comparatively small elements and in particular layer thicknesses may be illustrated with an exaggerated size for clarification.

[0037] FIGS. 1 to 7 illustrate various method stages of one exemplary embodiment of a method for producing a plurality of components 100 in schematic sectional views.

[0038] In FIG. 1, a composite carrier 90 is provided. The composite carrier 90 includes a carrier layer 91, which is formed for instance as a metal layer, preferably as a metal foil, and a connecting layer 92 arranged on the carrier layer 91. The connecting layer 92 includes in particular a partly cured connecting material. The connecting layer 92 is initially formed in particular as viscose, preferably pasty and moldable. By way of example, the connecting layer 92 may include an adhesive. Moreover, the connecting layer 92 can be a printed circuit board material including a plastics matrix material reinforced with fibers, preferably with glass fibers, for instance. The composite carrier 90 can also be formed with 3 layers, 4 layers or in a multilayered fashion. In this case, the connecting layer 92 is formed in an electrically insulating fashion. The carrier layer 91 is formed in an electrically conductive fashion and includes in particular a metal, for instance copper.

[0039] The carrier layer 91 can be provided in this case as a copper layer, in particular as a copper foil, wherein the connecting layer 92 can be formed by applying an adhesion promoter, for example an adhesive, on the carrier layer 91 for example with the aid of a coating method.

[0040] Alternatively, the composite carrier 90 is provided as a printed circuit board prepreg. The prepreg includes a metal layer, for instance in the form of a copper foil, formed as the carrier layer 91, and an electrically insulating layer composed of a resin material, for instance, formed as the connecting layer 92. By way of example, the prepreg includes a connecting layer 92 composed of a partly cured high-Tg epoxy resin which is clad for instance over the whole area in particular with the carrier layer 91 composed of a metal such as copper, for example. In this case, the metal layer can be a copper foil having a vertical thickness of between 18 μm and 250 μm, for example. In this case, Tg denotes a glass transition temperature at which the epoxy resin microstructure becomes soft and extensible upon attaining this temperature. A high-Tg value is understood to mean in particular a temperature of between 140° C. and 210° C., for instance between 150° C. and 210° C. inclusive, or between 180° C. and 210° C. inclusive. Preferably, the connecting layer 92 has a Tg of greater than or equal to 180° C., such that the connecting layer 92 does not soften for instance when the molded body material is applied, for example by molding, in the course of which the temperature can be up to 180° C.

[0041] In accordance with FIG. 2, a plurality of semiconductor bodies 10 are applied on the composite carrier 90. The semiconductor body 10 includes a radiation passage surface 11 and a rear side 12 facing away from the radiation passage surface. The radiation passage surface 11 can be formed by a surface of a substrate 9, for instance of a growth substrate 9 or by a surface of a semiconductor layer 2. The semiconductor body 10 includes on the rear side 12 connection locations 70 for the electrical contacting of the semiconductor body 10. In this case, the connection locations 70 can be parts of connection layers which can extend into the semiconductor body 10.

[0042] By way of example, the semiconductor body 10 includes a first connection location 71, which is electrically conductively connected to a first semiconductor layer 1 of the semiconductor body, and a second connection location 72, which is electrically conductively connected to a second semiconductor layer 2 of the semiconductor body 10. The semiconductor body 10 additionally includes an active layer 3, which is arranged between the first semiconductor layer 1 and the second semiconductor layer 2 and is configured for emitting or detecting electromagnetic radiations in visible, ultraviolet or infrared spectral ranges during operation of the component. The radiation passage surface 11 can be unstructured or structured in order to increase the efficiency of coupling radiation in or out. The connection locations 70, 71 and 72 can be formed from copper or coated with copper.

[0043] The semiconductor body 10 can be formed as part of an unpackaged semiconductor chip. An unpackaged semiconductor chip is in particular free of a housing that laterally surrounds the semiconductor body. Moreover, the unpackaged semiconductor chip can be free of a carrier that differs from the growth substrate. Alternatively, it is possible to arrange the semiconductor body 10 of an unpackaged semiconductor chip on a carrier substrate 9 on a growth substrate 9. The unpackaged semiconductor chip can be a sapphire flip-chip. It is also possible for the growth substrate to be removed from the semiconductor body in a further method step, such that the component 100 is free of a growth substrate.

[0044] The unpackaged semiconductor chip can be a flip-chip in which the first semiconductor layer 1 and the active layer 3 are partly removed in order to expose the second semiconductor layer 2 and the second connection location 72 is electrically conductively connected to the second semiconductor layer 2 at an exposed surface. Alternatively, the unpackaged semiconductor chip may include a connection location formed as part of a connection layer in the form of a plated-through hole, wherein the plated-through hole extends through the first semiconductor layer 1 and the active layer 3 to the second semiconductor layer 2 and is thus electrically connected to the second semiconductor layer 2. The second connection location 72 and/or the connection layer in this case can be enclosed by the first semiconductor layer 1 and by the active layer 3 fully circumferentially in lateral directions and can be electrically insulated from these layers by an insulation layer.

[0045] The semiconductor bodies 10 are applied on the composite carrier 90, such that the connection locations 70 penetrate into the partly cured connecting layer 92 of the composite carrier 90, as a result of which the semiconductor bodies 10 are pre-fixed on the composite carrier 90. As a result, an interspace situated between the connection locations 70 in the lateral direction can be partly or completely filled with a material of the connecting layer 92.

[0046] In a further method step, the connecting layer 92 is cured for instance by a thermal treatment in order to form a solid, in particular permanent, composite including the semiconductor bodies 10 and the composite carrier 90. Particularly in the case of a printed circuit board material such as epoxy resin reinforced with fibers, in particular with glass fibers, a permanent mechanical connection between the semiconductor bodies 10 and the composite carrier 90 is produced by the curing of the connecting layer 92, wherein after curing the semiconductor bodies 10 can be separated from the carrier layer 91 for instance only by the connecting layer 92 being destroyed. After the curing of the connecting layer 92, the positions of the semiconductor bodies 10 on the composite carrier 90 are thus fixed permanently and in particular in a manner that can no longer be altered.

[0047] In FIG. 3, after the semiconductor bodies 10 have been fixed, a housing material, for instance in the form of a potting compound for producing a molded body 50, is applied on the composite carrier 90 for example by a molding method, such that the molded body 50 partly or completely covers side surfaces of the semiconductor bodies 10. In particular, interspaces between the semiconductor bodies 10 are filled with the molded body material. In this case, the molded body material can be a molded body material filled with scattering or reflective particles. In particular, the molded body material can be highly filled with the particles. The particles can thus make up for instance at least 60, for example at least 70 or 80% of the total weight or total volume of the molded body material. Such molded body material highly filled with scattering or reflective particles, without the semiconductor bodies 10 being fixed, can be applied on side surfaces of the semiconductor bodies 10 only with great outlay owing to the low viscosity and low adhesiveness of the molded body material. As a result of the semiconductor bodies 10 being fixed before the molded body 50 is formed, a molded body material highly filled with scattering or reflective particles, for instance, can be applied on the composite carrier 90 in a simplified manner for example by foil assisted molding, such that the molded body material for forming the molded body 10 can readily adhere to the side surfaces of the semiconductor bodies 20.

[0048] In FIG. 4, a plurality of cutouts 93 are formed in each case through the carrier layer 91 and the connecting layer 92 in order to expose the connection locations 70. In other words, the cutouts 93 each have a bottom surface formed by a surface of the connection location 70. In a departure from FIG. 4, it is also possible merely to form a common cutout 93 in order to expose for instance two or more connection locations 70 of a semiconductor body 10 that are assigned to the different electrical polarities. That is to say that the connection locations 70 of a semiconductor body 10 can be exposed in the common cutout 93.

[0049] In FIG. 5, the cutouts 93 are filled in each case with an electrically conductive material in order to form a plurality of connection columns 80. In this case, the cutouts 93 can be filled with a material identical to a material of the carrier layer 91. By way of example, the carrier layer 91 can be formed from copper. In particular, the cutouts 93 can be filled with copper. Moreover, the cutouts 93 can be filled with a material that differs from the material of the carrier layer 91. Directly after the cutouts have been filled, the semiconductor body 10 or the plurality of semiconductor bodies 10 can be electrically short-circuited since the connection columns 80 formed in the cutouts 93 adjoin the carrier layer 91 and can thus be electrically connected thereto. In the case of a common cutout 93 in which both connection locations 70 of a semiconductor body 10 are exposed, the common cutout 93 can be filled for example with the aid of a separating structure or a mask such that the connection columns 80 which are associated with the different connection locations 70 and are formed in the common cutout 93 are electrically insulated from one another, as a result of which the semiconductor body 10 is not electrically short-circuited directly after the common cutout 93 has been filled.

[0050] In FIG. 6, a plurality of intermediate trenches 94 are formed, wherein the intermediate trenches 94 are formed in each case between two filled cutouts 93 of a semiconductor body 10. In particular, the connecting layer 92 is exposed in the regions of the intermediate trenches 94. A possible electrical short circuit of the respective semiconductor body 10 can be canceled as a result.

[0051] In accordance with FIG. 6, moreover, a plurality of isolation trenches 95 are produced, wherein the isolation trenches 95 extend through the carrier layer 91 in particular as far as or into the connecting layer 92. In the lateral direction the isolation trenches 95 are formed in each case between two components 100 to be produced or between two series of components 100 to be produced. The components 100 can be singulated along the isolation trenches 95 in a subsequent method step, such that each component 100 includes one of the semiconductor bodies 10 and a housing 20, wherein the housing 20 is formed from a continuous composite including the singulated molded body 50, the singulated carrier layer 91 and the singulated connecting layer 92.

[0052] The cutouts 93, the intermediate trenches 94 and the isolation trenches 95 can be formed by a printed circuit board process, for example. In this case, the printed circuit board process may include for example processes which are used in the production of HDI (high density interconnect) printed circuit boards. In this case, the cutouts 93 and/or trenches 94 and 95 in the carrier layer 91 can be produced by a mechanical method, for instance by drilling and/or by a laser method. In particular, the cutouts 93 are opened for instance as far as the connecting layer 92 by a mechanical method, whereupon the cutouts 93 are deepened further for instance by a laser method, for instance by laser drilling, until the connection locations 70 are exposed at least in places in the respective cutouts. Laser drilling is a particularly suitable method for producing such cutouts since the cutouts 93 can be produced in a highly targeted and precise manner with regard to their positions and sizes and in a very short time by this method. It has additionally been found that copper layers can serve as particularly suitable stop layers during laser drilling. The connection locations 70 are therefore preferably formed from copper or consist thereof.

[0053] The isolation trenches 95 are formed in particular such that the isolation trenches 95 extend only through the carrier layer 91 and not through the connecting layer 92 or the molded body 50. During singulation into a plurality of semiconductor components 100, therefore, only the molded body 50 and/or the connecting layer 92 are/is separated along the isolation trenches 95, thereby preventing possible metal residues, for instance copper residues from the carrier layer 91, from being able to pass in the direction of the semiconductor body 10.

[0054] The cutouts 93, the intermediate trenches 94 or the isolation trenches 95 can each include an inner wall having separating traces. In particular, all inner walls of the trenches 93, of the intermediate trenches 94 and/or of the isolation trenches 95 can have separating traces. Separating traces are understood to mean traces for instance on the inner wall of the respective cutout which arose for instance during the formation of the cutout. Such traces can be characteristic traces of a corresponding processing process. The separating traces can additionally be present in the form of grooves filled with electrically conductive material or severed glass fiber bundles on the inner wall of the cutout.

[0055] FIG. 7 illustrates a plurality of singulated components 100 in particular in the form of CSPs (chip-size packages). Each component 100 includes a semiconductor body 10 and a housing 20, wherein the semiconductor body 10 is surrounded by the housing 20 fully circumferentially in lateral directions. In particular, the side surfaces of the semiconductor body 10 are completely covered by the molded body 50 of the housing 20. In a plan view of the carrier layer 91, the molded body 50 at least partly overlaps the connecting layer 92. In particular, in a plan view of the carrier layer 91, the molded body 50 completely overlaps the connecting layer 92 and/or completely overlaps the carrier layer 91. The molded body 50 is thus mechanically carried by the connecting layer 92 and/or by the carrier layer 91.

[0056] In the vertical direction, the molded body 50 terminates flush in particular with the semiconductor body 10. In FIG. 7, the molded body 50 terminates both with the connecting layer 92 and with the carrier layer 91 in the lateral direction. The carrier layer 91 of the housing 20 is subdivided for instance into a first partial region 81 and a second partial region 82, wherein the partial regions 81 and 82 are spatially separated from one another by an intermediate trench 94 in the lateral direction. In this case, the partial regions 81 and 82 each include one or a plurality of connection columns 80 and extend in particular through the connecting layer 92 to a first connection location 71 and to a second connection location 72, respectively, in order to form in each case an electrical contact with the respective connection location 71 and 72. The connection locations 71 and 72 each have a connecting plane with the carrier layer 91, wherein the connecting plane is situated within the connecting layer 92, that is to say not at an edge or on a surface of the connecting layer 92. The connection columns 80 such as are illustrated in FIG. 5 are not illustrated in FIG. 7.

[0057] In plan view the connecting layer 92 overlaps both the first partial region 81 and the second partial region 82 of the carrier layer 91. In particular, the connecting layer 92 includes an intermediate region arranged between the first connection location 71 and the second connection location 72 in the lateral direction, wherein the intermediate region of the connecting layer 92 in plan view laterally bridges the intermediate trench 94 and in this case covers for instance a large portion of the intermediate trench, in particular the complete intermediate trench 94. By virtue of this intermediate region of the connecting layer 92, the component 100 is free of a mechanical weak point in particular at the location of the intermediate trench 94, as a result of which the component 100 overall is formed in a particularly mechanically stable fashion.

[0058] FIG. 8 illustrates a plurality of singulated components in accordance with a further exemplary embodiment of a method for producing a plurality of components 100 in sectional view. This exemplary embodiment substantially corresponds to the exemplary embodiment illustrated in FIG. 7. In contrast thereto, the housing 20 has a side surface having a step, wherein the step is formed by the connecting layer 92 and the carrier layer 91. In this case, the connecting layer 92 projects beyond the carrier layer 91 in the lateral direction. In plan view the partial regions 81 and 82 of the carrier layer 91 are completely covered by the connecting layer 92 and the semiconductor body 10 together. This makes it possible to ensure that the carrier layer 91 is not severed during singulation into a plurality of components 100, as a result of which the risk of a deposition of metal residues, in particular copper residues, for instance on the radiation passage surface is largely prevented. Moreover, a possible migration of copper atoms or copper ions in the direction of the radiation passage surface for instance during operation of the component can be minimized as a result. A risk for instance regarding copper contamination can thus be minimized.

[0059] The exemplary embodiment illustrated in FIG. 9 substantially corresponds to the exemplary embodiment illustrated in FIG. 2. In contrast thereto, the plurality of semiconductor bodies 10 is applied in the form of a common semiconductor composite on the composite carrier 90. In a subsequent step, the semiconductor composite is structured into a plurality of semiconductor bodies 10 arranged alongside one another. In FIG. 10, interspaces between the semiconductor bodies 10 that arose as a result of the structuring are filled or potted with a molded body material. The exemplary embodiment illustrated in FIG. 10 substantially corresponds to the exemplary embodiment illustrated in FIG. 5 for a method for producing a plurality of components 100.

[0060] The exemplary embodiment illustrated in FIG. 11 substantially corresponds to the exemplary embodiment illustrated in FIG. 6. In contrast thereto, it is clarified that the two connection locations 70 of the respective semiconductor body 10 can be exposed by a common cutout 93, wherein, in a subsequent method step, the common cutout 93 can be filled for example by a mask or a separating structure such that two connection columns 80 spatially separated from one another can be formed. In this case, the connection columns 80 can be spaced apart laterally from one another by an intermediate trench 94, which is for instance part of the common cutout 93, wherein the connection columns 80 are each electrically conductively connected for instance to one of the connection locations 70 on the rear side 12 of the semiconductor body 10.

[0061] The formation of a solid instead of temporary composite including the semiconductor body and the composite carrier before the semiconductor body is packaged allows the use of mechanically stable and high-temperature-stable housing materials for a housing for the semiconductor body, in particular the use of a housing material which is highly filled with impurity particles and which can be applied on the semiconductor body efficiently and without great outlay for instance by foil assisted molding.

[0062] While the disclosed embodiments have been particularly shown and described with reference to specific embodiments, it should be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the disclosed embodiments as defined by the appended claims. The scope of the disclosed embodiments is thus indicated by the appended claims and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced.