ELECTRIC DEVICE WAFER

Abstract

A device wafer with functional device structures, comprises a semiconductor substrate (SU) as a carrier wafer, a piezoelectric layer (PL) arranged on the carrier wafer and functional device structures (DS) of a first and a second type realized by a structured metallization on top of the piezoelectric layer (PL). A space charge region is formed near the top surface of the carrier wafer to yield enhanced electrical isolation between functional device structures (DS) of first and second type.

Claims

1. A device wafer with functional device structures, comprising a carrier wafer comprising a semiconductor substrate (SU) a piezoelectric layer (PL) arranged on the carrier wafer a structured metallization on top of the piezoelectric layer; and functional device structures (DS) of a first and a second type realized by the structured metallization; wherein either the semiconductor substrate (SU) is entirely doped and thus low-ohmic or the carrier wafer comprises at least a doped zone.

2. The device wafer of claim 1, wherein the carrier wafer comprises a highly doped semiconductor substrate (SU) and a high-ohmic epitaxial silicon layer deposited on top of the semiconductor substrate.

3. The wafer of claim 1, wherein the semiconductor substrate (SU) is entirely doped to enhance electrical and thermal conductivity of the substrate in view of a respective undoped material wherein a weakly doped and thus high ohmic epitaxial silicon layer (EL) of inverse conductivity is arranged across the entire surface of the carrier wafer between the semiconductor substrate and the piezoelectric layer wherein a space charge region is formed between semiconductor substrate and the high ohmic epitaxial silicon layer.

4. The wafer of claim 3, comprising a first and a second surface region within the carrier wafer, wherein first and second surface region are facing respective device structures (DS) of the first and second type first and second surface regions are isolated against each other by a barrier formed as surrounding frame or as a linearly extending zone the barrier extends from the top surface of the high ohmic epitaxial silicon layer through the layer at least to the top surface of the semiconductor substrate wherein the barrier comprises a dielectric material or a doped zone that is doped inversely with regard to the high ohmic epitaxial silicon layer (EL) the barrier is embedded in.

5. The wafer of claim 1, wherein the semiconductor substrate (SU) comprises a doped well (DW) in the first and/or a second surface region thereof, the doped well facing respective device structures (DS) wherein a first and a second surface region are isolated against each other by a pn junction that forms at the interface between the well and the surrounding semiconductor substrate.

6. The wafer of claim 1, wherein a doped well (DW) is arranged in the first and a second surface region of the high ohmic epitaxial silicon layer (EL) wherein first and second surface regions are isolated against each other by a pn junction that forms at the interface between the doped well (DW) and the high ohmic epitaxial silicon layer (EL).

7. The wafer of claim 1, wherein the barrier surrounds a doped well that comprises one of first or second surface regions.

8. The wafer of claim 1, wherein the functional device structures (DS) of first and second type comprise at least one acoustic track (AT) of a SAW device each.

9. The wafer of claim 1, wherein the device wafer is adapted to apply a BIAS voltage between functional device structures (DS) and the bulk material of the semiconductor wafer (SU) such that a zone at the top surface of the semiconductor wafer is enriched with charge carriers and forms together with the functional device a capacitive element with the intermediate piezoelectric layer as a dielectric.

10. The wafer of claim 9, wherein a first BIAS voltage is applied to first functional device structures and a second BIAS voltage is applied to second functional device structures wherein first and second BIAS voltage are different such that capacitive elements of different capacitance are formed.

11. An electric device, comprising: a carrier wafer comprising a semiconductor substrate (SU) a piezoelectric layer (PL) arranged on the carrier wafer a structured metallization on top of the piezoelectric layer; and functional device structures (DS) of a first and a second type realized by the structured metallization; wherein either the semiconductor substrate (SU) is entirely doped and thus low-ohmic or the carrier wafer comprises at least a doped zone.

Description

[0044] In the following the invention will be explained in more detail with reference to preferred embodiments and accompanying figures. The figures are drawn schematically only and not to scale. Hence, some details of the inventive devices may be depicted enlarged for better understanding. As a consequence, no ratios of any dimension can be taken from the figures.

[0045] FIG. 1 shows a cross-sectional view through part of a device wafer according to the art;

[0046] FIG. 2 shows a device wafer with an epitaxial layer according to an embodiment of the invention;

[0047] FIG. 3 shows a device wafer with doped wells according to another embodiment;

[0048] FIG. 4 shows according to another embodiment a device wafer comprising an epitaxial layer with an isolating barrier arranged in this layer;

[0049] FIG. 5 shows another embodiment of a device wafer with an epitaxial layer comprising a doped zone;

[0050] FIG. 6 shows a device wafer with an epitaxial layer including doped wells therein according to another embodiment;

[0051] FIG. 7 shows, in a top view, device structures of a device wafer that are enclosed by a barrier formed by an isolating material or doped frame-like zone;

[0052] FIG. 8 shows, in a top view, the arrangement of device structures within doped wells;

[0053] FIG. 9 shows, in a top view, a relative arrangement of a frame and device structures;

[0054] FIG. 10 shows, in a top view, a device wafer where only part of the device structures are arranged within a doped well; and

[0055] FIG. 11 shows a cross-sectional view through a device wafer comprising means for applying a BIAS voltage between the device structures and the bulk material of the substrate.

[0056] FIG. 1 shows, in a schematic cross-section, a device wafer according to the art. The device wafer comprises a carrier wafer comprising a silicon substrate SU on top of which a layer system is arranged. Such a layer system may comprise a bonding layer BL and a piezoelectric layer PL. The bonding layer may be produced directly on the silicon substrate SU and usually comprises aluminium nitride and/or silicon oxide. A piezoelectric layer PL is wafer-bonded on top of the bonding layer BL. The piezoelectric layer PL may be a thick wafer that is wafer-bonded to the substrate and then reduced in thickness by a grinding process or by a wafer cleavage followed by a polishing process. On top of the piezoelectric layer PL metallic device structures DS may be applied. As shown in FIG. 1, the device structures may comprise interdigital transducer electrodes of a SAW device like a SAW filter, for example.

[0057] A disadvantage of the shown device wafer is insufficient electric isolation between different device structures DS.

[0058] The device structures DS to be isolated against each other are interfering with each other by capacitive coupling via charge carriers within the substrate SU. To minimize such coupling, a very low doped silicon substrate SU is necessary. As the low doped silicon material is a very clean material having a very low amount of impurities, this material is expensive.

[0059] FIG. 2 shows, in a cross-sectional view, a device wafer according to an embodiment of the invention. In contrast to the known device wafer according to FIG. 1, the device wafer comprises a silicon substrate SU that is weakly doped and provides a certain amount of conductivity. On top of the silicon substrate SU a high-ohmic epitaxial layer EL is applied. Any epitaxial silicon deposition may be used to manufacture this epitaxial layer.

[0060] To provide a space charge region between epitaxial layer EL and silicon substrate SU, different doping is used for both layers. For example, the silicon substrate SU may have a n.sup.+ doping. The epitaxial layer may then be low conductive and, for example p.sup.− doped. But it is not mandatory to have different type of doping for bulk wafer and epitaxial layer.

[0061] The piezoelectric layer PL may be a lithium tantalate layer, for example. But any other piezoelectric material is useful for the invention. The piezoelectric layer may have relatively low thickness of about two times the acoustic wavelength the device is working with. Thicker piezoelectric layers are possible too. However a thicker layer could possibly worsen or complicate a desired interaction of a semiconductor element in the carrier wafer and functional device structures. The epitaxial layer thickness may be in the same order. But a higher or lower thickness may be possible too. In the course of the pn junction between epitaxial layer EL and silicon substrate SU a space charge region forms that isolates the two layers against each other by forming a respective barrier.

[0062] FIG. 3 shows a schematic cross-section of a further embodiment. In this example a very low doped silicon substrate SU is used, for example, an n.sup.− doped silicon. Near the surface and directly under a group of device structures DS a doped well DW is formed by implanting therein a dopant that provides a conductivity of the contrary type. In the example the doped wells comprise a p.sup.− doping. With these doped wells a pn junction is formed at the interface of the doped well and the silicon substrate. A space charge region forms and provides a barrier that prevents charge carriers to leave the doped well. Hence, the doped well provides a perfect isolation of the region opposite to the device structures such that device structures that have to be isolated against each other are arranged opposite to separate and different doped wells DW.

[0063] FIG. 4 shows in a cross-sectional view the method to further improve the isolation between different device structures DS. The improvement can be applied to a device wafer according to FIG. 2. In addition to the pn junction between epitaxial layer EL and silicon substrate SU an isolating frame IF is formed as a barrier within the epitaxial layer EL. The isolating frame IF extends from the top surface of the epitaxial layer EL to the top surface of the silicon substrate SU. It may be manufactured by forming a trench, for example by etching, and then filling up the trench with an isolating material like silicon oxide for example. Any other dielectric may be possible too, the filling of the trenches may be accomplished by applying an isolating dielectric to the entire surface of the epitaxial layer before forming the bonding layer BL. The isolating layer is applied in a thickness that is sufficient to totally fill the trenches. Then the surface may be planarized by grinding or back-etching such that a plane surface remains. Alternatively the trench can remain unfilled to provide an air-filled isolating trench. In this case, it may be advantageous to form the trench during manufacturing of the carrier wafer as a last step before bonding the piezoelectric wafer to the carrier wafer.

[0064] The isolating frame IF surrounds a region opposite to a type of device structures DS that has to be isolated against other device structures. At the area enclosed by the isolating frame IF the surface of the epitaxial layer EL may be exposed. But it is possible too that the isolating material filling the trench is used at the same time to form a bonding layer.

[0065] Alternatively, a bonding layer BL is applied separately on top of the carrier wafer in a usually known manner. Then the piezo layer PL is applied on top of the bonding layer BL and device structures DS are formed on top of the piezoelectric layer. In this embodiment the region of the epitaxial layer EL opposite to a type of device structure DL is isolated against the silicon substrate SU by the pn junction. Two adjacent types of device structures DS are isolated against each other by the isolating frame IF.

[0066] FIG. 5 shows another example where a barrier is formed within the epitaxial layer EL as shown in FIG. 2. But in this embodiment the barrier comprises a frame-like doped zone DF. Alternatively, the barrier may extend linearly between two surface regions of the substrate to be isolated against each other.

[0067] The used doping is contrary to the doping of the remaining epitaxial layer EL such that a pn junction is formed between the low doped epitaxial layer EL and the doped frame-like zone DF. In this example, the doped zone may be n+ doped. The doping may comprise applying a doping mask to the epitaxial layer EL before diffusing in or implanting the dopant and before applying the bonding layer BL. In the doping mask only those regions are exposed where the doped zone DF is to be produced.

[0068] In an embodiment according to FIG. 6 an isolation inverse to the embodiment shown in FIG. 5 used. While the embodiment of FIG. 5 uses doped zones as a barrier between surface regions, doped wells are formed in a surface region within the epitaxial layer EL. This is similar to the embodiment of FIG. 3 with the advantage that the weakly doped and low conductive epitaxial layer EL has only a small thickness over a silicon substrate SU that may be strongly doped. Besides the pn junction between epitaxial layer EL and silicon substrate SU, a further pn junction is formed between the doped wells and the remaining area of the epitaxial layer besides the doped wells. While in the embodiment of FIG. 5 a frame-like zone DF is doped and the epitaxial layer remains undoped, FIG. 6 provides an embodiment where the region opposite to the device structures is conductive and the remaining epitaxial layer is low conductive.

[0069] FIG. 7 shows in a top view onto a device wafer how different device structures can be isolated against each other. As a device structure DS, acoustic tracks AT of a SAW device are formed. By a barrier like isolating frames IF or doped zones DF different areas of the carrier wafer may be isolated against each other. Each isolated area may comprise one or more device structures as shown in the embodiment. While the area shown on the left side of the figure comprises three acoustic tracks AT surrounded by an isolating frame IF or a doped zone DF, the area shown in the middle of the figure comprises two acoustic tracks AT within one enclosing barrier and in the area shown on the right side of the figure only one acoustic track each is surrounded by a respective isolating frame IF or frame-like doped zone DF.

[0070] The frames are formed and arranged between device structures DS that have to be isolated against each other. These may be for example between interdigital transducer electrodes of an input transducer and an output transducer. It is also possible to use this kind of isolation to separate parts within a track from each other, e.g. in DMS structures (IN vs. OUT), to isolate parts of MPR filters (multi-port resonator) or to separate parts of cascaded resonators (e.g. frame/trench below “bus-bar” between tracks of a cascade).

[0071] FIG. 8 is a top view onto a device wafer according to the embodiment shown in FIG. 3 or FIG. 6. The figure shows how the doped wells may be arranged within the surface of the silicon substrate or the epitaxial layer. Similar to the embodiment of FIG. 7, several device structures like acoustic tracks AT may be arranged within one doped well DW. Different doped wells DW may comprise a different number of device structures as shown. Accordingly, the doped wells may comprise different surface areas.

[0072] FIG. 9 shows another arrangement of isolating frames IF or doped frame-like zones DF in a top view on a device wafer according to the invention. On the left side, a frame surrounds and isolates a number of device structures like acoustic tracks AT. Two other acoustic tracks shown in the middle of the figure do not need a surrounding frame, but are isolated against the acoustic tracks on the right part of the figure by a non-surrounding barrier zone that is formed linearly to isolate the not-surrounded device structures against the surrounded and non-surrounded device structures on the right side. As shown in FIG. 9, barriers formed as surrounding frames and linearly extending isolating zones may be present on the same device wafer. But it is also possible that only linearly extending isolating zones are necessary to isolate different regions on top of the silicon substrate, each region being opposite to one or more device structures that need to be isolated against other device structures.

[0073] FIG. 10 shows another possibility to arrange doped wells in a silicon substrate or an epitaxial layer according to the embodiments shown in FIGS. 3 and 6. In FIG. 10 two doped wells DW comprise at least one device structure that is at least one acoustic track AT. Other acoustic tracks are arranged outside the doped wells DW. In spite of not being arranged in the doped well, the device structures or acoustic tracks shown in the left part of FIG. 10 are isolated against the device structures arranged in a doped well by virtue of the pn junction between the doped well and the remaining undoped area outside the doped well DW.

[0074] FIG. 11 shows a cross-section of a device wafer according to another embodiment. A space charge region is formed as a depletion region due to an applied DC BIAS voltage V.sub.DC. The BIAS voltage is applied between device structures DS and the bulk material of the silicon substrate SU, for example by applying a metallized area on the bottom surface of the silicon substrate SU. Because of the BIAS voltage, charge carriers enrich in a zone opposite to the device structures the BIAS voltage is applied to. As a result enhanced conductivity in the region opposite to the device structures is achieved and a capacitance forms between the device structures and the enriched region opposite thereof in the upper surface of the silicon substrate. This capacitance may add to the capacitance of the device that the device structures belong to. By varying the capacitance of the device, properties thereof may be changed. As a consequence of an enhanced static capacitance of an interdigital transducer electrode, the resonance frequency thereof may be tuned. But every other property that is dependent on a capacity may be tuned by such a DC BIAS voltage too.

[0075] Applying of an inverse bias voltage may also lead to a depleted zone below the structure reducing the capacitance in this region and thus, resulting in the same effect of tuning resonance frequency.

[0076] The invention has been explained and depicted with reference to a limited number of embodiments and figures. However the scope of the invention is not restricted to the embodiments. As in most figures only one a single aspect of the invention is shown, it is within the scope of the invention to combine different features shown in different figures. Hence, it is possible to combine a doped well and an isolating or a doped frame. Further, each lateral structuring may be done within an epitaxial layer or within the silicon substrate alternatively or additionally. But in most cases photolithography, epitaxial deposition or doping processes or combinations of them needed before wafer bonding. Other manufacturing steps of structuring and/or doping the carrier wafer may alternatively be done after wafer bonding. E.g. ion implanting can be done through any barrier layer or other layer to form a structures at a depth within the wafer that is depended on the implanting energy e.g. the ion accelerating field. Another step may use the transparency of the piezoelectric layer for a range of wavelengths such that a laser can be used to specifically form a structure that is buried under a covering layer. These buried structures can comprise isolating trenches or any other discontinuity within the carrier wafer.