Method for manufacturing a resistive memory

Abstract

A method for manufacturing a resistive random access memory includes depositing a layer made of an active material of variable electrical resistance on a substrate containing a first electrode, forming a lower electrode; depositing an electrically conductive layer on the active material layer; etching the electrically conductive layer so as to delimit a second electrode, forming an upper electrode, facing the lower electrode; exposing at least one flank of the upper electrode to an ion beam inclined with respect to the normal to the substrate by an angle (α) comprised between 20° and 65°, so as to implant the ions in a portion of the active material layer adjacent to the flank and located under the upper electrode, the ion implantation conditions being chosen so as to create defects in the structure of the active material and to obtain an average implantation width comprised between 5 nm and 10 nm.

Claims

1. Method for manufacturing a resistive random access memory comprising: depositing a layer made of an active material of variable electrical resistance on a substrate containing a first electrode forming a lower electrode; depositing an electrically conductive layer on the active material layer; etching the electrically conductive layer so as to delimit a second electrode forming an upper electrode, facing the lower electrode and exposing at least one flank of the upper electrode and a portion of the top surface of the layer made of an active material to an on beam inclined with respect to the normal to the substrate by an angle (α) comprised between 20° and 65°, so as to implant the ions in a portion of the active material layer adjacent to said flank and located under the upper electrode, the ion implantation conditions being chosen so as to create defects in the structure of the active material and to obtain an average implantation width comprised between 5 nm and 10 nm, wherein the ions are implanted at a dose comprised between 10.sup.13 atoms.Math.cm.sup.−2 and 10.sup.16 atoms.Math.cm.sup.−2 and the ions being metal ions, negatively charged halogen ions, or silicon ions, and wherein only one flank of the upper electrode is exposed to the ion beam so as to form a localized zone of said defects under said one flank.

2. The method according to claim 1, wherein the ion beam is inclined with respect to the normal to the substrate by an angle (α) comprised between 40° and 50°.

3. The method according to claim 1, wherein the ions are implanted with an energy such that the average penetration depth of the ions is located within the active material layer.

4. The method according to claim 1, comprising depositing a protective material on the electrically conductive layer before the etching of the electrically conductive layer.

5. The method according to claim 1, wherein the electrically conductive layer is etched so as to delimit at least two upper electrodes and wherein the angle of inclination α of the ion beam is chosen such that $\mathrm{tan\alpha }\le \frac{S}{h}$ S being the minimum distance separating two electrodes and h the thickness of the electrically conductive layer.

6. The method according to claim 1, wherein the active material is a transition metal oxide.

7. The method according to claim 1, wherein the active material layer implanted with said ions is unetched.

8. Method for manufacturing a resistive random access memory comprising: depositing a layer made of an active material of variable electrical resistance on a substrate containing a first electrode forming a lower electrode, depositing an electrically conductive layer on the active material layer; etching the electrically conductive layer so as to delimit a second electrode forming an upper electrode, facing the lower electrode and after said etching, exposing at least one flank of the upper electrode and a portion of the top surface of the layer made of an active material to an ion beam inclined with respect to the normal to the substrate by an angle (α) comprised between 20° and 65°, so as to implant the ions in a portion of the active material layer adjacent to said flank and located under the upper electrode, the ion implantation conditions being chosen so as to create defects in the structure of the active material and to obtain an average implantation width comprised between 5 nm and 10 nm, wherein the active material layer serves as stop layer during the etching of the electrically conductive layer, an etching chemistry for etching the electrically conductive layer being selective with respect to the active material layer such that the active material layer is not removed by the etching of the electrically conductive layer.

9. The method according to claim 8, wherein the ions are implanted at a dose comprised between 10.sup.13 atoms.Math.cm.sup.−2 and 10.sup.16 atoms.Math.cm.sup.−2.

10. The method according to claim 8, wherein the implanted ions are metal ions, oxygen ions, halogen ions, silicon ions or argon ions.

Description

BRIEF DESCRIPTION OF THE FIGURES

(1) Other characteristics and advantages of the invention will become clear from the description that is given thereof below, for indicative purposes and in no way limiting, with reference to the appended figures, among which:

(2) FIGS. 1A and 1B, described previously, represent two types of OxRAM resistive memory cell according to the prior art;

(3) FIG. 2, described previously, illustrates the ion implantation step of a method for manufacturing an OxRAM memory according to the prior art;

(4) FIG. 3 represents in transversal section a substrate serving as starting point for the method for manufacturing a resistive memory according to the invention;

(5) FIGS. 4A to 4C schematically represent the steps S1 to S3 of a method for manufacturing a resistive memory, according to a preferential embodiment of the invention;

(6) FIG. 5 is a transversal sectional view of the resistive memory cell at the end of the manufacturing method of FIGS. 4A to 4C; and

(7) FIG. 6 illustrates two resistive memory cells spaced apart by a sufficient distance to carry out the ion implantation of FIG. 4C in each of the memory cells.

(8) For greater clarity, identical or similar elements are marked by identical reference signs in all of the figures.

DETAILED DESCRIPTION OF AT LEAST ONE EMBODIMENT

(9) A preferential embodiment of the method for manufacturing a resistive memory according to the invention is described below with reference to FIGS. 3, 4A to 4C and 5. FIG. 3 shows a substrate 300 being able to serve as starting point for the manufacturing method. FIGS. 4A to 4C represent the different steps S1 to S3 of the manufacturing method. Finally, FIG. 5 illustrates the resistive memory obtained at the end of the manufacturing method of FIGS. 4A to 4C.

(10) The resistive memory may comprise a multitude of identical memory cells, for example organised in lines and in columns. Each memory cell comprised a first electrode called lower electrode, a second electrode called upper electrode and an oxide layer arranged between the first and second electrodes. The oxide layer may be common to several memory cells, like one or the other of the lower and upper electrodes. For example, in a matrix of cross-point memory cells, the memory cells of a same row share the same lower electrode (formed by the bit line) and the memory cells of a same column share the same electrode (formed by the word line).

(11) The substrate 300 advantageously comprises a CMOS circuit capable of addressing each memory cell and/or reading the datum recorded in the memory cell, that is the electrical resistance value of the cell. This circuit comprises for example transistors electrically connected to the memory cells by one or more interconnection levels. In FIG. 3 is represented in transversal section uniquely the final interconnection level before the memory cells. It is formed of a dielectric material layer 301 (for example made of SiO.sub.2 or SiN) traversed by the interconnection patterns 302, preferably made of metal (copper, aluminium, metal alloys, etc.) or made of titanium nitride. These interconnection patterns 302 are for example conductive vias or conductive lines and enable the memory cells to be electrically connected to the underlying CMOS circuit.

(12) For reasons of clarity, the resistive memory represented at various stages of its manufacture in FIGS. 3 to 5 only comprises a single memory cell. Consequently, the substrate 300 of FIG. 3 only has a single interconnection pattern 302.

(13) In this preferential embodiment, the interconnection pattern 302 of the substrate 300 constitutes the lower electrode of the memory cell. Alternatively, a metal pad (surrounded by another dielectric layer) may be formed on the interconnection pattern 302 and constitute the lower electrode of the cell.

(14) At step S1 of FIG. 4A, the substrate 300 is successively covered with a layer 410 made of an active material of variable electrical resistance and an electrically conductive layer 420 intended to form the upper electrode of the memory cell. The material of variable electrical resistance of the layer 410 is a dielectric material which can switch from a high resistance state (HRS) to a low resistance state (LRS).

(15) The resistive memory manufactured may be of OxRAM (Oxide-based Random Access Memory), CBRAM (Conductive Bridge Random Access Memory) or HRAM (Hybrid Random Access Memory) type, depending on the nature of the active material used and the upper electrode.

(16) Preferably, the active material is an oxide, and more preferentially a transition metal oxide, for example hafnium oxide (HfO.sub.2), titanium oxide (TiO.sub.2), tantalum oxide (Ta.sub.2O.sub.5), nickel oxide (NiO) or zinc oxide (ZnO). The memory is then of OxRAM type.

(17) The dielectric layer 410 may also be composed of several superimposed oxide sub-layers (for example of Al.sub.2O.sub.3/HfO.sub.2 type).

(18) The electrically conductive layer 420 is formed of one or more superimposed conductive materials, preferably chosen from metals (platinum, titanium, tantalum, hafnium, zirconium), titanium nitride (TiN), tantalum nitride (TaN), doped polysilicon and metal silicides. In the example represented in FIG. 3, the conductive layer 420 is comprised of a stack of a titanium sub-layer 421 and a titanium nitride sub-layer 422.

(19) The thickness of the active material layer 410 is comprised between 1 nm and 20 nm, whereas the thickness of the conductive layer 420 is comprised between 5 nm and 200 nm.

(20) Advantageously, the conductive layer 420 is covered with a protective layer 430, for example made of SiO.sub.2 or SiN. The aim of this protective layer 430 is to protect the upper face of the upper electrode during the later step of ion implantation (cf. FIG. 4C). Thus, it has a sufficient thickness to absorb the totality of the ions which will be directed to the upper face of the electrode.

(21) FIG. 4B represents a step S2 during which the conductive layer 420 is etched to delimit the upper electrode 440 of the memory cell. The conductive layer 420 is etched in mesa shape of which the flanks are advantageously vertical. The etching technique used is preferably a highly anisotropic dry etching, such as RIE (Reactive Ion Etching).

(22) The protective layer 430 advantageously serves as hard mask during the etching of the conductive layer 420. The hard mask is for example formed by optical or extreme UV photolithography and etching of the protective layer 430, then the conductive layer 420 is etched through this hard mask.

(23) In the preferential embodiment of FIG. 4B, the conductive layer 420 is etched while leaving intact the underlying oxide layer 410. This may be obtained by choosing an etching chemistry that is selective with respect to the oxide used. The etching chemistry depends on the materials constituting the conductive layer 420 and the oxide layer 410. In the particular case of a conductive layer 420 made of TiN or Ti and an oxide layer 410 made of HfO.sub.2, the etching chemistry used to etch the conductive layer 420 selectively with respect to the layer 410 may be Cl.sub.2/HBr.

(24) The oxide layer 410 then serves as etching stop layer. Preserving the oxide layer 410 during the etching step S2 makes it possible to protect the lower electrode 302 from the later step of ion implantation (FIG. 4C).

(25) Conversely, in an alternative embodiment, the oxide layer 410 is etched at the same time as the conductive layer 420.

(26) Finally, at step S3 of FIG. 4C, an ion implantation step is carried out so as to create a zone of defects localised on an edge of the memory cell, that is to say, on an edge of the lower electrode 302—oxide layer 410—upper electrode 440 stack. To do so, one of the vertical flanks of the upper electrode 440 (the right flank in the example of the figure) is exposed to an oblique ion beam 450. The ion beam 450 is inclined with respect to the perpendicular to the substrate 300 by an angle α comprised between 20° and 65°.

(27) Due to the inclination of the beam 450, the ions arriving at the base of the flank penetrate into the oxide layer 410 and generate structural defects in this oxide layer.

(28) The effect desired by the creation of this localised zone of defects is the confinement of the conductive filament within this same zone, during the operation of the memory cell. Indeed, as mentioned in the U.S. Pat. No. 8,872,268, the structural defects generated by the implantation of metal ions, oxygen ions, negatively charged halogen ions (F.sup.−, CL.sup.−, etc.), silicon ions or argon ions in the oxide layer favour the formation of the conductive filament. The defects may notably be metal, silicon or oxygen atoms in interstitial position, metal or silicon atoms in substitutional position or oxygen vacancies. In the case of metal ions, it would seem that the atoms implanted constitute a part of the conductive filament of the memory cell.

(29) The conductive filament is formed for the first time during the process of “forming” the memory cell. The “forming” of a cell consists in a reversible breakdown of the oxide, that is to say that the oxide switches from an insulating state to a conducting state. After this breakdown of the oxide, the electrical resistance of the active material can witch from a low resistance (conductive) state (LRS) to a high resistance (insulating) state (HRS), by operations of erasing and writing. During an erasing and writing cycle, the conductive filament is broken then reconstructed. However, it does not disappear totally, nor change zone in the oxide layer located between the electrodes (it is reconstructed in the spot where it is formed initially, during “forming”).

(30) Unlike the method according to the prior art, the manufacturing method of FIGS. 4A-4C does not require any mask for the implantation step S3. All the surface of the substrate may be exposed to the ion beam 450 under oblique incidence, which greatly simplifies the manufacture of the OxRAM memory. The delimitation of the zone of defects located under the upper electrode results, as is described hereafter, uniquely from a shading effect of the upper electrode.

(31) FIG. 5 schematically represents the state of the memory cell immediately after the ion implantation step S3.

(32) An upper part of the protective layer 430, a lateral part of the protective layer 430 and a lateral part of the upper electrode 440, on the side of the exposure to the ion beam 450 (here on the right side), have been implanted (not all of these parts have the same thickness, because the density of the materials varies). The protective layer 430 prevents the ions from reaching the surface of the upper electrode 440, where the contact will be made. Thus, thanks to the protective layer 430, the quality of the electrical contact made on the upper electrode is not diminished by the ion implantation and the formation of structural defects in the upper electrode 440.

(33) Besides, it is possible to distinguish two distinct zones in the oxide layer 410: a first zone 411 implanted by ions and a second zone 412, adjacent to the first zone 411, but devoid of ions. The ion-free second zone 412 is located in the shade of the upper electrode 440 with respect to the ion beam 450. Conversely, the first implanted zone 411 corresponds to the non-shaded zones of the oxide layer 410. The first zone 411 of the oxide layer extends outside of the upper electrode 440 (on the left and the right of the electrode) and comprises a portion 413 located under the edge of the upper electrode 440.

(34) In other words, under the upper electrode, only the portion 413 of the oxide layer 410 immediately adjacent to the exposed flank of the upper electrode 440 is implanted, whereas the large majority of the oxide layer located under the upper electrode 440 is not impacted by the ion implantation.

(35) The shape and the dimensions (width and depth) of the implanted zone 413 depend on the implantation parameters (nature of the ion, dose, angle and energy). The average width of the implanted portion 413 here designates the transversal dimension measured (on average) parallel to the plane of the substrate 300 and located in the plane of transversal section of FIG. 5. The depth of the implanted portion 413 is the dimension measured perpendicularly to the plane of the substrate 300.

(36) Preferably, these conditions will be chosen so as to obtain an average implantation width of the same order of magnitude (or even a little more) than the assumed size of the filament, i.e. typically between 5 nm and 10 nm. Advantageously, an angle α equal to 45° will be chosen and the implantation energy will be modulated to affect the implantation width.

(37) In this preferential embodiment (where only the conductive layer 420 is etched, not the oxide layer 410), the ion implantation energy is preferably chosen (for a given type of ions) so that the average penetration depth of the ions is located within the oxide layer 410. Thus, the ions virtually do not penetrate into the lower electrode 302 and do not risk altering its electrical behaviour.

(38) The ion implantation dose is, for its part, advantageously comprised between 10.sup.13 atoms.Math.cm.sup.−2 and 10.sup.16 atoms.Math.cm.sup.−2. Such a dose has the effect of decreasing the forming voltage of the memory cell. For example, a dose of silicon ions implanted in a layer of HfO.sub.2 comprised between 2.Math.10.sup.15 cm.sup.−2 and 5.Math.10.sup.15 cm.sup.−2 makes it possible to decrease the forming voltage by more than 1 V.

(39) FIG. 6 is a perspective view to two adjacent memory cells formed on the substrate 300. The two memory cells advantageously share the same lower electrode 302 (formed for example by a line) and the same oxide layer 410. They each have on the other hand a mesa-shaped upper electrode 440. The different upper electrodes have preferably been formed simultaneously from a single conductive layer 420, as described previously in relation with FIG. 4B. The different memory cells or points of an OxRAM memory may thus be delimited uniquely by their upper electrode 440.

(40) The upper electrodes 440 advantageously have a width I comprised between 80 nm and 300 nm, and a length L (in the perpendicular direction) comprised between 80 nm and 300 nm. To attain such dimensions, advanced lithography techniques, such as electron beam (e-beam) lithography, are not necessary.

(41) The upper electrodes 440 of these two consecutive cells in the memory plane are spaced apart by a given distance S. The upper electrode of a memory cell must not form an obstacle to the ion beam directed to another memory cell. This condition on the angle of implantation a may be approximated by the following relationship:

(42) $\mathrm{tan\alpha }\le \frac{S}{h}$

(43) where h is the thickness of the upper electrode and S is the separation distance between the two electrodes.

(44) Preferably, the ion beam is inclined with respect to the exposed flank of the electrode by an angle α comprised between 40° and 50°, for example 45°. This second range, more restricted, makes it possible to obtain simultaneously localised zones of dimensions of the same order of magnitude as the thickness of the oxide layer and a high integration density of the cells of the memory.

(45) Thus, this manufacturing method makes it possible to limit considerably the formation zone of the conductive filament in the memory cell, also called active zone, thanks to an ion implantation localised under an edge of the upper electrode. As an example, the surface area of the active zone of a memory cell having an oxide layer of 5 nm thickness and implanted according to an angle of 45° is equal to 1000 nm.sup.2 (L=200 nm×I.sub.2=5 nm).

(46) As a comparison, the active zone of a memory cell with sides measuring 200 nm and in which no zone of defects is provided has a surface area of more than 40,000 nm.sup.2, i.e. at least 40 times more than the implanted memory cell. To obtain the same surface area of active zone with the conventional manufacturing method, it would be necessary to delimit an upper electrode with sides measuring around 30 nm, which is complex and costly to obtain in photolithography.

(47) The manufacturing method may also comprise, after the ion implantation step S3, a step of encapsulating the memory cell, for example with silicon nitride (SiN) or silicon dioxide (SiO.sub.2), and a step of making contact on the upper face of the upper electrode, for example by means of an interconnection pad (via) or an interconnection level (line).

(48) Since it is not necessary to reduce the dimensions of the upper electrode to obtain a small active zone, there are few constraints for making the contact on the upper electrode. The manufacturing method according to the invention thus makes easier the end of integration of the memory.

(49) Many variants and modifications of the manufacturing method described above will become clear to those skilled in the art. In particular, at step S3 of FIG. 4C, the substrate 300 may be rotationally driven during implantation of the ions. This has the effect of exposing all the flanks of the upper electrode 440 to the inclined ion beam 450 and, consequently, to form defects at the periphery of the memory cell (rather than on a single edge of the memory cell), that is to say on all the edges of the memory cell. The implantation step S3 may thus be executed more easily. The surface area of the active zone will however be greater.

(50) Finally, although it is not necessary to make the contact on the upper electrode, it is also possible to remove the protective layer 430 having served as etching mask after the implantation step S3.